会员体验
专利管家（专利管理）
工作空间（专利管理）
风险监控（情报监控）
数据分析（专利分析）
侵权分析（诉讼无效）
联系我们
交流群
官方交流：
QQ群： 891211   
微信请扫码    >>>
现在联系顾问~
下载
著录项
PDF全文
热词
    • 44. 发明申请
      US20030099253A1 Apparatus and method for arbitrating data transmission amongst devices having SMII standard 审中-公开
    • Apparatus and method for arbitrating data transmission amongst devices having SMII standard
    • 用于在具有SMII标准的设备之间仲裁数据传输的装置和方法
    • US20030099253A1
    • 2003-05-29
    • US10058431
    • 2002-01-28
    • Corecess Inc.
    • Mee Sun Kim
    • H04J003/02
    • H04L12/422 , H04L7/0008
    • Disclosed relates to an apparatus and method for arbitrating data transmission amongst at least a Media Access Control (MAC) device and at least a Physical Layer (PHY) device having a Serial Media Independent Interface (SMII), respectively, which can remove a restriction of a distance between the MAC and PHY devices on a printed circuit board (PCB) and prevent a transmission error due to a data transmission delay. The apparatus for arbitrating data transmission amongst a first and a second devices corresponding to the MAC and PHY devices having SMII standard, respectively, the apparatus comprising at least one buffering means for buffering transmission data input from the first device to be resynchronized a predetermined number of times in a unit of a segment and outputting the resynchronized transmission data to the second device.
    • 本发明涉及一种用于在至少媒体访问控制（MAC）设备和至少具有串行媒体独立接口（SMII）的物理层（PHY）设备的至少媒体访问控制（MAC）设备之间仲裁数据传输的装置和方法，其可以消除对 在印刷电路板（PCB）上的MAC和PHY设备之间的距离，并防止由于数据传输延迟引起的传输错误。 用于在与具有SMII标准的MAC和PHY设备相对应的第一和第二设备之间仲裁数据传输的设备，所述设备包括至少一个缓冲装置，用于缓冲从第一设备输入的要重新同步的传输数据以预定数量的 次数，并将再同步的传输数据输出到第二设备。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 46. 发明授权
      US6104732A Integrated signal routing circuit 失效
    • Integrated signal routing circuit
    • 集成信号路由电路
    • US6104732A
    • 2000-08-15
    • US33866
    • 1998-03-03
    • Trevor Pearman
    • Trevor Pearman
    • H04L12/42 , H04J3/02
    • H04L12/422
    • An integrated routing circuit that provides serial-to-parallel and parallel-to-serial data conversion, and data transmission over various types of media including coaxial, twisted-pair, and fiber optic media. The integrated routing circuit has two receivers, three multiplexers, a reclocking circuit, a serial to parallel converter, a parallel to serial converter, a serial transmitter, an output controller, and a parallel transmitter. The circuits that form the integrated routing circuit are arranged so that either serial or parallel data sources can be selected from a plurality of inputs to the integrated routing circuit and so that various routing paths can be established for the selected sources. The selected routing path is established via the use of control words.
    • 集成路由电路，提供串行到并行和并行到串行数据转换，以及通过各种类型的介质（包括同轴，双绞线和光纤介质）进行数据传输。 集成路由电路具有两个接收器，三个多路复用器，再生电路，串并转换器，并行到串行转换器，串行发送器，输出控制器和并行发送器。 构成集成路由电路的电路被布置成使得可以从集成路由电路的多个输入中选择串行或并行数据源，并且可以为所选择的源建立各种路由路径。 选择的路由路径是通过使用控制字建立的。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 48. 发明授权
      US5602882A Digital jitter attenuator using selection of multi-phase clocks and auto-centering elastic buffer 失效
    • Digital jitter attenuator using selection of multi-phase clocks and auto-centering elastic buffer
    • 数字抖动衰减器采用多相时钟选择和自动定心弹性缓冲器
    • US5602882A
    • 1997-02-11
    • US588902
    • 1996-01-19
    • Ramon S. Co , Lance K. Lee
    • Ramon S. Co , Lance K. Lee
    • H04J3/06 , H04L7/033 , H04L12/42 , H04L7/00
    • H04J3/0626 , H04L12/422 , H04J3/0632
    • A jitter attenuator receives data and a receive clock extracted from an input data stream. A transmit clock is generated for retransmitting the data. The transmit clock has less jitter than the receive clock but has the same average frequency. An elastic buffer or FIFO is necessary to buffer the data. The receive clock is divided into a series of write clocks for writing data into the elastic buffer, and the transmit clock is also divided into a series of read clocks for reading data from the elastic buffer. A series of multi-phase clocks is used to generate the transmit clock. The multi-phase clocks all have the same frequency but are offset in phase from one another. A phase selector, under control of a counter, selects one of the multi-phase clocks to be the transmit clock. The counter is incremented or decremented by a phase comparator. The phase comparator compares the phase of one of the write clocks to the phase of one of the read clocks. The counter is incremented when the phase of the write clock lags the read clock, selecting a multi-phase clock with a more retarded phase, but the counter is decremented when the write clock leads the read clock, selecting a multi-phase clock with a more advanced phase. Thus the phase of the transmit clock is adjusted by the phase comparison of the write and read clocks for the elastic buffer. The elastic buffer is forced to half-full by comparing a write and read clock that are separated by half the capacity of the buffer. The phase, rather than the frequency, is adjusted, eliminating the feedback to an external VCO, allowing the jitter attenuator to be integrated on a single silicon substrate.
    • 抖动衰减器接收从输入数据流提取的数据和接收时钟。 生成发送时钟用于重发数据。 发送时钟的抖动小于接收时钟，但平均频率相同。 需要一个弹性缓冲区或FIFO来缓冲数据。 接收时钟被分成一系列用于将数据写入弹性缓冲器的写时钟，并且发送时钟也被分成用于从弹性缓冲器读取数据的一系列读时钟。 一系列多相时钟用于产生传输时钟。 多相时钟都具有相同的频率，但相位偏移。 在计数器的控制下，相位选择器选择多相时钟之一作为发送时钟。 计数器由相位比较器递增或递减。 相位比较器将一个写入时钟的相位与其中一个读取时钟的相位进行比较。 当写时钟的相位滞后于读时钟时，计数器递增，选择具有更延迟相位的多相时钟，但当写时钟引导读时钟时，计数器递减，选择多相时钟 更先进的阶段。 因此，通过弹性缓冲器的写入和读取时钟的相位比较来调整发送时钟的相位。 通过比较分离为缓冲器容量的一半的写入和读取时钟，将弹性缓冲区强制为半满。 相位而不是频率被调整，消除了对外部VCO的反馈，允许抖动衰减器集成在单个硅衬底上。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 50. 发明授权
      US5502750A Digital jitter attenuator using selection of multi-phase clocks and auto-centering elastic buffer for a token ring network 失效
    • Digital jitter attenuator using selection of multi-phase clocks and auto-centering elastic buffer for a token ring network
    • 数字抖动衰减器采用多相时钟选择和自动定心弹性缓冲区，用于令牌环网络
    • US5502750A
    • 1996-03-26
    • US259910
    • 1994-06-15
    • Ramon S. Co , Lance K. Lee
    • Ramon S. Co , Lance K. Lee
    • H04J3/06 , H04L7/033 , H04L12/42 , H04L7/00
    • H04J3/0626 , H04L12/422 , H04J3/0632
    • A jitter attenuator receives data and a receive clock extracted from an input data stream. A transmit clock is generated for retransmitting the data. The transmit clock has less jitter than the receive clock but has the same average frequency. An elastic buffer or FIFO is necessary to buffer the data. The receive clock is divided into a series of write clocks for writing data into the elastic buffer, and the transmit clock is also divided into a series of read clocks for reading data from the elastic buffer. A series of multi-phase clocks is used to generate the transmit clock. The multi-phase clocks all have the same frequency but are offset in phase from one another. A phase selector, under control of a counter, selects one of the multi-phase clocks to be the transmit clock. The counter is incremented or decremented by a phase comparator. The phase comparator compares the phase of one of the write clocks to the phase of one of the read clocks. The counter is incremented when the phase of the write clock lags the read clock, selecting a multi-phase clock with a more retarded phase, but the counter is decremented when the write clock leads the read clock, selecting a multi-phase clock with a more advanced phase. Thus the phase of the transmit clock is adjusted by the phase comparison of the write and read clocks for the elastic buffer. The elastic buffer is forced to half-full by comparing a write and read clock that are separated by half the capacity of the buffer. The phase, rather than the frequency, is adjusted, eliminating the feedback to an external VCO, allowing the jitter attenuator to be integrated on a single silicon substrate.
    • 抖动衰减器接收从输入数据流提取的数据和接收时钟。 生成发送时钟用于重发数据。 发送时钟的抖动小于接收时钟，但平均频率相同。 需要一个弹性缓冲区或FIFO来缓冲数据。 接收时钟被分成一系列用于将数据写入弹性缓冲器的写时钟，并且发送时钟也被分成用于从弹性缓冲器读取数据的一系列读时钟。 一系列多相时钟用于产生传输时钟。 多相时钟都具有相同的频率，但相位偏移。 在计数器的控制下，相位选择器选择多相时钟之一作为发送时钟。 计数器由相位比较器递增或递减。 相位比较器将一个写入时钟的相位与其中一个读取时钟的相位进行比较。 当写时钟的相位滞后于读时钟时，计数器递增，选择具有更延迟相位的多相时钟，但当写时钟引导读时钟时，计数器递减，选择多相时钟 更先进的阶段。 因此，通过弹性缓冲器的写入和读取时钟的相位比较来调整发送时钟的相位。 通过比较分离为缓冲器容量的一半的写入和读取时钟，将弹性缓冲区强制为半满。 相位而不是频率被调整，消除了对外部VCO的反馈，允许抖动衰减器集成在单个硅衬底上。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
每页展示10个专利
每页展示10个专利
每页展示20个专利
每页展示50个专利
每页展示100个专利

IPRDB

最新中国发明专利 最新美国发明专利 技术领域 专利库 专利分类库 国际专利分类库

热门服务

会员版试用 API 数据接口 找代理 知嘟嘟专利交易 排行榜 大学排行榜 专利百科

关于我们

平台介绍 战略合作 网站地图

友情链接

知嘟嘟专利交易 国家知识产权局 中国商标网

联系方式


©2019-2023 上海吉码数字技术有限公司 版权所有，并保留所有权利 沪ICP备20016256号-6 沪公网安备31011702005475号