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1. 发明授权

US5602882A Digital jitter attenuator using selection of multi-phase clocks and auto-centering elastic buffer 失效
标题翻译：数字抖动衰减器采用多相时钟选择和自动定心弹性缓冲器
公开(公告)号：US5602882A
公开(公告)日：1997-02-11
申请号：US588902
申请日：1996-01-19
申请人： Ramon S. Co , Lance K. Lee
发明人： Ramon S. Co , Lance K. Lee
IPC分类号： H04J3/06 , H04L7/033 , H04L12/42 , H04L7/00
CPC分类号： H04J3/0626 , H04L12/422 , H04J3/0632
摘要： A jitter attenuator receives data and a receive clock extracted from an input data stream. A transmit clock is generated for retransmitting the data. The transmit clock has less jitter than the receive clock but has the same average frequency. An elastic buffer or FIFO is necessary to buffer the data. The receive clock is divided into a series of write clocks for writing data into the elastic buffer, and the transmit clock is also divided into a series of read clocks for reading data from the elastic buffer. A series of multi-phase clocks is used to generate the transmit clock. The multi-phase clocks all have the same frequency but are offset in phase from one another. A phase selector, under control of a counter, selects one of the multi-phase clocks to be the transmit clock. The counter is incremented or decremented by a phase comparator. The phase comparator compares the phase of one of the write clocks to the phase of one of the read clocks. The counter is incremented when the phase of the write clock lags the read clock, selecting a multi-phase clock with a more retarded phase, but the counter is decremented when the write clock leads the read clock, selecting a multi-phase clock with a more advanced phase. Thus the phase of the transmit clock is adjusted by the phase comparison of the write and read clocks for the elastic buffer. The elastic buffer is forced to half-full by comparing a write and read clock that are separated by half the capacity of the buffer. The phase, rather than the frequency, is adjusted, eliminating the feedback to an external VCO, allowing the jitter attenuator to be integrated on a single silicon substrate.
摘要翻译：抖动衰减器接收从输入数据流提取的数据和接收时钟。生成发送时钟用于重发数据。发送时钟的抖动小于接收时钟，但平均频率相同。需要一个弹性缓冲区或FIFO来缓冲数据。接收时钟被分成一系列用于将数据写入弹性缓冲器的写时钟，并且发送时钟也被分成用于从弹性缓冲器读取数据的一系列读时钟。一系列多相时钟用于产生传输时钟。多相时钟都具有相同的频率，但相位偏移。在计数器的控制下，相位选择器选择多相时钟之一作为发送时钟。计数器由相位比较器递增或递减。相位比较器将一个写入时钟的相位与其中一个读取时钟的相位进行比较。当写时钟的相位滞后于读时钟时，计数器递增，选择具有更延迟相位的多相时钟，但当写时钟引导读时钟时，计数器递减，选择多相时钟更先进的阶段。因此，通过弹性缓冲器的写入和读取时钟的相位比较来调整发送时钟的相位。通过比较分离为缓冲器容量的一半的写入和读取时钟，将弹性缓冲区强制为半满。相位而不是频率被调整，消除了对外部VCO的反馈，允许抖动衰减器集成在单个硅衬底上。

2. 发明授权

US5502750A Digital jitter attenuator using selection of multi-phase clocks and auto-centering elastic buffer for a token ring network 失效
标题翻译：数字抖动衰减器采用多相时钟选择和自动定心弹性缓冲区，用于令牌环网络
公开(公告)号：US5502750A
公开(公告)日：1996-03-26
申请号：US259910
申请日：1994-06-15
申请人： Ramon S. Co , Lance K. Lee
发明人： Ramon S. Co , Lance K. Lee
IPC分类号： H04J3/06 , H04L7/033 , H04L12/42 , H04L7/00
CPC分类号： H04J3/0626 , H04L12/422 , H04J3/0632
摘要： A jitter attenuator receives data and a receive clock extracted from an input data stream. A transmit clock is generated for retransmitting the data. The transmit clock has less jitter than the receive clock but has the same average frequency. An elastic buffer or FIFO is necessary to buffer the data. The receive clock is divided into a series of write clocks for writing data into the elastic buffer, and the transmit clock is also divided into a series of read clocks for reading data from the elastic buffer. A series of multi-phase clocks is used to generate the transmit clock. The multi-phase clocks all have the same frequency but are offset in phase from one another. A phase selector, under control of a counter, selects one of the multi-phase clocks to be the transmit clock. The counter is incremented or decremented by a phase comparator. The phase comparator compares the phase of one of the write clocks to the phase of one of the read clocks. The counter is incremented when the phase of the write clock lags the read clock, selecting a multi-phase clock with a more retarded phase, but the counter is decremented when the write clock leads the read clock, selecting a multi-phase clock with a more advanced phase. Thus the phase of the transmit clock is adjusted by the phase comparison of the write and read clocks for the elastic buffer. The elastic buffer is forced to half-full by comparing a write and read clock that are separated by half the capacity of the buffer. The phase, rather than the frequency, is adjusted, eliminating the feedback to an external VCO, allowing the jitter attenuator to be integrated on a single silicon substrate.
摘要翻译：抖动衰减器接收从输入数据流提取的数据和接收时钟。生成发送时钟用于重发数据。发送时钟的抖动小于接收时钟，但平均频率相同。需要一个弹性缓冲区或FIFO来缓冲数据。接收时钟被分成一系列用于将数据写入弹性缓冲器的写时钟，并且发送时钟也被分成用于从弹性缓冲器读取数据的一系列读时钟。一系列多相时钟用于产生传输时钟。多相时钟都具有相同的频率，但相位偏移。在计数器的控制下，相位选择器选择多相时钟之一作为发送时钟。计数器由相位比较器递增或递减。相位比较器将一个写入时钟的相位与其中一个读取时钟的相位进行比较。当写时钟的相位滞后于读时钟时，计数器递增，选择具有更延迟相位的多相时钟，但当写时钟引导读时钟时，计数器递减，选择多相时钟更先进的阶段。因此，通过弹性缓冲器的写入和读取时钟的相位比较来调整发送时钟的相位。通过比较分离为缓冲器容量的一半的写入和读取时钟，将弹性缓冲区强制为半满。相位而不是频率被调整，消除了对外部VCO的反馈，允许抖动衰减器集成在单个硅衬底上。

3. 发明授权

US06266799B1 Multi-phase data/clock recovery circuitry and methods for implementing same 失效
标题翻译：多相数据/时钟恢复电路及其实现方法
公开(公告)号：US06266799B1
公开(公告)日：2001-07-24
申请号：US08967087
申请日：1997-11-10
申请人： Lance K. Lee , Jyn-Bang Shyu , David Y. Wang
发明人： Lance K. Lee , Jyn-Bang Shyu , David Y. Wang
IPC分类号： G06F1750
CPC分类号： H03L7/0991 , H03L7/0814 , H03L7/089 , H03L7/091 , H04L7/0337
摘要： Disclosed is a data/clock recovery system for use in a high speed networking transceiver units. The data/clock recovery system includes a four phase sampler circuit that is configured to receive a data input waveform and produce output data. A transition detect circuit that is arranged to receive the output data produced by the four phase sampler circuit. The transition detect circuit is configured to determine whether a clock is leading or lagging the data input waveform. A counter for shifting the clock if the clock is determined by the transition detect circuit to either be leading or lagging the data input waveform, such that the shifting is configured to synchronize the clock and the data input waveform. A decoder that receives control signals from the counter, such that the decoder generates a selection signal. The data/clock recovery system further including a multiplexer for selecting four predetermined clock phases in response to the selection signal generated by the decoder. Preferably, the four predetermined clock phases are continually shifted by the counter if the clock and the data input waveform are not synchronized.
摘要翻译：公开了一种用于高速网络收发器单元的数据/时钟恢复系统。数据/时钟恢复系统包括被配置为接收数据输入波形并产生输出数据的四相采样器电路。一种转换检测电路，被配置为接收由四相采样器电路产生的输出数据。转移检测电路被配置为确定时钟是引导还是滞后数据输入波形。如果时钟由转换检测电路确定为使数据输入波形引导或滞后，则使时钟转换的计数器，使得移位被配置为使时钟和数据输入波形同步。一个从计数器接收控制信号的解码器，使得解码器产生选择信号。数据/时钟恢复系统还包括一个多路复用器，用于响应由解码器产生的选择信号来选择四个预定时钟相位。优选地，如果时钟和数据输入波形不同步，则四个预定时钟相位被计数器连续移位。

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