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1. 发明申请

US20100174843A1 SYSTEM AND METHOD FOR OPERATING A BUS SYSTEM 有权
标题翻译：用于操作总线系统的系统和方法
公开(公告)号：US20100174843A1
公开(公告)日：2010-07-08
申请号：US12725932
申请日：2010-03-17
申请人： Martin HUBER , Hendrik Koehler
发明人： Martin HUBER , Hendrik Koehler
IPC分类号： G06F13/28
CPC分类号： H04L25/4904 , G05B2219/15072 , H03M5/12 , H04L12/403 , H04L12/4135 , H04L47/30 , H04L2012/6435
摘要： A bus system for the real-time communication of a superordinate unit with one or more subordinate units is used for exchanging address and data information via a bus. For the rapid exchange of messages, further fields are provided between the fields for the address and data information.
摘要翻译：用于通过一个或多个从属单元实时通信上级单元的总线系统用于通过总线交换地址和数据信息。为了快速交换消息，在地址和数据信息的字段之间提供了进一步的字段。

2. 发明授权

US07586933B2 Network comprising an interconnecting network and several network nodes that are coupled to said interconnecting network 失效
标题翻译：网络包括互连网络和耦合到所述互连网络的若干网络节点
公开(公告)号：US07586933B2
公开(公告)日：2009-09-08
申请号：US10510390
申请日：2003-04-04
申请人： Ing Ralf Belschner , Bernd Hedenetz , Christopher Temple , Anton Schedl , Josef Berwanger , Martin Peller , Thomas Führer , Arnold Millsap , Thomas Forest , Gregor Pokorny , Peter Fuhrmann
发明人： Ing Ralf Belschner , Bernd Hedenetz , Christopher Temple , Anton Schedl , Josef Berwanger , Martin Peller , Thomas Führer , Arnold Millsap , Thomas Forest , Gregor Pokorny , Peter Fuhrmann
IPC分类号： H04L12/413
CPC分类号： H04L12/44 , H03M13/09 , H03M13/43 , H04J3/0652 , H04J3/0682 , H04L12/6418 , H04L2012/6435 , H04L2012/644 , H04L2012/6459
摘要： The invention concerns a network comprising an interconnecting network and several network nodes that are coupled to said interconnecting network and are designed to adapt their local communication time schedule to the communication time schedule of at least one other network mode, prior to being integrated as active network nodes. A network node to be integrated checks the activity of other network nodes and if no activity is identified, sends out positional messages for other network nodes, said message being fixed by predetermination in its communication time schedule. If a network node cannot be integrated as a reference node, it can only be integrated as an active node if it adapts its local communication time schedule to that of the reference node after receiving positional messages and if a check as to whether its own communication time schedule agrees with the communication time schedules of at least some of the active network nodes proves positive.
摘要翻译：本发明涉及一种包括互连网络和若干网络节点的网络，所述网络节点被耦合到所述互连网络，并且被设计成在被集成为主动网络之前将其本地通信时间调度调整到至少一个其他网络模式的通信时间表节点。要集成的网络节点检查其他网络节点的活动，如果没有识别活动，则发送其他网络节点的位置消息，所述消息在其通信时间表中通过预先确定。如果网络节点不能集成为参考节点，则只有在接收到位置消息后，如果网络节点将其本地通信时间表调整为参考节点的时间表，则只能将其集成为主动节点，并且如果检查其自身的通信时间至少有一些活动网络节点的通信时间表表明方案是正确的。

3. 发明授权

US06484201B1 Method and apparatus to test an isochronous data transport 失效
标题翻译：测试同步数据传输的方法和装置
公开(公告)号：US06484201B1
公开(公告)日：2002-11-19
申请号：US09418092
申请日：1999-10-14
申请人： John I. Garney , Brent S. Baxter
发明人： John I. Garney , Brent S. Baxter
IPC分类号： G06F1300
CPC分类号： G06F13/36 , H04L12/6418 , H04L2012/6435 , H04L2012/6464
摘要： A method includes setting a contention scheme for an asynchronous bus such that the contention delay of isochronous transactions on the bus is bounded, and establishing an isochronous interface between at least two devices, the isochronous interface supporting an X-T contract. A number of isochronous transactions and corresponding return transactions delivered across the bus is measured during a specified time interval.
摘要翻译：一种方法包括设置异步总线的竞争方案，使得总线上的等时事务的竞争延迟受到限制，并且在至少两个设备之间建立同步接口，支持X-T合同的等时接口。在指定的时间间隔内测量在总线上传送的许多等时事务和相应的返回事务。

4. 发明授权

US5960002A Defragmentation method and arrangement 失效
标题翻译：碎片整理方法和布置
公开(公告)号：US5960002A
公开(公告)日：1999-09-28
申请号：US770359
申请日：1996-12-20
申请人： Lars Ramfelt , Christer Bohm , Per Lindgren
发明人： Lars Ramfelt , Christer Bohm , Per Lindgren
IPC分类号： H04J3/00 , H04L12/28 , H04L12/64 , H04L12/417
CPC分类号： H04L12/6418 , H04L12/2852 , H04L2012/6435 , H04L2012/6451 , H04L2012/6456 , H04L2012/6459
摘要： The present invention relates to a defragmentation method and arrangement for increasement of the average block size of free tokens in the nodes of a DTM (Dynamic Synchronous Transfer Mode) network. The defragmentation comprises defining a home node for each token at network startup in such way that the tokens sharing the same home node will always define at least partly a continuous slot range, sending back free tokens to home nodes when a significant time has passed and, merging two or more slot-consecutive tokens with the same slot range into a single token when existing in the free pool of a node. The defragmentation can be realized in a central or a distributed token management scheme.
摘要翻译：本发明涉及一种用于增加DTM的节点中的自由令牌的平均块大小的碎片整理方法和装置（+ E，uns D + EE ynamic Synchronous + E，uns T + EE ransfer + E，uns M + EE ode）网络。碎片整理包括在网络启动时为每个令牌定义家庭节点，使得共享相同家庭节点的令牌将总是至少部分地定义连续的时隙范围，当有重要时间已经过去时将免费令牌发送回归属节点，当存在于节点的空闲池中时，将具有相同时隙范围的两个或更多个时隙连续令牌合并成单个令牌。碎片整理可以在中央或分布式令牌管理方案中实现。

5. 发明授权

US5428613A Method for transmitting either data or voice in an allocated TDM slot 失效
标题翻译：在分配的TDM时隙中发送数据或语音的方法
公开(公告)号：US5428613A
公开(公告)日：1995-06-27
申请号：US984777
申请日：1992-12-03
申请人： Mark G. Spiotta , Juan C. Santiago
发明人： Mark G. Spiotta , Juan C. Santiago
IPC分类号： H04L12/64 , H04J3/12
CPC分类号： H04L12/6418 , H04L2012/6421 , H04L2012/6435 , H04L2012/6459 , H04L2012/6481 , H04Q2213/13098 , H04Q2213/13174 , H04Q2213/13216 , H04Q2213/13292 , H04Q2213/13299
摘要： Data transfer for a time division multiplex (TDM) bus in a communication system that includes a plurality of communication nodes wherein each communication node is allocated at least one time slot of the TDM bus can utilize the following protocol to improve flexibility. When a communication node has an information packet to transmit, it must determine whether it is changing from a first information packet type to a second information packet type message. If a change from transmitting a first information packet type to transmitting a second information packet type is determined, an information type transition message is transmitted via the allocated time slot during a first frame cycle. Upon receiving the information type transition message, at least one other communication node stores the information type transition message. The transmitting communication node then transmits a second information packet type message during a subsequent frame cycle wherein a receiving communication node interprets the second information packet type message as a second information packet type.
摘要翻译：在包括多个通信节点的通信系统中的时分多路复用（TDM）总线的数据传输，其中每个通信节点被分配至TDM总线的至少一个时隙可以利用以下协议来提高灵活性。当通信节点具有要发送的信息分组时，它必须确定它是否从第一信息分组类型改变到第二信息分组类型消息。如果确定从发送第一信息分组类型到发送第二信息分组类型的改变，则在第一帧周期期间经由所分配的时隙来发送信息类型转换消息。在接收到信息类型转换消息时，至少一个其他通信节点存储信息类型转换消息。然后，发送通信节点在随后的帧周期期间发送第二信息分组类型消息，其中接收通信节点将第二信息分组类型消息解释为第二信息分组类型。

6. 发明授权

US08335241B2 System and method for operating a bus system 有权
公开(公告)号：US08335241B2
公开(公告)日：2012-12-18
申请号：US12725932
申请日：2010-03-17
申请人： Martin Huber , Hendrik Koehler
发明人： Martin Huber , Hendrik Koehler
IPC分类号： H04J3/06
CPC分类号： H04L25/4904 , G05B2219/15072 , H03M5/12 , H04L12/403 , H04L12/4135 , H04L47/30 , H04L2012/6435
摘要： A bus system for the real-time communication of a superordinate unit with one or more subordinate units is used for exchanging address and data information via a bus. For the rapid exchange of messages, further fields are provided between the fields for the address and data information.

7. 发明申请

US20030147416A1 Extendible asynchronous and synchronous interface bus for broadband access 失效
标题翻译：可扩展的异步和同步接口总线，用于宽带接入
公开(公告)号：US20030147416A1
公开(公告)日：2003-08-07
申请号：US10072329
申请日：2002-02-06
申请人： TranSwitch Corporation
发明人： John F. Gilsdorf , Yung-Yuan Yang
IPC分类号： H04L012/403
CPC分类号： H04L12/6418 , H04L2012/6435
摘要： Apparatus for simultaneously transferring synchronous and asynchronous signals among broadband access devices includes a data bus, a clock bus, and a plurality of control lines which are used to indicate the type of data being carried on the bus. According to the methods of the invention, data is transferred on the bus in a repeating frame having a plurality of slots, each slot being defined as one bus clock cycle. Each slot may contain a synchronous or asynchronous data signal and one or more of the control lines are asserted during the slot time of the data to indicate the type of data. Two embodiments are provided. One utilizes a 25 MHz clock bus and a repeating frame of three hundred thirty-six slots. The other utilizes a 75 MHz clock bus and a repeating frame of one thousand eight slots.
摘要翻译：用于在宽带接入设备之间同时传送同步和异步信号的设备包括数据总线，时钟总线以及用于指示在总线上承载的数据类型的多个控制线。根据本发明的方法，数据在具有多个时隙的重复帧中在总线上传送，每个时隙被定义为一个总线时钟周期。每个时隙可以包含同步或异步数据信号，并且在数据的时隙时间期间断言一个或多个控制线以指示数据的类型。提供了两个实施例。一个使用25MHz时钟总线和三百三十六个时隙的重复帧。另一个使用75MHz时钟总线和一千八个时隙的重复帧。

8. 发明授权

US06320863B1 Backplane architecture for dynamic synchronous transfer mode 有权
标题翻译：用于动态同步传输模式的背板架构
公开(公告)号：US06320863B1
公开(公告)日：2001-11-20
申请号：US09464032
申请日：1999-12-15
申请人： Lars Håkan Ramfelt
发明人： Lars Håkan Ramfelt
IPC分类号： H04L1256
CPC分类号： H04L12/2852 , H04J3/07 , H04J2203/0026 , H04J2203/0044 , H04J2203/0046 , H04J2203/0071 , H04J2203/0073 , H04L12/422 , H04L12/43 , H04L12/6418 , H04L2012/6435 , H04L2012/6451 , H04L2012/6456 , H04L2012/6459 , H04Q11/0478
摘要： A backplane for a dynamic synchronous transfer mode network that comprises two dual ring topologies having opposite fiber direction. The ring topologies has a plurality of disjointed segments that permits the simultaneous transmission of signals in the same time slots over the disjointed segments.
摘要翻译：用于动态同步传输模式网络的背板，包括具有相反纤维方向的两个双环拓扑。环形拓扑具有多个不相交的段，其允许在不相交段上的相同时隙中同时传输信号。

9. 发明授权

US5825752A Local area network transferring data using isochronous and asynchronous channels 失效
标题翻译：局域网使用等时和异步信道传输数据
公开(公告)号：US5825752A
公开(公告)日：1998-10-20
申请号：US719511
申请日：1996-09-25
申请人： Junichi Fujimori , Tatsutoshi Abe
发明人： Junichi Fujimori , Tatsutoshi Abe
IPC分类号： H04L12/28 , H04L12/18 , H04L12/40 , H04L12/64 , H04L29/06 , H04Q11/04 , H04M3/42
CPC分类号： H04L12/40058 , H04L12/40065 , H04L12/40117 , H04L12/6418 , H04L29/06 , H04L65/1069 , H04L65/4076 , H04L67/104 , H04L12/18 , H04L2012/6435 , H04L2012/6443 , H04L2012/6448 , H04L2012/6456 , H04L29/06027
摘要： In a network system, a plurality of nodes are communicable with one another to exchange information and to transfer data, and a bus is provided for connection to the nodes and for configuration of logical paths to logically link one node to another node so as to secure transfer of the data. Each node has at least one port which is allocated for accessing the bus and which is classified into four types of an isochronous talker, an isochronous listener, a multicast talker and a multicast listener. The nodes are allocated to bind isochronous channel numbers or multicast channel numbers to respective isochronous or multicast talkers and listeners in a manner so as to maximize efficiency of the network.
摘要翻译：在网络系统中，多个节点可彼此通信以交换信息和传送数据，并且提供总线用于连接到节点并且用于配置逻辑路径以逻辑地将一个节点链接到另一个节点，以便安全传输数据。每个节点至少有一个端口被分配用于访问总线，并且分为四种类型的同步话音器，等时听话器，多播讲话者和组播听众。这些节点被分配以将同步信道号或多播信道号绑定到相应的同步或多播讲话者和收听者，以便最大化网络的效率。

10. 发明授权

US5708779A Multimedia system and method of controlling data transfer between a host system and a network adapter using a DMA engine 失效
标题翻译：使用DMA引擎控制主机系统和网络适配器之间的数据传输的多媒体系统和方法
公开(公告)号：US5708779A
公开(公告)日：1998-01-13
申请号：US719053
申请日：1996-09-24
申请人： Michael J. Graziano , Jon F. Hauris , Daniel L. Stanley
发明人： Michael J. Graziano , Jon F. Hauris , Daniel L. Stanley
IPC分类号： G06F13/00 , G06F13/12 , H04L12/42 , H04L12/433 , H04L12/56 , H04L12/64 , H04L29/06 , G06F3/00
CPC分类号： H04L49/90 , G06F13/128 , H04L12/6418 , H04L29/06 , H04L49/901 , H04L49/9031 , H04L49/9057 , H04L49/9063 , H04L49/9089 , H04L63/0428 , H04L63/083 , H04L12/433 , H04L2012/6435 , H04L2012/6448 , H04L2012/6489 , H04L29/06027
摘要： A communications adapter receives and transmits simultaneously packet and/or isochronous data between two interfaces; a network and a host bus system. The adapter stores the isochronous and packet data in receive and transmit queues configured in a FDDI RAM buffer. A controller manages the transfers of the data into and out of the queues. A local bus interacts with the system to provide descriptors of addresses in the system for transfers of data out of the queues to the system or the network. The controller is programmable to provide a variable threshold for the transfer of data between the queues and the system or the network. A systems interface unit handles the transfer of data to/from the system and allows data to bypass the queues and directly access the system or the network.
摘要翻译：通信适配器在两个接口之间同时接收并发送分组和/或等时数据; 网络和主机总线系统。适配器将等时和分组数据存储在配置在FDDI RAM缓冲区中的接收和发送队列中。控制器管理数据进出队列的数据。本地总线与系统交互以提供系统中的地址描述符，用于将数据从队列传送到系统或网络。控制器是可编程的，以提供用于队列与系统或网络之间的数据传输的可变阈值。系统接口单元处理向/从系统传输数据，并允许数据绕过队列并直接访问系统或网络。

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