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    • 1. 发明申请
    • System and method for seamless multiplexing of embedded bitstreams
    • 嵌入式比特流无缝复用的系统和方法
    • US20040258104A1
    • 2004-12-23
    • US10600555
    • 2003-06-20
    • Microsoft Corporation
    • Jin Li
    • H04J003/02
    • H04N19/34H04N19/13H04N19/132H04N19/146H04N19/154H04N19/17H04N19/18H04N19/184H04N19/187H04N19/63H04N19/70
    • A nullseamless multiplexer,null as described herein, provides a flexible and efficient system and method for multiplexing embedded coded bitstreams. Further, unlike the conventional JPEG 2000 standard, the seamless multiplexer is capable of decoding multiplexed encoded bitstreams without the need to use a demultiplexing aide as overhead in the encoded signal. In general, the seamless multiplexer provides a novel approach for multiplexing code block bitstreams by using a nulldecoder pointer,null for multiplexing multiple embedded bitstreams without the use of a demultiplexing aide. Consequently, the seamless multiplexer not only reduces any multiplexing overhead, but also allows much smaller granularity of access in reshaping the compressed input signal. In addition, in one embodiment, the seamless multiplexer also uses dependencies between coefficient blocks to further improve overall compression efficiency.
    • 如本文所描述的,“无缝多路复用器”提供了用于复用嵌入式编码比特流的灵活且有效的系统和方法。 此外,与传统的JPEG 2000标准不同,无缝多路复用器能够对多路复用的编码比特流进行解码,而不需要在编码信号中使用解复用技术作为开销。 通常,无缝多路复用器提供了一种用于通过使用“解码器指针”复用码块比特流的新颖方法,用于复用多个嵌入的比特流而不使用解复用辅助。 因此,无缝多路复用器不仅减少了任何复用开销,而且在重新压缩压缩输入信号时也允许更小的访问粒度。 此外,在一个实施例中,无缝多路复用器还使用系数块之间的依赖关系,以进一步提高整体压缩效率。
    • 2. 发明申请
    • Method and apparatus for multiplexing high-speed packet data transmission with voice/data transmission
    • 用于多路复用高速分组数据传输与语音/数据传输的方法和装置
    • US20040240401A1
    • 2004-12-02
    • US10884120
    • 2004-07-02
    • Serge WilleneggerStein A. Lundby
    • H04J003/02H04L012/66
    • H04B7/264H04W52/34
    • Techniques for transmitting voice/data and packet data services such that packet data transmissions have less impact on voice/data transmissions. In one aspect, voice/data and packet data can be multiplexed within a transmission interval such that the available resources are efficiently utilized. In another aspect, the amount of variation in the total transmit power from a base station is controlled to reduce degradation to transmissions from this and other base stations. In a specific method for concurrently transmitting a number of types of data, a first data type (e.g., voice, overhead, and some data) and a second data type are respectively processed in accordance with first and second signal processing schemes to generate first and second payloads, respectively. First and second partitions are then defined in a transmission interval. The first and second payloads are time multiplexed into the first and second partitions, respectively, and the multiplexed payloads are transmitted.
    • 用于发送语音/数据和分组数据服务的技术,使得分组数据传输对语音/数据传输的影响较小。 在一个方面,语音/数据和分组数据可以在传输间隔内复用,使得有效利用可用资源。 在另一方面,来自基站的总发射功率的变化量被控制以减少来自该基站和其它基站的传输的劣化。 在用于同时发送多种类型的数据的特定方法中,根据第一和第二信号处理方案分别处理第一数据类型(例如,语音,开销和一些数据)和第二数据类型,以产生第一和第 第二有效载荷。 然后在传输间隔中定义第一和第二分区。 第一和第二有效载荷分别被时分复用到第一和第二分区中,并且传输多路复用的有效载荷。
    • 3. 发明申请
    • Image reproduction apparatus
    • 图像再现装置
    • US20040233938A1
    • 2004-11-25
    • US10809379
    • 2004-03-26
    • Kenichiro Yamauchi
    • H04J003/02
    • H04N21/2365H04N21/4305H04N21/4334H04N21/4344H04N21/4347
    • An image reproduction apparatus that can select arbitrary video/audio data among plural MPEG transport streams which have been recorded in a storage medium at different times, and can re-multiplex the selected video and audio data into one MPEG transport stream to be reproduced. When a MPEG transport stream is recorded in the storage medium, a reference clock is generated from Program_clock_reference in the stream, and then the MPEG transport stream is recorded with the generated reference clock being attached thereto as an Arrived Time Stamp. At the start of reproduction, a common PCR is generated on the basis of the ATS value to be used as a video/audio PCR. Further, as for PTS and DTS, the difference value in the ATS of packets having PTS and DTS in the same video/audio is calculated, and the video or audio is outputted so as not to vary the difference value.
    • 可以在已经记录在存储介质中的不同时间的多个MPEG传输流中选择任意的视频/音频数据的图像再现装置,并且可以将所选择的视频和音频数据重新复用为要再现的一个MPEG传输流。 当MPEG传输流被记录在存储介质中时,从流中的Program_clock_reference生成参考时钟,然后以生成的参考时钟的形式记录MPEG传送流作为到达时间戳。 在再现开始时,根据要用作视频/音频PCR的ATS值产生公共PCR。 此外,对于PTS和DTS,计算出具有相同视频/音频中的PTS和DTS的分组的ATS中的差值,并且输出视频或音频以便不改变差值。
    • 4. 发明申请
    • Multiplexer
    • 复用器
    • US20040131089A1
    • 2004-07-08
    • US10471732
    • 2004-03-05
    • Aritomo UemuraSeiji KozakiKazup KuboHiroshi Ichibangase
    • H04J003/02
    • H04L25/4923H04J3/047H04J3/0685
    • A multiplexer includes an encoder (4). The encoder (4) includes: flip-flop circuits (4a, 4b) that output two signals having a transmission rate of B/2 at a frequency of B/2, while holding signals of each signal; an adder (4f) that adds the respective signals output from the flip-flop circuits (4a, 4b) and outputs the added signal; and a delay unit (4e) that delays the signal output from the flip-flop circuit (4b) by the time of 1/B, with respect to the signal output from the flip-flop circuit (4a), and outputs the signal delayed to the adder (4f).
    • 复用器包括编码器(4)。 编码器(4)包括:在保持每个信号的信号的同时,以B / 2的频率输出具有B / 2的传输速率的两个信号的触发器电路(4a,4b) 加法器(4f),其将从触发器电路(4a,4b)输出的各个信号相加并输出相加的信号; 以及延迟单元(4e),相对于从触发器电路(4a)输出的信号,将从触发器电路(4b)输出的信号延迟1 / B的时间,并输出延迟的信号 到加法器(4f)。
    • 7. 发明申请
    • Information processing system, information processing apparatus, and information processing method
    • 信息处理系统,信息处理装置和信息处理方法
    • US20040057448A1
    • 2004-03-25
    • US10653962
    • 2003-09-04
    • Canon Kabushiki Kaisha
    • Atsushi Nakamura
    • H04L012/54H04J003/02
    • H04L12/40052H04L49/90
    • There is disclosed a system which makes efficient data transfer using two channels of an IEEE1394 bus. A system of this invention is an information processing system including first and second devices, wherein the first device comprises transmission means for transmitting one request which designates a plurality of data storage areas to the second device, the second device comprises completion notifying means for notifying the first device of completion of a data communication for one of the plurality of data storage areas, and in accordance with the notification of completion of the data communication for one of the plurality of data storage areas, the transmission means transmits one request which designates a data storage area, a data communication for which is not complete, and a new data storage area for the data storage area, the data communication for which is complete, to the second device.
    • 公开了一种使用IEEE1394总线的两个通道进行有效数据传输的系统。 本发明的系统是包括第一和第二设备的信息处理系统,其中第一设备包括用于将指定多个数据存储区域的一个请求发送到第二设备的传输装置,第二设备包括完成通知装置, 第一装置,用于完成多个数据存储区域中的一个数据存储区域的数据通信,并且根据多个数据存储区域之一的数据通信完成通知,发送装置发送一个指定数据的请求 存储区域,其不完整的数据通信以及数据存储区域的新数据存储区域,其数据通信完成到第二设备。
    • 8. 发明申请
    • Multi-stage multiplexing chip set having switchable forward/reverse clock relationship
    • 多级复用芯片组具有可切换的正向/反向时钟关系
    • US20040037332A1
    • 2004-02-26
    • US10602227
    • 2003-06-24
    • Mohammad NejadAli Ghiasi
    • H04J003/02
    • H04J3/0685H04J3/04H04J3/0629H04L7/0008
    • A multi-stage bit stream multiplexer that divides multiplexing functions between two or more integrated circuits. The first integrated circuit receives 16 bit streams to produce 4 output bits streams with a nominal data rate of 10 GBPS. A second integrated circuit multiplexes the 4 streams and to a bit stream with a data rate of 40 GBPS. The first IC is made in a standard CMOS process while the second IC is made using processes that support higher switching rates. The first IC produces a source-centered double data rate forward transmit clock from a reference clock selectable from either a crystal oscillator, a voltage controlled oscillator using a loop clock from the receive side of the bit stream multiplexer or a reverse clock generated by the second IC. The reverse clock can be selected as the source of the reference either by default, or in response to a specific condition.
    • 多级比特流多路复用器,其分割两个或多个集成电路之间的复用功能。 第一个集成电路接收16位流,产生标称数据速率为10 GBPS的4个输出位流。 第二集成电路将4个流和数据速率40GBPS的比特流复用。 第一个IC采用标准CMOS工艺制造,而第二个IC采用支持更高开关速率的工艺制造。 第一个IC从可以从晶体振荡器,使用来自位流多路复用器的接收侧的环形时钟的压控振荡器或由第二个时钟产生的反向时钟选择的参考时钟产生源中心的双数据速率正向传输时钟 我知道了。 默认情况下也可以选择反向时钟作为参考源,或响应特定条件。
    • 10. 发明申请
    • M:N path protection
    • M:N路径保护
    • US20040022279A1
    • 2004-02-05
    • US10603614
    • 2003-06-26
    • ALCATEL
    • Walter KailbachKerstin SkerraHans-Jorg JakelMartin Huck
    • H04J003/02
    • H04J3/085H04J2203/0051H04J2203/006
    • An 1:n or m:n path protection mechanism is provided. Rather than defining an automatic protection protocol, use is made of the existing tandem connection monitoring function, tandem connection reverse defect indication, and tandem connection trail trace identifier. Upon detection of a failure on the working path segment, the occurrence of this failure is communicated to the far end node by inserting forced RDI into the tandem connection as long as the failure persists. In the case of more than one protected paths, the failed path is identified by means of the unique trail trace identifier received on the protection path. In the case of several protection paths, one network node is defined as slave node which has to follow the switch-over initiated by the master node and choose the same protection path as the master node. Preferably, a combination of two timers enables return from failure condition to normal operation.
    • 提供1:n或m:n路径保护机制。 而不是定义自动保护协议,而是使用现有的串联连接监视功能,串联连接反向缺陷指示和串联连接跟踪跟踪标识符。 在检测到工作路径段上的故障时,只要故障仍然存在,就将该故障的发生通过插入强制的RDI传送到远端节点。 在多于一个受保护的路径的情况下,通过在保护路径上接收到的唯一路径跟踪标识符来识别故障路径。 在多个保护路径的情况下,一个网络节点被定义为从节点,必须遵循由主节点发起的切换,并选择与主节点相同的保护路径。 优选地,两个定时器的组合使得能够从故障状态返回到正常操作。