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41. 发明授权

US06660647B1 Method for processing surface of sample 失效
标题翻译：样品表面处理方法
公开(公告)号：US06660647B1
公开(公告)日：2003-12-09
申请号：US09646012
申请日：2001-01-11
申请人： Tetsuo Ono , Takafumi Tokunaga , Tadashi Umezawa , Motohiko Yoshigai , Tatsumi Mizutani , Tokuo Kure , Masayuki Kojima , Takashi Sato , Yasushi Goto
发明人： Tetsuo Ono , Takafumi Tokunaga , Tadashi Umezawa , Motohiko Yoshigai , Tatsumi Mizutani , Tokuo Kure , Masayuki Kojima , Takashi Sato , Yasushi Goto
IPC分类号： H01L2100
CPC分类号： H01J37/32082 , H01L21/32136 , H01L21/32139
摘要： A surface processing method of a sample having a mask layer that does not contain carbon as a major component formed on a substance to be processed, the substance being a metal, semiconductor and insulator deposited on a silicon substrate, includes the steps of installing the sample on a sample board in a vacuum container, generating a plasma that consists of a mixture of halogen gas and adhesive gas inside the vacuum container, applying a radio frequency bias voltage having a frequency ranging from 200 kHz to 20 MHz on the sample board, and controlling a periodic on-off of the radio frequency bias voltage with an on-off control frequency ranging from 100 Hz to 10 kHz.
摘要翻译：具有在被处理物质上形成的不含有碳作为主要成分的掩模层的样品的表面处理方法，该物质是沉积在硅基板上的金属，半导体和绝缘体，该物质包括如下步骤：在真空容器中的样品板上，在真空容器内产生由卤素气体和粘合气体的混合物构成的等离子体，在样品板上施加频率范围为200kHz〜20MHz的射频偏置电压，以从100Hz到10kHz的开关控制频率来控制射频偏置电压的周期性的断开。

42. 发明授权

US06525336B1 Superfine electronic device and method for making same 失效
标题翻译：超细电子设备及其制作方法
公开(公告)号：US06525336B1
公开(公告)日：2003-02-25
申请号：US08463761
申请日：1995-06-05
申请人： Seiichi Kondo , Yasuo Wada , Tsuyoshi Uda , Tokuo Kure , Tsuneo Ichiguchi , Shinji Okazaki , Yoshimasa Murayama
发明人： Seiichi Kondo , Yasuo Wada , Tsuyoshi Uda , Tokuo Kure , Tsuneo Ichiguchi , Shinji Okazaki , Yoshimasa Murayama
IPC分类号： H01L2906
CPC分类号： G11C13/025 , B82Y10/00 , B82Y15/00 , G11C11/34 , G11C19/00 , G11C2216/08 , H01L49/006 , H03K19/02
摘要： A superfine electronic device is disclosed, which is constructed by atomic fine lines having a structure in which a plurality of atoms are arranged on one or a plurality of straight lines, in a ring shape or on curves with a size of atomic level, and which includes elements for doping electrons and holes. Using these atomic fine lines, it is possible to integrate semiconductor elements utilizing pn junctions at an atomic level with a high density. A groove having a sufficiently small size is formed in an insulating film disposed on a substrate. Then, atoms or molecules are supplied on the substrate and in the groove, which and are heated to a temperature sufficiently high for moving the atoms or molecules during or after the supply thereof to form a quantum fine line at edge portions of the groove.
摘要翻译：公开了一种超细电子器件，其由具有多个原子排列在一个或多个直线上的原子细线构成，具有环形或具有原子级尺寸的曲线，并且其中包括用于掺杂电子和空穴的元件。使用这些原子细线，可以利用高密度的原子级的pn结集成半导体元件。在设置在基板上的绝缘膜中形成具有足够小尺寸的凹槽。然后，原子或分子被提供在衬底和沟槽中，并且被加热到足够高的温度以在其供给期间或之后移动原子或分子，以在槽的边缘部分处形成量子细线。

43. 发明授权

US5061645A Method of manufacturing a bipolar transistor 失效
公开(公告)号：US5061645A
公开(公告)日：1991-10-29
申请号：US498489
申请日：1990-03-26
申请人： Kazuo Nakazato , Tohru Nakamura , Masatoshi Matsuda , Takao Miyazaki , Tokuo Kure , Takahiro Okabe , Minoru Nagata
发明人： Kazuo Nakazato , Tohru Nakamura , Masatoshi Matsuda , Takao Miyazaki , Tokuo Kure , Takahiro Okabe , Minoru Nagata
IPC分类号： H01L21/8222 , H01L21/033 , H01L21/3205 , H01L21/331 , H01L27/06 , H01L29/423 , H01L29/70 , H01L29/72 , H01L29/73 , H01L29/732 , H01L29/735
CPC分类号： H01L29/66272 , H01L21/033 , H01L29/42304 , H01L29/72 , H01L29/732 , H01L29/735
摘要： A method of manufacturing a bipolar transistor semiconductor device wherein the active regions of a transistor are formed in an opening provided in an insulating film, electrodes are led out by a polycrystalline silicon film formed on the insulating film, and the upper surfaces of the emitter and base electrodes and the exposed surface of the insulating film are substantially even.

44. 发明授权

US4860071A Semiconductor memory using trench capacitor 失效
标题翻译：半导体存储器采用沟槽电容器
公开(公告)号：US4860071A
公开(公告)日：1989-08-22
申请号：US157129
申请日：1988-02-10
申请人： Hideo Sunami , Tokuo Kure , Atsushi Hiraiwa , Yasuo Wada
发明人： Hideo Sunami , Tokuo Kure , Atsushi Hiraiwa , Yasuo Wada
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L29/945 , H01L27/10829
摘要： A memory is disclosed which uses a microcapacitor as a data storage portion. The microcapacitor uses as its main electrode surface the side wall of a first trench formed on a semiconductor substrate, and is fabricated by diffusing an impurity from a second diffusion trench adjacent to the first trench by setting the shapes and diffusion conditions of the first and second trenches so that the tip of the diffusion layer reaches the side wall of the first trench. The capacitor uses the diffusion layer as one of the electrodes. An insulating film is deposited on the side wall of the first trench and an electrode as the other electrode of the capacitor is deposited on this insulating film. The memory can reduce a leakage current between memory cells by connecting the capacitor to a transistor fabricated in the same semiconductor substrate, and can be formed within a limited space.
摘要翻译：公开了一种使用微电容器作为数据存储部分的存储器。微电容器使用形成在半导体衬底上的第一沟槽的侧壁作为其主电极表面，并且通过将第一和第二沟槽的形状和扩散条件设定为第一和第二沟槽的形状和扩散条件，沟槽，使得扩散层的尖端到达第一沟槽的侧壁。电容器使用扩散层作为电极之一。绝缘膜沉积在第一沟槽的侧壁上，并且作为电容器的另一个电极的电极沉积在该绝缘膜上。存储器可以通过将电容器连接到在同一半导体衬底中制造的晶体管来减小存储器单元之间的漏电流，并且可以在有限的空间内形成。

45. 发明授权

US07049243B2 Surface processing method of a specimen and surface processing apparatus of the specimen 有权
标题翻译：试样的表面处理方法和试样的表面处理装置
公开(公告)号：US07049243B2
公开(公告)日：2006-05-23
申请号：US10754594
申请日：2004-01-12
申请人： Tetsuo Ono , Yasuhiro Nishimori , Takashi Sato , Naoyuki Kofuji , Masaru Izawa , Yasushi Goto , Ken Yoshioka , Hideyuki Kazumi , Tatsumi Mizutani , Tokuo Kure , Masayuki Kojima , Takafumi Tokunaga , Motohiko Yoshigai
发明人： Tetsuo Ono , Yasuhiro Nishimori , Takashi Sato , Naoyuki Kofuji , Masaru Izawa , Yasushi Goto , Ken Yoshioka , Hideyuki Kazumi , Tatsumi Mizutani , Tokuo Kure , Masayuki Kojima , Takafumi Tokunaga , Motohiko Yoshigai
IPC分类号： H01L21/302
CPC分类号： H01J37/32082 , H01L21/32136
摘要： A plasma processing method for etching a sample having a gate oxide film which generates a plasma in a vacuum chamber using electromagnetic waves, applies an rf bias power to the sample, turns off the rf bias power before a charged voltage of the sample reaches a breakdown voltage of the gate oxide film, turns on the rf bias power after the charged voltage of the sample has substantially dropped and repeats the turning on and off of the rf bias power to process the sample. The off-time is set at least longer than the on-time, and the plasma is generated by continuously supplying power to enable generation of the plasma during the repeated turning on and off of the rf bias power.
摘要翻译：一种用于蚀刻具有使用电磁波在真空室中产生等离子体的栅极氧化膜的样品的等离子体处理方法，对样品施加rf偏置功率，在样品的充电电压达到击穿之前关断rf偏置功率栅极氧化膜的电压在样品的充电电压基本上下降之后导通rf偏置功率，并重复rf偏置功率的导通和截止以处理样品。关断时间至少比导通时间长，并且通过连续供电以在反复打开和关闭rf偏置功率期间产生等离子体而产生等离子体。

46. 发明授权

US06492277B1 Specimen surface processing method and apparatus 有权
标题翻译：试样表面处理方法和装置
公开(公告)号：US06492277B1
公开(公告)日：2002-12-10
申请号：US09393893
申请日：1999-09-10
申请人： Tetsuo Ono , Yasuhiro Nishimori , Takashi Sato , Naoyuki Kofuji , Masaru Izawa , Yasushi Goto , Ken Yoshioka , Hideyuki Kazumi , Tatsumi Mizutani , Tokuo Kure , Masayuki Kojima , Takafumi Tokunaga , Motohiko Yoshigai
发明人： Tetsuo Ono , Yasuhiro Nishimori , Takashi Sato , Naoyuki Kofuji , Masaru Izawa , Yasushi Goto , Ken Yoshioka , Hideyuki Kazumi , Tatsumi Mizutani , Tokuo Kure , Masayuki Kojima , Takafumi Tokunaga , Motohiko Yoshigai
IPC分类号： H01L21302
CPC分类号： H01J37/32082 , H01L21/32136
摘要： Electrical damage to semiconductor elements in the plasma etching thereof is suppressed. In processing of a fine pattern by plasma etching, the high frequency power supply to be applied to the specimen is turned off before the charge potential at a portion of the pattern reaches the breakdown voltage of the gate oxide film which is interconnected to said fine pattern, and then the high frequency power supply is turned on when the charge potential at the portion of the pattern drops substantially. This on and off control is effected in a repetitive mode of operation.
摘要翻译：抑制其等离子体蚀刻对半导体元件的电气损伤。在通过等离子体蚀刻处理精细图案时，在图案的一部分处的电荷电位达到与所述精细图案互连的栅极氧化膜的击穿电压之前，施加到样本的高频电源被关断，然后当图案部分的电荷电位基本上下降时，高频电源被接通。该开启和关闭控制以重复的操作模式进行。

47. 发明授权

US5969357A Scanning electron microscope and method for dimension measuring by using the same 失效
公开(公告)号：US5969357A
公开(公告)日：1999-10-19
申请号：US979327
申请日：1997-11-26
申请人： Hideo Todokoro , Kenji Takamoto , Tadashi Otaka , Fumio Mizuno , Satoru Yamada , Sadao Terakado , Katsuhiro Kuroda , Ken Ninomiya , Tokuo Kure
发明人： Hideo Todokoro , Kenji Takamoto , Tadashi Otaka , Fumio Mizuno , Satoru Yamada , Sadao Terakado , Katsuhiro Kuroda , Ken Ninomiya , Tokuo Kure
IPC分类号： G01Q30/02 , G01B15/00 , G01B15/04 , G01Q30/04 , H01J37/26
CPC分类号： G01B15/00 , G01B15/04 , H01J2237/2448 , H01J2237/24495 , H01J2237/281
摘要： An electron beam which can transmit through part of a specimen and can reach a portion not exposing to the electron beam is irradiated and a scanning image is obtained on the basis of a signal secondarily generated from a portion irradiated with the electron beam. Dimension-measuring start and end points are set on the scanning image and a dimension therebetween is measured. A cubic model is assumed, the cubic model is modified so as to match the scanning image, and dimension measurement is carried out on the basis of a modified cubic model.

48. 发明授权

US5352324A Etching method and etching apparatus therefor 失效
标题翻译：蚀刻方法及其蚀刻装置
公开(公告)号：US5352324A
公开(公告)日：1994-10-04
申请号：US136947
申请日：1993-10-18
申请人： Yasushi Gotoh , Tokuo Kure , Hiroshi Kawakami , Masanori Katsuyama , Kiyomi Yagi , Hiromichi Enami
发明人： Yasushi Gotoh , Tokuo Kure , Hiroshi Kawakami , Masanori Katsuyama , Kiyomi Yagi , Hiromichi Enami
IPC分类号： H01L21/3065 , H01L21/311 , H01L21/3213 , H01L21/8242 , H01L21/306 , B44C1/22 , C03C15/00 , C03C25/06
CPC分类号： H01L21/30655 , H01J37/32706 , H01L21/3065 , H01L21/31116 , H01L21/32137 , H01L27/10861 , H01J2237/3341 , H01J2237/3347
摘要： Disclosed is an etching method and an apparatus for performing an etching by alternately and repeatedly switching an average thickness of an ion sheath and an average energy of etching ions between two different values. Since the etchant absorption to the surface of an article to be etched and the etching by ions are effectively performed, it is possible to reduce the influence of an aspect ratio on an etching depth, and hence to perform the etching with an equal depth even if the width of the opening is changed.
摘要翻译：公开了一种蚀刻方法和装置，用于通过交替地和重复地切换离子鞘的平均厚度和蚀刻离子的平均能量在两个不同的值之间进行蚀刻。由于蚀刻剂对被蚀刻物的表面的吸附和离子蚀刻的吸附有效地进行，所以可以减小长宽比对蚀刻深度的影响，因此即使在相同的深度进行蚀刻开口的宽度改变。

49. 发明授权

US4825281A Bipolar transistor with sidewall bare contact structure 失效
标题翻译：双极晶体管与侧壁裸接触结构
公开(公告)号：US4825281A
公开(公告)日：1989-04-25
申请号：US435552
申请日：1982-10-21
申请人： Kazuo Nakazato , Tohru Nakamura , Masatoshi Matsuda , Takao Miyazaki , Tokuo Kure , Takahiro Okabe , Minoru Nagata
发明人： Kazuo Nakazato , Tohru Nakamura , Masatoshi Matsuda , Takao Miyazaki , Tokuo Kure , Takahiro Okabe , Minoru Nagata
IPC分类号： H01L21/8222 , H01L21/033 , H01L21/3205 , H01L21/331 , H01L27/06 , H01L29/423 , H01L29/70 , H01L29/72 , H01L29/73 , H01L29/732 , H01L29/735 , H01L23/48 , H01L29/04 , H01L29/34
CPC分类号： H01L29/66272 , H01L21/033 , H01L29/42304 , H01L29/72 , H01L29/732 , H01L29/735
摘要： A semiconductor device wherein the active regions of a transistor are formed in an opening provided in an insulating film, electrodes are led out by a polycrystalline silicon film formed on the insulating film, and the upper surfaces of the emitter and base electrodes and the exposed surface of the insulating film are substantially even.
摘要翻译：一种半导体器件，其中晶体管的有源区形成在设置在绝缘膜中的开口中，电极由形成在绝缘膜上的多晶硅膜引出，发射极和基极的上表面和暴露表面的绝缘膜基本上均匀。

50. 发明授权

US07259104B2 Sample surface processing method 失效
标题翻译：样品表面处理方法
公开(公告)号：US07259104B2
公开(公告)日：2007-08-21
申请号：US10671608
申请日：2003-09-29
申请人： Tetsuo Ono , Takafumi Tokunaga , Tadashi Umezawa , Motohiko Yoshigai , Tatsumi Mizutani , Tokuo Kure , Masayuki Kojima , Takashi Sato , Yasushi Goto
发明人： Tetsuo Ono , Takafumi Tokunaga , Tadashi Umezawa , Motohiko Yoshigai , Tatsumi Mizutani , Tokuo Kure , Masayuki Kojima , Takashi Sato , Yasushi Goto
IPC分类号： H01L21/302 , B44C1/22
CPC分类号： H01J37/32082 , H01L21/32136 , H01L21/32139
摘要： A surface processing method of a sample having a mask layer that does not contain carbon as a major component formed on a substance to be processed, the substance being a metal, semiconductor and insulator deposited on a silicon substrate, includes the steps of installing the sample on a sample board in a vacuum container, generating a plasma that consists of a mixture of halogen gas and adhesive gas inside the vacuum container, applying a radio frequency bias voltage having a frequency ranging from 200 kHz to 20 MHz on the sample board, and controlling a periodic on-off of the radio frequency bias voltage with an on-off control frequency ranging from 100 Hz to 10 kHz.
摘要翻译：具有在被处理物质上形成的不含有碳作为主要成分的掩模层的样品的表面处理方法，该物质是沉积在硅基板上的金属，半导体和绝缘体，该物质包括如下步骤：在真空容器中的样品板上，在真空容器内产生由卤素气体和粘合气体的混合物构成的等离子体，在样品板上施加频率范围为200kHz〜20MHz的射频偏置电压，以从100Hz到10kHz的开关控制频率来控制射频偏置电压的周期性的断开。

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