专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06525336B1 Superfine electronic device and method for making same 失效
标题翻译：超细电子设备及其制作方法
公开(公告)号：US06525336B1
公开(公告)日：2003-02-25
申请号：US08463761
申请日：1995-06-05
申请人： Seiichi Kondo , Yasuo Wada , Tsuyoshi Uda , Tokuo Kure , Tsuneo Ichiguchi , Shinji Okazaki , Yoshimasa Murayama
发明人： Seiichi Kondo , Yasuo Wada , Tsuyoshi Uda , Tokuo Kure , Tsuneo Ichiguchi , Shinji Okazaki , Yoshimasa Murayama
IPC分类号： H01L2906
CPC分类号： G11C13/025 , B82Y10/00 , B82Y15/00 , G11C11/34 , G11C19/00 , G11C2216/08 , H01L49/006 , H03K19/02
摘要： A superfine electronic device is disclosed, which is constructed by atomic fine lines having a structure in which a plurality of atoms are arranged on one or a plurality of straight lines, in a ring shape or on curves with a size of atomic level, and which includes elements for doping electrons and holes. Using these atomic fine lines, it is possible to integrate semiconductor elements utilizing pn junctions at an atomic level with a high density. A groove having a sufficiently small size is formed in an insulating film disposed on a substrate. Then, atoms or molecules are supplied on the substrate and in the groove, which and are heated to a temperature sufficiently high for moving the atoms or molecules during or after the supply thereof to form a quantum fine line at edge portions of the groove.
摘要翻译：公开了一种超细电子器件，其由具有多个原子排列在一个或多个直线上的原子细线构成，具有环形或具有原子级尺寸的曲线，并且其中包括用于掺杂电子和空穴的元件。使用这些原子细线，可以利用高密度的原子级的pn结集成半导体元件。在设置在基板上的绝缘膜中形成具有足够小尺寸的凹槽。然后，原子或分子被提供在衬底和沟槽中，并且被加热到足够高的温度以在其供给期间或之后移动原子或分子，以在槽的边缘部分处形成量子细线。

2. 发明授权

US5561300A Atomic switching devices and logical circuits 失效
标题翻译：原子开关器件和逻辑电路
公开(公告)号：US5561300A
公开(公告)日：1996-10-01
申请号：US994968
申请日：1992-12-22
申请人： Yasuo Wada , Seiichi Kondo , Tsuyoshi Uda , Masukazu Igarashi , Hiroshi Kajiyama , Hisashi Nagano , Akito Sakurai , Tsuneo Ichiguchi
发明人： Yasuo Wada , Seiichi Kondo , Tsuyoshi Uda , Masukazu Igarashi , Hiroshi Kajiyama , Hisashi Nagano , Akito Sakurai , Tsuneo Ichiguchi
IPC分类号： G01Q90/00 , G11B9/00 , G11C11/34 , G11C13/00 , G11C19/00 , H01L27/06 , H01L27/085 , H01L49/00 , H03F3/04 , H03K17/51 , H03K17/54 , H03K17/56 , H03K19/02 , H03K19/08 , H01J37/30 , H02B1/24
CPC分类号： B82Y15/00 , B82Y10/00 , G11B9/14 , G11B9/1463 , G11C11/34 , G11C13/00 , G11C19/00 , H01L27/06 , H01L27/085 , H01L49/00 , H01L49/006 , H03F3/04 , H03K17/51 , H03K17/545 , H03K17/56 , H03K19/02 , H03K19/08 , G11C13/025 , G11C2213/81 , G11C2216/08 , Y10S977/94 , Y10T307/74 , Y10T307/937
摘要： In an atomic switch, opposite ends of an atom wire are connected to an input and output, and a switching gate is connected to a switching power supply. An input signal is outputted when a switching atom is connected to the atom wire, whereas an input signal is not outputted when the switching atom is moved to disconnect from the atom wire. There are provided an atom wire having a plurality of atoms arranged in a line or in a plurality of lines, in a ring shape, or in a curved line, and a switching gate made of an atom wire. The atom wire is switched by the field effect of the switching gate.
摘要翻译：在原子开关中，原子线的相对端连接到输入和输出，并且开关栅极连接到开关电源。当切换原子连接到原子线时输出输入信号，而当切换原子移动以与原子线分离时，输出信号不输出。提供一种原子线，其具有以线状或多条排列成环状或曲线的多个原子以及由原子线构成的开关栅极。原子线由开关栅极的场效应切换。

3. 发明授权

US5694059A Buffer of fine connection structure for connecting an atom level circuit and a general semiconductor circuit 失效
标题翻译：用于连接原子电平电路和一般半导体电路的精细连接结构缓冲器
公开(公告)号：US5694059A
公开(公告)日：1997-12-02
申请号：US383843
申请日：1995-02-06
申请人： Yasuo Wada , Munehisa Mitsuya , Yasushi Tomioka , Mark I. Lutwyche , Seiichi Kondo , Seiji Heike
发明人： Yasuo Wada , Munehisa Mitsuya , Yasushi Tomioka , Mark I. Lutwyche , Seiichi Kondo , Seiji Heike
IPC分类号： G11C5/00 , G11C11/34 , G11C19/00 , H01L27/06 , H01L49/00 , H03F3/04 , H03K19/02 , H03K19/08 , H03K19/0175
CPC分类号： B82Y15/00 , B82Y10/00 , G11C11/34 , G11C19/00 , H01L27/06 , H01L49/00 , H01L49/006 , H03F3/04 , H03K19/02 , H03K19/08 , G11C13/025 , G11C2213/81 , G11C2216/08 , Y10S977/936 , Y10S977/937
摘要： A buffer circuit ID provided for connecting an atom level device (for example, an Atom Relay Transistor circuit), formed by arranging atoms in a predetermined pattern, to a device such as a semiconductor device and a quantum device. The buffer circuit can be formed as a voltage or current amplification circuit. The voltage amplification circuit may be a single electron transistor circuit, and the current amplification circuit may be an avalanche amplification device circuit. The Atom Relay Transistor circuit and the device such as a semiconductor device and a quantum device are formed substantially on the same flat insulating member, and connected by a fine connection structure made of a conductive body such as metal.
摘要翻译：提供用于连接原子级装置（例如，原子继电器晶体管电路）的缓冲电路ID，其通过以预定图案排列原子而形成于诸如半导体装置和量子装置之类的装置。缓冲电路可以形成为电压或电流放大电路。电压放大电路可以是单电子晶体管电路，并且电流放大电路可以是雪崩放大器件电路。原子继电器晶体管电路和诸如半导体器件和量子器件的器件基本上形成在相同的平坦绝缘构件上，并且由诸如金属的导电体形成的精细连接结构连接。

4. 发明授权

US5510614A Solid surface observation method and apparatus therefor, and electronic apparatus formed of the solid surface observation apparatus and method of forming the electronic apparatus 失效
标题翻译：固体表面观察方法及其设备，以及由固体表面观察装置和形成电子设备的方法形成的电子设备
公开(公告)号：US5510614A
公开(公告)日：1996-04-23
申请号：US184068
申请日：1994-01-21
申请人： Munehisa Mitsuya , Yasuo Wada , Seiji Heike , Seiichi Kondo
发明人： Munehisa Mitsuya , Yasuo Wada , Seiji Heike , Seiichi Kondo
IPC分类号： C04B41/00 , C04B41/80 , C23C26/00 , G01Q30/02 , G01Q60/10 , G11B9/00 , H01J37/00
CPC分类号： G01Q30/02 , B82Y35/00 , C04B41/0027 , C04B41/0045 , C04B41/009 , C04B41/80 , C23C26/00 , G01Q60/10 , B82Y10/00 , C04B2111/94 , G11B9/14 , G11B9/149 , H01J2237/31732 , Y10S977/855
摘要： A surface of an insulator or semiconductor substrate is irradiated with a beam such as an electron beam, an electromagnetic wave beam, an ion beam, etc. to excite carriers so as to form an electrical conductive layer on the surface of and in the inside of the substrate to thereby make it possible to perform observation and micro working on the insulator by using a scanning tunneling microscope.
摘要翻译：用电子束，电磁波束，离子束等光束照射绝缘体或半导体基板的表面，以激励载流子，以在其表面上和内部形成导电层从而能够通过使用扫描隧道显微镜对绝缘体进行观察和微加工。

5. 发明申请

US20080260156A1 Management Service Device, Backup Service Device, Communication Terminal Device, and Storage Medium 审中-公开
标题翻译：管理服务设备，备份服务设备，通信终端设备和存储介质
公开(公告)号：US20080260156A1
公开(公告)日：2008-10-23
申请号：US11660105
申请日：2004-08-19
申请人： Akihiro Baba , Shouji Sakurai , Seiichi Kondo , Tatsuji Munaka , Mariko Sawamura
发明人： Akihiro Baba , Shouji Sakurai , Seiichi Kondo , Tatsuji Munaka , Mariko Sawamura
IPC分类号： H04L9/06 , G06F21/00
CPC分类号： G06F21/6209 , G06F11/1458 , G06F11/1464 , G06F11/1469 , G06F21/34 , G06F21/88 , G06F2221/2103 , G06F2221/2129
摘要： It is an object to provide a method for invalidation and new registration of a storage medium, a method for backup of data stored in a storage medium and for restoration of backup data to a storage medium, and a method for encryption of and application of an electronic signature to data to be backed up, and for decryption of backup data to be restored and verification of a signature. A service device includes a reception unit for receiving a request for data processing regarding a storage medium from a communication terminal device connected to the storage medium, an authentication unit for performing authentication of whether or not the storage medium connected to the communication terminal device is valid, and a database for storing a public key of the storage medium, wherein, when the reception unit receives a request for invalidation of the first storage medium from the communication terminal device, and the authentication unit authenticates the second storage medium connected to the communication terminal device as a valid storage medium, the database deletes the public key of the first storage medium stored in the database.
摘要翻译：本发明的目的是提供一种用于存储介质的无效和新的注册的方法，用于备份存储在存储介质中的数据的方法以及用于将备份数据恢复到存储介质的方法，以及用于对存储介质进行加密和应用的方法对要备份的数据进行电子签名，以及解密要恢复的备份数据和签名的验证。服务设备包括：接收单元，用于从连接到存储介质的通信终端设备接收关于存储介质的数据处理的请求;认证单元，用于执行与通信终端设备连接的存储介质是否有效的认证以及用于存储所述存储介质的公开密钥的数据库，其中，当所述接收单元从所述通信终端设备接收到所述第一存储介质的无效请求时，所述认证单元认证连接到所述通信终端的所述第二存储介质设备作为有效的存储介质，数据库删除存储在数据库中的第一个存储介质的公开密钥。

6. 发明申请

US20080233736A1 PROCESS FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：制造半导体集成电路器件的工艺
公开(公告)号：US20080233736A1
公开(公告)日：2008-09-25
申请号：US12127564
申请日：2008-05-27
申请人： Naofumi Ohashi , Junji Noguchi , Toshinori Imai , Hizuru Yamaguchi , Nobuo Owada , Kenji Hinode , Yoshio Homma , Seiichi Kondo
发明人： Naofumi Ohashi , Junji Noguchi , Toshinori Imai , Hizuru Yamaguchi , Nobuo Owada , Kenji Hinode , Yoshio Homma , Seiichi Kondo
IPC分类号： H01L21/4763
CPC分类号： H01L21/0209 , G09G5/399 , H01L21/02074 , H01L21/3212 , H01L21/76838 , H01L21/7684 , Y10S438/906
摘要： In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.
摘要翻译：为了提供通过化学机械抛光（CMP）方法形成的金属配线的防腐蚀技术，根据本发明的半导体集成电路器件的制造方法包括以下步骤：形成Cu（或Cu合金）的金属层含有Cu作为主要成分），然后通过化学机械抛光（CMP）方法平坦化金属层以形成金属布线; 防止晶片的平面化主面在金属布线的表面上形成疏水性保护膜; 将晶圆的防腐主面浸入或保持湿润状态，使其不会变干; 并将晶片的主要表面保持在潮湿状态。

7. 发明授权

US07183212B2 Polishing method, metallization fabrication method, method for manufacturing semiconductor device and semiconductor device 有权
标题翻译：抛光方法，金属化制造方法，制造半导体器件和半导体器件的方法
公开(公告)号：US07183212B2
公开(公告)日：2007-02-27
申请号：US10898252
申请日：2004-07-26
申请人： Seiichi Kondo , Masaaki Fujimori , Noriyuki Sakuma , Yoshio Homma
发明人： Seiichi Kondo , Masaaki Fujimori , Noriyuki Sakuma , Yoshio Homma
IPC分类号： H01L21/302
CPC分类号： C23F1/18 , C09G1/04 , C23F3/06 , H01L21/3212 , H01L21/7684
摘要： Described is a polishing technique adapted for multilevel metallization of an electronic circuit device, which comprises polishing a metal film with a polishing liquid containing an oxidizing substance, a phosphoric acid and a protection-layer forming agent. The present invention makes it possible to polishing a metal film at a high removal rate while suppressing occurrence of scratches, delamination, dishing or erosion.
摘要翻译：描述了适用于电子电路器件的多层金属化的抛光技术，其包括用包含氧化物质，磷酸和保护层形成剂的抛光液抛光金属膜。本发明能够在抑制划痕，分层，凹陷或侵蚀的发生的同时以高的去除率对金属膜进行研磨。

8. 发明申请

US20060141792A1 Process for manufacturing semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件制造工艺
公开(公告)号：US20060141792A1
公开(公告)日：2006-06-29
申请号：US11357181
申请日：2006-02-21
申请人： Naofumi Ohashi , Junji Noguchi , Toshinori Imai , Hizuru Yamaguchi , Nobuo Owada , Kenji Hinode , Yoshio Homma , Seiichi Kondo
发明人： Naofumi Ohashi , Junji Noguchi , Toshinori Imai , Hizuru Yamaguchi , Nobuo Owada , Kenji Hinode , Yoshio Homma , Seiichi Kondo
IPC分类号： H01L21/44
CPC分类号： H01L21/0209 , G09G5/399 , H01L21/02074 , H01L21/3212 , H01L21/76838 , H01L21/7684 , Y10S438/906
摘要： In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP). method, a process for manufacturing. a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.
摘要翻译：为了提供通过化学机械抛光（CMP）形成的金属配线的防腐蚀技术。方法，制造方法。根据本发明的半导体集成电路器件包括以下步骤：在晶片的主面上形成Cu（或含有Cu作为主要成分的Cu合金）的金属层，然后通过化学机械抛光使金属层平坦化（CMP）方法形成金属布线; 防止晶片的平面化主面在金属布线的表面上形成疏水性保护膜; 将晶圆的防腐主面浸入或保持湿润状态，使其不会变干; 并将晶片的主要表面保持在潮湿状态。

9. 发明授权

US06800557B2 Process for manufacturing semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件制造工艺
公开(公告)号：US06800557B2
公开(公告)日：2004-10-05
申请号：US10369716
申请日：2003-02-21
申请人： Naofumi Ohashi , Junji Noguchi , Toshinori Imai , Hizuru Yamaguchi , Nobuo Owada , Kenji Hinode , Yoshio Homma , Seiichi Kondo
发明人： Naofumi Ohashi , Junji Noguchi , Toshinori Imai , Hizuru Yamaguchi , Nobuo Owada , Kenji Hinode , Yoshio Homma , Seiichi Kondo
IPC分类号： H01L21302
CPC分类号： H01L21/0209 , G09G5/399 , H01L21/02074 , H01L21/3212 , H01L21/76838 , H01L21/7684 , Y10S438/906
摘要： In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.
摘要翻译：为了提供通过化学机械抛光（CMP）方法形成的金属配线的防腐蚀技术，根据本发明的半导体集成电路器件的制造方法包括以下步骤：形成Cu（或Cu合金）的金属层含有Cu作为主要成分），然后通过化学机械抛光（CMP）方法平坦化金属层以形成金属布线; 防止晶片的平面化主面在金属布线的表面上形成疏水性保护膜; 将晶圆的防腐主面浸入或保持湿润状态，使其不会变干; 并将晶片的主要表面保持在潮湿状态。

10. 发明授权

US06750128B2 Methods of polishing, interconnect-fabrication, and producing semiconductor devices 失效
标题翻译：抛光，互连制造和制造半导体器件的方法
公开(公告)号：US06750128B2
公开(公告)日：2004-06-15
申请号：US10396410
申请日：2003-03-26
申请人： Seiichi Kondo , Noriyuki Sakuma , Yoshio Homma
发明人： Seiichi Kondo , Noriyuki Sakuma , Yoshio Homma
IPC分类号： H01L213205
CPC分类号： H01L21/3212 , B24B37/044 , C09G1/02 , H01L21/7684
摘要： The present invention provides a technique to reduce and suppress scratches and delamination, to suppress and control the development of dishing and erosion, and to polish at high polishing rate. Polishing is performed using a polishing solution, which contains an oxidizer, phosphoric acid, organic acid, a chemical to form inhibition layer, and water.
摘要翻译：本发明提供减少和抑制划痕和分层，抑制和控制凹陷和侵蚀的发展并以高抛光速率抛光的技术。使用包含氧化剂，磷酸，有机酸，形成抑制层的化学品和水的抛光溶液进行抛光。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式