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41. 发明授权

US07671405B2 Deep bitline implant to avoid program disturb 有权
标题翻译：深位线植入，以避免程序干扰
公开(公告)号：US07671405B2
公开(公告)日：2010-03-02
申请号：US11646157
申请日：2006-12-26
申请人： Timothy Thurgate , Yi He , Ming-Sang Kwan , Zhizheng Liu , Xuguang Wang
发明人： Timothy Thurgate , Yi He , Ming-Sang Kwan , Zhizheng Liu , Xuguang Wang
IPC分类号： H01L27/112 , H01L21/336
CPC分类号： H01L27/11568 , G11C5/02 , G11C5/06 , H01L27/115
摘要： A method of forming at least a portion of a dual bit memory core array upon a semiconductor substrate, the method comprising performing front end processing, performing a first bitline implant, or pocket implants, or both into the first bitline spacings to establish buried first bitlines within the substrate, depositing a layer of the spacer material over the charge trapping dielectric and the polysilicon layer features, forming a sidewall spacer adjacent to the charge trapping dielectric and the polysilicon layer features to define second bitline spacings between adjacent memory cells, performing a deep arsenic implant into the second bitline spacings to establish a second bitline within the structure that is deeper than the first bit line, removing the sidewall spacers and performing back end processing.
摘要翻译：一种在半导体衬底上形成双位存储器核心阵列的至少一部分的方法，所述方法包括执行前端处理，执行第一位线注入或袋式注入或二者进入第一位线间隔以建立掩埋的第一位线在衬底内，在电荷俘获电介质和多晶硅层特征之上沉积间隔物材料层，形成与电荷俘获电介质相邻的侧壁隔离层和多晶硅层特征以限定相邻存储器单元之间的第二位线间隔，执行深度砷注入到第二位线间隔中，以在结构内建立比第一位线更深的第二位线，去除侧壁间隔件并执行后端处理。

42. 发明授权

US07626869B2 Multi-phase wordline erasing for flash memory 有权
标题翻译：闪存多相字线擦除
公开(公告)号：US07626869B2
公开(公告)日：2009-12-01
申请号：US11745327
申请日：2007-05-07
申请人： Xuguang Wang , Yi He , Zhizheng Liu , Sung-Yong Chung , Darlene G. Hamilton , Ashot Melik-Martirosian , Gulzar Kathawala , Ming Sang Kwan , Mark Randolph , Timothy Thurgate
发明人： Xuguang Wang , Yi He , Zhizheng Liu , Sung-Yong Chung , Darlene G. Hamilton , Ashot Melik-Martirosian , Gulzar Kathawala , Ming Sang Kwan , Mark Randolph , Timothy Thurgate
IPC分类号： G11C11/34
CPC分类号： G11C16/16
摘要： Erasing wordlines at the same time can cause undesirable results because some wordlines are affected by electromagnetic waves of other wordlines. However, other wordlines are not affected because they are next to contacts. Therefore, it can be beneficial to erase wordlines in a multi-phase sequence that allows for erasing wordlines without an impact from other wordlines.
摘要翻译：同时删除字线可能会导致不良结果，因为某些字线受到其他字线的电磁波的影响。然而，其他字线不受影响，因为它们在联系人旁边。因此，删除允许擦除字线而不受其他字线影响的多相序列中的字线可能是有益的。

43. 发明授权

US06770938B1 Diode fabrication for ESD/EOS protection 有权
标题翻译：用于ESD / EOS保护的二极管制造
公开(公告)号：US06770938B1
公开(公告)日：2004-08-03
申请号：US10050394
申请日：2002-01-16
申请人： Michael Fliesler , Mark Ramsbey , Mark Randolph , Ian Morgan , Timothy Thurgate , Paohua Kuo , David M. Rogers
发明人： Michael Fliesler , Mark Ramsbey , Mark Randolph , Ian Morgan , Timothy Thurgate , Paohua Kuo , David M. Rogers
IPC分类号： H01L2362
CPC分类号： H01L27/0255
摘要： An ESD protection device is provided for an integrated circuit. The ESD protection device includes a power supply clamp device formed from a diode and coupled between a first power supply VCC and a second power supply VSS. An input protection device is also provided which is formed from a diode coupled between an input pad and the first power supply and a second diode coupled between the input pad and a second power supply. The diodes have an adjusted reverse breakdown voltage that is higher than the voltage supply VCC used to power the peripheral circuitry that drives circuitry within a core of the integrated circuit. The adjusted reverse breakdown voltage is also lower than the breakdown voltage of gate oxide layers used within the peripheral circuitry.
摘要翻译：为集成电路提供ESD保护装置。 ESD保护装置包括由二极管形成并耦合在第一电源VCC和第二电源VSS之间的电源钳位装置。还提供一种输入保护装置，其由耦合在输入焊盘和第一电源之间的二极管和耦合在输入焊盘和第二电源之间的第二二极管形成。二极管具有调整的反向击穿电压，其高于用于为驱动集成电路的核心内的电路的外围电路供电的电压源VCC。调整的反向击穿电压也低于在外围电路中使用的栅极氧化物层的击穿电压。

44. 发明授权

US06518072B1 Deposited screen oxide for reducing gate edge lifting 有权
标题翻译：沉积的屏幕氧化物，用于减少门边缘提升
公开(公告)号：US06518072B1
公开(公告)日：2003-02-11
申请号：US09476906
申请日：2000-01-03
申请人： Carl Robert Huster , Daniel Sobek , Timothy Thurgate , Sameer S. Haddad
发明人： Carl Robert Huster , Daniel Sobek , Timothy Thurgate , Sameer S. Haddad
IPC分类号： H01L218247
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324
摘要： A method of manufacturing a flash memory device with a controllable amount of gate edge lifting including etching the ends of the tunnel oxide forming a cavity at each end of the tunnel oxide and anisotropically depositing and etching an oxide to form spacers on the sides of the gate stack. The spacers have a predetermined thickness that controls the amount of gate edge lifting. The predetermined thickness is determined during a characterization procedure that can be a computer modeling procedure or it can be determined empirically.
摘要翻译：一种制造具有可控量的栅极边缘提升的闪速存储器件的方法，包括蚀刻隧道氧化物的端部，在隧道氧化物的每一端处形成空腔，并各向异性沉积和蚀刻氧化物以在栅极的侧面上形成间隔物堆栈间隔物具有控制浇口边缘提升量的预定厚度。在可以是计算机建模过程的表征过程中确定预定厚度，或者可以凭经验确定。

45. 发明授权

US06329273B1 Solid-source doping for source/drain to eliminate implant damage 有权
标题翻译：用于源极/漏极的固体源掺杂以消除植入物损伤
公开(公告)号：US06329273B1
公开(公告)日：2001-12-11
申请号：US09430410
申请日：1999-10-29
申请人： Timothy Thurgate , Carl Robert Huster
发明人： Timothy Thurgate , Carl Robert Huster
IPC分类号： H01L21225
CPC分类号： H01L29/66825 , H01L21/2257
摘要： A method of manufacturing a flash memory device in which minimal gate edge lifting is accomplished by minimally oxidizing the gate stack and exposed surface of the substrate, anisotropically etching the layer of oxide from the substrate, forming a doped solid source material on portions of the substrate in which source regions are to be formed and diffusing the dopants from the solid source material into the substrate.
摘要翻译：一种制造闪速存储器件的方法，其中通过最小化氧化栅极堆叠和衬底的暴露表面来实现最小栅极边缘提升，从衬底各向异性地蚀刻氧化层，在衬底的部分上形成掺杂的固体源材料其中将形成源区并将掺杂剂从固体源材料扩散到衬底中。

46. 发明授权

US06268624B1 Method for inhibiting tunnel oxide growth at the edges of a floating gate during semiconductor device processing 有权
标题翻译：在半导体器件处理期间抑制浮栅的边缘处的隧道氧化物生长的方法
公开(公告)号：US06268624B1
公开(公告)日：2001-07-31
申请号：US09364982
申请日：1999-07-31
申请人： Daniel Sobek , Timothy Thurgate , Carl R. Huster , Tuan Duc Pham , Mark T. Ramsbey , Sameer S. Haddad
发明人： Daniel Sobek , Timothy Thurgate , Carl R. Huster , Tuan Duc Pham , Mark T. Ramsbey , Sameer S. Haddad
IPC分类号： H01L218247
CPC分类号： H01L21/28273
摘要： A method for making a ULSI MOSFET chip includes forming a MOSFET gate stack on a substrate, with a tunnel oxide layer being sandwiched between the gate stack and substrate. To prevent thickening of the tunnel oxide layer into a “gate edge lifting” profile during subsequent oxidation-causing steps, at least one protective barrier film is deposited or grown over the gate stack and tunnel oxide layer immediately after gate stack formation. Then, subsequent steps, including forming source and drain regions for the gate stack, can be undertaken without causing thickening of the tunnel oxide layer.
摘要翻译：制造ULSI MOSFET芯片的方法包括在衬底上形成MOSFET栅极叠层，其中隧道氧化层夹在栅叠层和衬底之间。为了防止隧道氧化物层在随后的氧化引发步骤期间增厚到“栅极边缘提升”轮廓中，在栅极堆叠形成之后立即沉积或生长至少一个保护性阻挡膜在栅极堆叠和隧道氧化物层上。然后，可以进行包括形成栅极堆叠的源极和漏极区域的后续步骤，而不会导致隧道氧化物层的增厚。

47. 发明授权

US08547738B2 Techniques for providing a semiconductor memory device 有权
标题翻译：提供半导体存储器件的技术
公开(公告)号：US08547738B2
公开(公告)日：2013-10-01
申请号：US13047097
申请日：2011-03-14
申请人： Srinivasa Rao Banna , Michael A. Van Buskirk , Timothy Thurgate
发明人： Srinivasa Rao Banna , Michael A. Van Buskirk , Timothy Thurgate
IPC分类号： G11C11/34
CPC分类号： H01L27/10802 , G11C7/00 , H01L27/105 , H01L27/1052 , H01L27/1203 , H01L29/0847 , H01L29/1029 , H01L29/1095 , H01L29/7841
摘要： Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell including a first region, a a second region, and a body region capacitively coupled to at least one word line and disposed between the first region and the second region. Each memory cell also including a third region, wherein the third region may be doped differently than the first region, the second region, and the body region.
摘要翻译：公开了一种用于提供半导体存储器件的技术。在一个特定示例性实施例中，这些技术可以被实现为包括布置成行和列阵列的多个存储器单元的半导体存储器件。每个存储单元包括电容耦合到至少一个字线并且设置在第一区域和第二区域之间的第一区域，第二区域和体区域。每个存储单元还包括第三区域，其中第三区域可以掺杂不同于第一区域，第二区域和体区域。

48. 发明申请

US20130228851A1 MEMORY DEVICE PROTECTION LAYER 审中-公开
标题翻译：存储器件保护层
公开(公告)号：US20130228851A1
公开(公告)日：2013-09-05
申请号：US13858229
申请日：2013-04-08
申请人： Rinji Sugino , Timothy Thurgate , Jean Yee-Mei Yang , Michael Brennan
发明人： Rinji Sugino , Timothy Thurgate , Jean Yee-Mei Yang , Michael Brennan
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/66825 , H01L29/66833 , H01L29/7881
摘要： A memory device includes a group of memory cells formed on a substrate, each memory cell including a source region and a drain region formed in the substrate. The memory device also includes a protection layer formed on top surfaces of the source regions and the drain regions, and on side surfaces of the group of memory cells.
摘要翻译：存储器件包括形成在衬底上的一组存储器单元，每个存储器单元包括形成在衬底中的源极区域和漏极区域。存储器件还包括形成在源极区域和漏极区域的顶表面上以及在该组存储器单元的侧表面上的保护层。

49. 发明授权

US08415734B2 Memory device protection layer 有权
标题翻译：内存设备保护层
公开(公告)号：US08415734B2
公开(公告)日：2013-04-09
申请号：US11608032
申请日：2006-12-07
申请人： Rinji Sugino , Timothy Thurgate , Jean Yee-Mei Yang , Michael Brennan
发明人： Rinji Sugino , Timothy Thurgate , Jean Yee-Mei Yang , Michael Brennan
IPC分类号： H01L29/76
CPC分类号： H01L29/792 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/66825 , H01L29/66833 , H01L29/7881
摘要： A memory device includes a group of memory cells formed on a substrate, each memory cell including a source region and a drain region formed in the substrate. The memory device also includes a protection layer formed on top surfaces of the source regions and the drain regions, and on side surfaces of the group of memory cells.
摘要翻译：存储器件包括形成在衬底上的一组存储器单元，每个存储器单元包括形成在衬底中的源极区域和漏极区域。存储器件还包括形成在源极区域和漏极区域的顶表面上以及在该组存储器单元的侧表面上的保护层。

50. 发明授权

US08409952B2 Method of forming an electronic device including forming a charge storage element in a trench of a workpiece 有权
标题翻译：形成电子器件的方法，包括在工件的沟槽中形成电荷存储元件
公开(公告)号：US08409952B2
公开(公告)日：2013-04-02
申请号：US12102488
申请日：2008-04-14
申请人： Suketu Arun Parikh , Olov B. Karlsson , Yun Sun , Shankar Sinha , Timothy Thurgate
发明人： Suketu Arun Parikh , Olov B. Karlsson , Yun Sun , Shankar Sinha , Timothy Thurgate
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L21/26586 , H01L27/115 , H01L29/1041 , H01L29/66666 , H01L29/7827
摘要： A method of forming an electronic device including forming a first trench in a workpiece including a substrate, the first trench having side walls and a bottom surface extending for a width between the side walls and forming a charge-storage layer along the side walls and bottom surface of the first trench. The method further includes implanting ions within the substrate underlying the bottom surface of the first trench to form an implant region and annealing the implant region, wherein after annealing, the implant region extends the width of the bottom surface and along a portion of the side walls.
摘要翻译：一种形成电子器件的方法，包括在包括衬底的工件中形成第一沟槽，所述第一沟槽具有侧壁和在所述侧壁之间延伸宽度的底表面，并且沿着所述侧壁和底部形成电荷存储层第一沟槽的表面。该方法还包括在第一沟槽的底表面下方的衬底内注入离子以形成植入区域并退火植入区域，其中在退火之后，植入区域延伸底表面的宽度并沿着侧壁的一部分。

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