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1. 发明授权

US06518072B1 Deposited screen oxide for reducing gate edge lifting 有权
标题翻译：沉积的屏幕氧化物，用于减少门边缘提升
公开(公告)号：US06518072B1
公开(公告)日：2003-02-11
申请号：US09476906
申请日：2000-01-03
申请人： Carl Robert Huster , Daniel Sobek , Timothy Thurgate , Sameer S. Haddad
发明人： Carl Robert Huster , Daniel Sobek , Timothy Thurgate , Sameer S. Haddad
IPC分类号： H01L218247
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324
摘要： A method of manufacturing a flash memory device with a controllable amount of gate edge lifting including etching the ends of the tunnel oxide forming a cavity at each end of the tunnel oxide and anisotropically depositing and etching an oxide to form spacers on the sides of the gate stack. The spacers have a predetermined thickness that controls the amount of gate edge lifting. The predetermined thickness is determined during a characterization procedure that can be a computer modeling procedure or it can be determined empirically.
摘要翻译：一种制造具有可控量的栅极边缘提升的闪速存储器件的方法，包括蚀刻隧道氧化物的端部，在隧道氧化物的每一端处形成空腔，并各向异性沉积和蚀刻氧化物以在栅极的侧面上形成间隔物堆栈间隔物具有控制浇口边缘提升量的预定厚度。在可以是计算机建模过程的表征过程中确定预定厚度，或者可以凭经验确定。

2. 发明授权

US06329273B1 Solid-source doping for source/drain to eliminate implant damage 有权
标题翻译：用于源极/漏极的固体源掺杂以消除植入物损伤
公开(公告)号：US06329273B1
公开(公告)日：2001-12-11
申请号：US09430410
申请日：1999-10-29
申请人： Timothy Thurgate , Carl Robert Huster
发明人： Timothy Thurgate , Carl Robert Huster
IPC分类号： H01L21225
CPC分类号： H01L29/66825 , H01L21/2257
摘要： A method of manufacturing a flash memory device in which minimal gate edge lifting is accomplished by minimally oxidizing the gate stack and exposed surface of the substrate, anisotropically etching the layer of oxide from the substrate, forming a doped solid source material on portions of the substrate in which source regions are to be formed and diffusing the dopants from the solid source material into the substrate.
摘要翻译：一种制造闪速存储器件的方法，其中通过最小化氧化栅极堆叠和衬底的暴露表面来实现最小栅极边缘提升，从衬底各向异性地蚀刻氧化层，在衬底的部分上形成掺杂的固体源材料其中将形成源区并将掺杂剂从固体源材料扩散到衬底中。

3. 发明授权

US06329687B1 Two bit flash cell with two floating gate regions 有权
标题翻译：两位闪存单元，带有两个浮动栅极区域
公开(公告)号：US06329687B1
公开(公告)日：2001-12-11
申请号：US09492353
申请日：2000-01-27
申请人： Daniel Sobek , Timothy Thurgate , Carl Robert Huster , Masaaki Higashitani
发明人： Daniel Sobek , Timothy Thurgate , Carl Robert Huster , Masaaki Higashitani
IPC分类号： H01L2976
CPC分类号： H01L29/66825 , G11C11/5621 , G11C11/5671 , G11C16/0458 , G11C2211/5612 , H01L21/28273 , H01L29/7887
摘要： The method of fabricating the semi-conductor device includes forming a center dielectric region on a substrate. The center dielectric region has a first thickness and the substrate includes a first conductive material. Then, a first plurality of spacers is formed near the center dielectric region. A second conductive material is implanted into the substrate using the first plurality of spacers for alignment. The second conductive material form sources/drains the first plurality of spacers are then removed and a dielectric layer is formed over the substrate and the source/drain regions. The dielectric layer has a second thickness that is less than the first thickness. A second plurality of spacers is formed near the center dielectric region. The second plurality of spacers are conductive and have a third thickness that is substantially equal to the difference of the first and second thickness'. A gate dielectric layer is formed over the substrate, center dielectric region, and second plurality of spacers. Finally, a control gate layer is formed over the gate dielectric layer.
摘要翻译：制造半导体器件的方法包括在衬底上形成中心电介质区域。中心电介质区域具有第一厚度，并且衬底包括第一导电材料。然后，在中心电介质区域附近形成第一多个间隔物。使用第一多个用于对准的间隔物将第二导电材料注入基板。然后去除第一多个间隔物的第二导电材料形成源/漏极，并且在衬底和源极/漏极区上形成介电层。介电层具有小于第一厚度的第二厚度。在中心电介质区域附近形成第二多个间隔物。第二多个间隔物是导电的并且具有基本上等于第一和第二厚度的差的第三厚度。栅极电介质层形成在衬底，中心电介质区域和第二多个衬垫之上。最后，在栅介质层上形成控制栅极层。

4. 发明授权

US06255165B1 Nitride plug to reduce gate edge lifting 有权
标题翻译：氮化物塞可减少浇口边缘的提升
公开(公告)号：US06255165B1
公开(公告)日：2001-07-03
申请号：US09420220
申请日：1999-10-18
申请人： Timothy Thurgate , Carl Robert Huster , Daniel Sobek
发明人： Timothy Thurgate , Carl Robert Huster , Daniel Sobek
IPC分类号： H01L21336
CPC分类号： H01L29/4983 , H01L21/28167 , H01L21/28273 , H01L29/42324 , H01L29/66825
摘要： A method of manufacturing a flash memory device in which minimal gate edge lifting is accomplished by etching a portion of the ends of the layer of tunnel oxide forming cavities, forming silicon nitride plugs in the cavities and forming a layer of oxide on the surface of the flash memory device wherein the silicon nitride plugs minimize gate edge lifting.
摘要翻译：一种制造闪速存储器件的方法，其中通过蚀刻隧道氧化物形成腔的层的一部分的一部分来实现最小栅边缘提升，在空腔中形成氮化硅塞，并在该表面上形成一层氧化物闪存器件，其中氮化硅插塞最小化栅极边缘提升。

5. 发明授权

US08531878B2 Techniques for providing a semiconductor memory device 有权
标题翻译：提供半导体存储器件的技术
公开(公告)号：US08531878B2
公开(公告)日：2013-09-10
申请号：US13109821
申请日：2011-05-17
申请人： Srinivasa Rao Banna , Michael A. Van Buskirk , Timothy Thurgate
发明人： Srinivasa Rao Banna , Michael A. Van Buskirk , Timothy Thurgate
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0441 , G11C16/0475 , G11C16/0483 , H01L27/11556 , H01L29/66825 , H01L29/7889
摘要： Techniques for providing a semiconductor memory device are disclosed. In one particular embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns, each memory cell. Each of the memory cell may include a first region coupled to a source line, a second region coupled to a bit line, and a body region capacitively coupled to at least one word line via a gate region and disposed between the first region and the second region, wherein the body region may include a plurality of floating body regions and a plurality of floating gate regions capacitively coupled to the at least one word line.
摘要翻译：公开了一种用于提供半导体存储器件的技术。在一个特定实施例中，这些技术可被实现为半导体存储器件，其包括布置成行和列阵列的多个存储器单元，每个存储器单元。每个存储单元可以包括耦合到源极线的第一区域，耦合到位线的第二区域和经由栅极区域电容耦合到至少一个字线并且被布置在第一区域和第二区域之间的体区域区域，其中所述主体区域可以包括多个浮动体区域和电容耦合到所述至少一个字线的多个浮动栅极区域。

6. 发明授权

US08208296B2 Apparatus and method for extended nitride layer in a flash memory 有权
标题翻译：闪存中的延伸氮化物层的装置和方法
公开(公告)号：US08208296B2
公开(公告)日：2012-06-26
申请号：US12706710
申请日：2010-02-16
申请人： Timothy Thurgate , Shenqing Fang , Kuo Tung Chang , Youseok Suh
发明人： Timothy Thurgate , Shenqing Fang , Kuo Tung Chang , Youseok Suh
IPC分类号： G11C11/34
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/11568 , H01L29/66833
摘要： A method and apparatus for storing information is provided. A core region of memory includes a semiconductor layer, at least one shallow trench, an insulator, and a charge-trapping layer. The semiconductor layer includes at least one source/drain region, and the insulator disposed above the source/drain region. The charge trapping layer is within the insulator, and the charge trapping layer is above the entire width of the source/drain region, and extends at least one angstrom beyond the width of the source/drain region, so that a portion the charge trapping layer extends into at least one shallow trench.
摘要翻译：提供了一种用于存储信息的方法和装置。存储器的核心区域包括半导体层，至少一个浅沟槽，绝缘体和电荷俘获层。半导体层包括至少一个源极/漏极区域，以及设置在源极/漏极区域上方的绝缘体。电荷捕获层在绝缘体内，并且电荷捕获层高于源/漏区的整个宽度，并且延伸超过源极/漏极区的宽度至少一埃，使得电荷捕获层延伸到至少一个浅沟槽中。

7. 发明授权

US07785965B2 Dual storage node memory devices and methods for fabricating the same 有权
标题翻译：双存储节点存储器件及其制造方法
公开(公告)号：US07785965B2
公开(公告)日：2010-08-31
申请号：US11530145
申请日：2006-09-08
申请人： Unsoon Kim , Kyunghoon Min , Ning Cheng , Hiroyuki Kinoshita , Sugino Rinji , Timothy Thurgate , Angela Hui , Jihwan Choi , Chi Chang
发明人： Unsoon Kim , Kyunghoon Min , Ning Cheng , Hiroyuki Kinoshita , Sugino Rinji , Timothy Thurgate , Angela Hui , Jihwan Choi , Chi Chang
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11568 , H01L29/42352 , H01L29/7923
摘要： Dual storage node memory devices and methods for fabricating dual storage node memory devices have been provided. In accordance with an exemplary embodiment, a method includes the steps of etching a plurality of trenches in a semiconductor substrate and forming a layered structure within the trenches. The layered structure includes a tunnel dielectric layer and a charge storage layer. Bit lines are formed within the semiconductor substrate and a layer of conductive material is deposited overlying the layered structure.
摘要翻译：已经提供了双存储节点存储器件和用于制造双存储节点存储器件的方法。根据示例性实施例，一种方法包括以下步骤：蚀刻半导体衬底中的多个沟槽并在沟槽内形成分层结构。层状结构包括隧道介电层和电荷存储层。位线形成在半导体衬底内，并且一层导电材料沉积在层叠结构之上。

8. 发明申请

US20080279014A1 MULTI-PHASE WORDLINE ERASING FOR FLASH MEMORY 有权
标题翻译：闪存存储器的多相WORDLINE擦除
公开(公告)号：US20080279014A1
公开(公告)日：2008-11-13
申请号：US11745327
申请日：2007-05-07
申请人： Xuguang Wang , Yi He , Zhizheng Liu , Sung-Yong Chung , Darlene G. Hamilton , Ashot Melik-Martirosian , Gulzar Kathawala , Ming Sang Kwan , Mark Randolph , Timothy Thurgate
发明人： Xuguang Wang , Yi He , Zhizheng Liu , Sung-Yong Chung , Darlene G. Hamilton , Ashot Melik-Martirosian , Gulzar Kathawala , Ming Sang Kwan , Mark Randolph , Timothy Thurgate
IPC分类号： G11C11/34
CPC分类号： G11C16/16
摘要： Erasing wordlines at the same time can cause undesirable results because some wordlines are affected by electromagnetic waves of other wordlines. However, other wordlines are not affected because they are next to contacts. Therefore, it can be beneficial to erase wordlines in a multi-phase sequence that allows for erasing wordlines without an impact from other wordlines.
摘要翻译：同时删除字线可能会导致不良结果，因为某些字线受到其他字线的电磁波的影响。然而，其他字线不受影响，因为它们在联系人旁边。因此，删除允许擦除字线而不受其他字线影响的多相序列中的字线可能是有益的。

9. 发明授权

US06177322B1 High voltage transistor with high gated diode breakdown voltage 有权
标题翻译：具有高门极二极管击穿电压的高压晶体管
公开(公告)号：US06177322B1
公开(公告)日：2001-01-23
申请号：US09177817
申请日：1998-10-23
申请人： Narbeh Derhacobian , Pau-Ling Chen , Hao Fang , Timothy Thurgate
发明人： Narbeh Derhacobian , Pau-Ling Chen , Hao Fang , Timothy Thurgate
IPC分类号： H01L21336
CPC分类号： H01L29/66575 , H01L29/1033 , H01L29/41775
摘要： A high voltage transistor exhibiting high gated diode breakdown voltage is formed while avoiding an excessive number of costly masking steps. Embodiments include providing a high gated diode breakdown voltage by masking the high voltage junctions from the conventional field implant, masking the source/drain regions from the conventional threshold adjust implant, providing a thick gate oxide layer, employing a very lightly doped n-type implant in lieu of conventional n+ and LDD implants, and forming contacts to the source and drain regions at a minimum distance from the gate.
摘要翻译：形成表现出高选通二极管击穿电压的高压晶体管，同时避免过多数量的昂贵的掩蔽步骤。实施例包括通过掩盖来自常规场注入的高电压接头来提供高门控二极管击穿电压，从常规阈值调整注入屏蔽源极/漏极区域，提供厚栅极氧化物层，采用非常轻掺杂的n型注入代替常规的n +和LDD植入物，并且在与栅极最小距离处形成与源区和漏区的接触。

10. 发明授权

US6147907A Biasing scheme to reduce stress on non-selected cells during read 有权
标题翻译：偏置方案，以减少读取期间未选择的细胞的压力
公开(公告)号：US6147907A
公开(公告)日：2000-11-14
申请号：US430336
申请日：1999-10-29
申请人： Timothy Thurgate , Ravi Sunkavalli
发明人： Timothy Thurgate , Ravi Sunkavalli
IPC分类号： G11C16/26 , G11C16/04
CPC分类号： G11C16/26
摘要： A method of reading a flash memory (EEPROM) device by applying zero volts to all bitlines and source terminals in the flash memory device. A negative voltage (V.sub.D) is applied to all the substrate and all wordlines in the flash memory device. The negative voltage (-V.sub.D) is applied to the bitline to which the drain of the cell being read is attached and applying a positive voltage (V.sub.G) minus the voltage V.sub.D to the wordline to which the gate of the cell being read is attached.
摘要翻译：通过对闪存器件中的所有位线和源极端子施加零伏特来读取闪存（EEPROM）器件的方法。对闪存设备中的所有基板和所有字线施加负电压（VD）。负电压（-VD）被施加到被读取的单元的漏极被附着到的位线上，并且将正电压（VG）减去电压VD加到读取单元的栅极所附着的字线上。

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