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1. 发明授权

US08409952B2 Method of forming an electronic device including forming a charge storage element in a trench of a workpiece 有权
标题翻译：形成电子器件的方法，包括在工件的沟槽中形成电荷存储元件
公开(公告)号：US08409952B2
公开(公告)日：2013-04-02
申请号：US12102488
申请日：2008-04-14
申请人： Suketu Arun Parikh , Olov B. Karlsson , Yun Sun , Shankar Sinha , Timothy Thurgate
发明人： Suketu Arun Parikh , Olov B. Karlsson , Yun Sun , Shankar Sinha , Timothy Thurgate
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L21/26586 , H01L27/115 , H01L29/1041 , H01L29/66666 , H01L29/7827
摘要： A method of forming an electronic device including forming a first trench in a workpiece including a substrate, the first trench having side walls and a bottom surface extending for a width between the side walls and forming a charge-storage layer along the side walls and bottom surface of the first trench. The method further includes implanting ions within the substrate underlying the bottom surface of the first trench to form an implant region and annealing the implant region, wherein after annealing, the implant region extends the width of the bottom surface and along a portion of the side walls.
摘要翻译：一种形成电子器件的方法，包括在包括衬底的工件中形成第一沟槽，所述第一沟槽具有侧壁和在所述侧壁之间延伸宽度的底表面，并且沿着所述侧壁和底部形成电荷存储层第一沟槽的表面。该方法还包括在第一沟槽的底表面下方的衬底内注入离子以形成植入区域并退火植入区域，其中在退火之后，植入区域延伸底表面的宽度并沿着侧壁的一部分。

2. 发明申请

US20090256242A1 METHOD OF FORMING AN ELECTRONIC DEVICE INCLUDING FORMING A CHARGE STORAGE ELEMENT IN A TRENCH OF A WORKPIECE 有权
标题翻译：形成电子装置的方法，包括在工作台的形式中形成充电储存元件
公开(公告)号：US20090256242A1
公开(公告)日：2009-10-15
申请号：US12102488
申请日：2008-04-14
申请人： Suketu Arun Parikh , Olov B. Karlsson , Yu Sun , Shankar Sinha , Timothy Thurgate
发明人： Suketu Arun Parikh , Olov B. Karlsson , Yu Sun , Shankar Sinha , Timothy Thurgate
IPC分类号： H01L21/425 , H01L23/58
CPC分类号： H01L27/11568 , H01L21/26586 , H01L27/115 , H01L29/1041 , H01L29/66666 , H01L29/7827
摘要： A method of forming an electronic device including forming a first trench in a workpiece including a substrate, the first trench having side walls and a bottom surface extending for a width between the side walls and forming a charge-storage layer along the side walls and bottom surface of the first trench. The method further includes implanting ions within the substrate underlying the bottom surface of the first trench to form an implant region and annealing the implant region, wherein after annealing, the implant region extends the width of the bottom surface and along a portion of the side walls.
摘要翻译：一种形成电子器件的方法，包括在包括衬底的工件中形成第一沟槽，所述第一沟槽具有侧壁和在所述侧壁之间延伸宽度的底表面，并且沿着所述侧壁和底部形成电荷存储层第一沟槽的表面。该方法还包括在第一沟槽的底表面下方的衬底内注入离子以形成植入区域并退火植入区域，其中在退火之后，植入区域延伸底表面的宽度并沿着侧壁的一部分。

3. 发明申请

US20080153223A1 Using thick spacer for bitline implant then remove 有权
标题翻译：使用厚间隔物进行位线植入，然后移除
公开(公告)号：US20080153223A1
公开(公告)日：2008-06-26
申请号：US11724775
申请日：2007-03-16
申请人： Zhizheng Liu , Shankar Sinha , Timothy Thurgate , Ming-Sang Kwan
发明人： Zhizheng Liu , Shankar Sinha , Timothy Thurgate , Ming-Sang Kwan
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L27/115 , H01L27/11568
摘要： The present invention pertains to a system method of forming at least a portion of a dual bit memory core array upon a semiconductor substrate, the method comprising forming adjacent first memory cell process assemblies; comprising a charge trapping dielectric, a first polysilicon layer and defining a first bitline opening there between, forming first polysilicon layer features over the charge trapping dielectric layer, depositing a layer of second spacer material over the charge trapping dielectric and the first polysilicon layer features, forming a sidewall spacer adjacent to the charge trapping dielectric and the first polysilicon layer features to define a second bitline opening between the adjacent memory cells, performing a bitline implant, or pocket implants, or both into the bitline opening to establish buried bitlines within the substrate having respective bitline widths that are narrower than the respective widths of the first bitline openings, removing the sidewall spacers, and performing back end processing.
摘要翻译：本发明涉及一种在半导体衬底上形成双位存储器芯阵列的至少一部分的系统方法，该方法包括形成相邻的第一存储单元处理组件; 包括电荷捕获电介质，第一多晶硅层并且在其间限定第一位线开口，在电荷俘获电介质层上形成第一多晶硅层特征，在电荷俘获电介质和第一多晶硅层特征之上沉积第二间隔物材料层，形成与电荷俘获电介质相邻的侧壁间隔物，并且第一多晶硅层的特征在于限定相邻存储器单元之间的第二位线开口，执行位线注入或凹坑注入，或两者进入位线开口以在衬底内建立掩埋位线具有比第一位线开口的相应宽度窄的各自的位线宽度，去除侧壁间隔件，以及执行后端处理。

4. 发明授权

US08148770B1 Memory device with buried bit line structure 有权
标题翻译：具有埋地位线结构的存储器件
公开(公告)号：US08148770B1
公开(公告)日：2012-04-03
申请号：US11165329
申请日：2005-06-24
申请人： Shankar Sinha , Timothy Thurgate
发明人： Shankar Sinha , Timothy Thurgate
IPC分类号： H01L29/792 , H01L23/52 , H01L29/40 , H01L27/088 , H01L21/70 , H01L23/48 , H01L21/82 , H01L21/336 , H01L21/76 , H01L21/44 , H01L29/788
CPC分类号： H01L29/792 , H01L29/78675 , H01L29/7881 , Y10S438/954
摘要： A memory device includes a number of memory cells and a bit line structure coupled to a group of the memory cells. The bit line structure includes an upper portion having a first width, and a lower portion having a second width, where the first width is less than the second width.
摘要翻译：存储器件包括多个存储器单元和耦合到一组存储器单元的位线结构。位线结构包括具有第一宽度的上部和具有第二宽度的下部，其中第一宽度小于第二宽度。

5. 发明授权

US07888218B2 Using thick spacer for bitline implant then remove 有权
标题翻译：使用厚间隔物进行位线植入，然后移除
公开(公告)号：US07888218B2
公开(公告)日：2011-02-15
申请号：US11724775
申请日：2007-03-16
申请人： Zhizheng Liu , Shankar Sinha , Timothy Thurgate , Ming-Sang Kwan
发明人： Zhizheng Liu , Shankar Sinha , Timothy Thurgate , Ming-Sang Kwan
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11568
摘要： The present invention pertains to a system method of forming at least a portion of a dual bit memory core array upon a semiconductor substrate, the method comprising forming adjacent first memory cell process assemblies; comprising a charge trapping dielectric, a first polysilicon layer and defining a first bitline opening there between, forming first polysilicon layer features over the charge trapping dielectric layer, depositing a layer of second spacer material over the charge trapping dielectric and the first polysilicon layer features, forming a sidewall spacer adjacent to the charge trapping dielectric and the first polysilicon layer features to define a second bitline opening between the adjacent memory cells, performing a bitline implant, or pocket implants, or both into the bitline opening to establish buried bitlines within the substrate having respective bitline widths that are narrower than the respective widths of the first bitline openings, removing the sidewall spacers, and performing back end processing.
摘要翻译：本发明涉及一种在半导体衬底上形成双位存储器芯阵列的至少一部分的系统方法，该方法包括形成相邻的第一存储单元处理组件; 包括电荷捕获电介质，第一多晶硅层并且在其间限定第一位线开口，在电荷俘获电介质层上形成第一多晶硅层特征，在电荷俘获电介质和第一多晶硅层特征之上沉积第二间隔物材料层，形成与电荷俘获电介质相邻的侧壁间隔物，并且第一多晶硅层的特征在于限定相邻存储器单元之间的第二位线开口，执行位线注入或凹坑注入，或两者进入位线开口以在衬底内建立掩埋位线具有比第一位线开口的相应宽度窄的各自的位线宽度，去除侧壁间隔件，以及执行后端处理。

6. 发明授权

US08531878B2 Techniques for providing a semiconductor memory device 有权
标题翻译：提供半导体存储器件的技术
公开(公告)号：US08531878B2
公开(公告)日：2013-09-10
申请号：US13109821
申请日：2011-05-17
申请人： Srinivasa Rao Banna , Michael A. Van Buskirk , Timothy Thurgate
发明人： Srinivasa Rao Banna , Michael A. Van Buskirk , Timothy Thurgate
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0441 , G11C16/0475 , G11C16/0483 , H01L27/11556 , H01L29/66825 , H01L29/7889
摘要： Techniques for providing a semiconductor memory device are disclosed. In one particular embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns, each memory cell. Each of the memory cell may include a first region coupled to a source line, a second region coupled to a bit line, and a body region capacitively coupled to at least one word line via a gate region and disposed between the first region and the second region, wherein the body region may include a plurality of floating body regions and a plurality of floating gate regions capacitively coupled to the at least one word line.
摘要翻译：公开了一种用于提供半导体存储器件的技术。在一个特定实施例中，这些技术可被实现为半导体存储器件，其包括布置成行和列阵列的多个存储器单元，每个存储器单元。每个存储单元可以包括耦合到源极线的第一区域，耦合到位线的第二区域和经由栅极区域电容耦合到至少一个字线并且被布置在第一区域和第二区域之间的体区域区域，其中所述主体区域可以包括多个浮动体区域和电容耦合到所述至少一个字线的多个浮动栅极区域。

7. 发明授权

US08208296B2 Apparatus and method for extended nitride layer in a flash memory 有权
标题翻译：闪存中的延伸氮化物层的装置和方法
公开(公告)号：US08208296B2
公开(公告)日：2012-06-26
申请号：US12706710
申请日：2010-02-16
申请人： Timothy Thurgate , Shenqing Fang , Kuo Tung Chang , Youseok Suh
发明人： Timothy Thurgate , Shenqing Fang , Kuo Tung Chang , Youseok Suh
IPC分类号： G11C11/34
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/11568 , H01L29/66833
摘要： A method and apparatus for storing information is provided. A core region of memory includes a semiconductor layer, at least one shallow trench, an insulator, and a charge-trapping layer. The semiconductor layer includes at least one source/drain region, and the insulator disposed above the source/drain region. The charge trapping layer is within the insulator, and the charge trapping layer is above the entire width of the source/drain region, and extends at least one angstrom beyond the width of the source/drain region, so that a portion the charge trapping layer extends into at least one shallow trench.
摘要翻译：提供了一种用于存储信息的方法和装置。存储器的核心区域包括半导体层，至少一个浅沟槽，绝缘体和电荷俘获层。半导体层包括至少一个源极/漏极区域，以及设置在源极/漏极区域上方的绝缘体。电荷捕获层在绝缘体内，并且电荷捕获层高于源/漏区的整个宽度，并且延伸超过源极/漏极区的宽度至少一埃，使得电荷捕获层延伸到至少一个浅沟槽中。

8. 发明授权

US07785965B2 Dual storage node memory devices and methods for fabricating the same 有权
标题翻译：双存储节点存储器件及其制造方法
公开(公告)号：US07785965B2
公开(公告)日：2010-08-31
申请号：US11530145
申请日：2006-09-08
申请人： Unsoon Kim , Kyunghoon Min , Ning Cheng , Hiroyuki Kinoshita , Sugino Rinji , Timothy Thurgate , Angela Hui , Jihwan Choi , Chi Chang
发明人： Unsoon Kim , Kyunghoon Min , Ning Cheng , Hiroyuki Kinoshita , Sugino Rinji , Timothy Thurgate , Angela Hui , Jihwan Choi , Chi Chang
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11568 , H01L29/42352 , H01L29/7923
摘要： Dual storage node memory devices and methods for fabricating dual storage node memory devices have been provided. In accordance with an exemplary embodiment, a method includes the steps of etching a plurality of trenches in a semiconductor substrate and forming a layered structure within the trenches. The layered structure includes a tunnel dielectric layer and a charge storage layer. Bit lines are formed within the semiconductor substrate and a layer of conductive material is deposited overlying the layered structure.
摘要翻译：已经提供了双存储节点存储器件和用于制造双存储节点存储器件的方法。根据示例性实施例，一种方法包括以下步骤：蚀刻半导体衬底中的多个沟槽并在沟槽内形成分层结构。层状结构包括隧道介电层和电荷存储层。位线形成在半导体衬底内，并且一层导电材料沉积在层叠结构之上。

9. 发明申请

US20080279014A1 MULTI-PHASE WORDLINE ERASING FOR FLASH MEMORY 有权
标题翻译：闪存存储器的多相WORDLINE擦除
公开(公告)号：US20080279014A1
公开(公告)日：2008-11-13
申请号：US11745327
申请日：2007-05-07
申请人： Xuguang Wang , Yi He , Zhizheng Liu , Sung-Yong Chung , Darlene G. Hamilton , Ashot Melik-Martirosian , Gulzar Kathawala , Ming Sang Kwan , Mark Randolph , Timothy Thurgate
发明人： Xuguang Wang , Yi He , Zhizheng Liu , Sung-Yong Chung , Darlene G. Hamilton , Ashot Melik-Martirosian , Gulzar Kathawala , Ming Sang Kwan , Mark Randolph , Timothy Thurgate
IPC分类号： G11C11/34
CPC分类号： G11C16/16
摘要： Erasing wordlines at the same time can cause undesirable results because some wordlines are affected by electromagnetic waves of other wordlines. However, other wordlines are not affected because they are next to contacts. Therefore, it can be beneficial to erase wordlines in a multi-phase sequence that allows for erasing wordlines without an impact from other wordlines.
摘要翻译：同时删除字线可能会导致不良结果，因为某些字线受到其他字线的电磁波的影响。然而，其他字线不受影响，因为它们在联系人旁边。因此，删除允许擦除字线而不受其他字线影响的多相序列中的字线可能是有益的。

10. 发明授权

US06177322B1 High voltage transistor with high gated diode breakdown voltage 有权
标题翻译：具有高门极二极管击穿电压的高压晶体管
公开(公告)号：US06177322B1
公开(公告)日：2001-01-23
申请号：US09177817
申请日：1998-10-23
申请人： Narbeh Derhacobian , Pau-Ling Chen , Hao Fang , Timothy Thurgate
发明人： Narbeh Derhacobian , Pau-Ling Chen , Hao Fang , Timothy Thurgate
IPC分类号： H01L21336
CPC分类号： H01L29/66575 , H01L29/1033 , H01L29/41775
摘要： A high voltage transistor exhibiting high gated diode breakdown voltage is formed while avoiding an excessive number of costly masking steps. Embodiments include providing a high gated diode breakdown voltage by masking the high voltage junctions from the conventional field implant, masking the source/drain regions from the conventional threshold adjust implant, providing a thick gate oxide layer, employing a very lightly doped n-type implant in lieu of conventional n+ and LDD implants, and forming contacts to the source and drain regions at a minimum distance from the gate.
摘要翻译：形成表现出高选通二极管击穿电压的高压晶体管，同时避免过多数量的昂贵的掩蔽步骤。实施例包括通过掩盖来自常规场注入的高电压接头来提供高门控二极管击穿电压，从常规阈值调整注入屏蔽源极/漏极区域，提供厚栅极氧化物层，采用非常轻掺杂的n型注入代替常规的n +和LDD植入物，并且在与栅极最小距离处形成与源区和漏区的接触。

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