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1. 发明授权

US08409952B2 Method of forming an electronic device including forming a charge storage element in a trench of a workpiece 有权
标题翻译：形成电子器件的方法，包括在工件的沟槽中形成电荷存储元件
公开(公告)号：US08409952B2
公开(公告)日：2013-04-02
申请号：US12102488
申请日：2008-04-14
申请人： Suketu Arun Parikh , Olov B. Karlsson , Yun Sun , Shankar Sinha , Timothy Thurgate
发明人： Suketu Arun Parikh , Olov B. Karlsson , Yun Sun , Shankar Sinha , Timothy Thurgate
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L21/26586 , H01L27/115 , H01L29/1041 , H01L29/66666 , H01L29/7827
摘要： A method of forming an electronic device including forming a first trench in a workpiece including a substrate, the first trench having side walls and a bottom surface extending for a width between the side walls and forming a charge-storage layer along the side walls and bottom surface of the first trench. The method further includes implanting ions within the substrate underlying the bottom surface of the first trench to form an implant region and annealing the implant region, wherein after annealing, the implant region extends the width of the bottom surface and along a portion of the side walls.
摘要翻译：一种形成电子器件的方法，包括在包括衬底的工件中形成第一沟槽，所述第一沟槽具有侧壁和在所述侧壁之间延伸宽度的底表面，并且沿着所述侧壁和底部形成电荷存储层第一沟槽的表面。该方法还包括在第一沟槽的底表面下方的衬底内注入离子以形成植入区域并退火植入区域，其中在退火之后，植入区域延伸底表面的宽度并沿着侧壁的一部分。

2. 发明申请

US20090256242A1 METHOD OF FORMING AN ELECTRONIC DEVICE INCLUDING FORMING A CHARGE STORAGE ELEMENT IN A TRENCH OF A WORKPIECE 有权
标题翻译：形成电子装置的方法，包括在工作台的形式中形成充电储存元件
公开(公告)号：US20090256242A1
公开(公告)日：2009-10-15
申请号：US12102488
申请日：2008-04-14
申请人： Suketu Arun Parikh , Olov B. Karlsson , Yu Sun , Shankar Sinha , Timothy Thurgate
发明人： Suketu Arun Parikh , Olov B. Karlsson , Yu Sun , Shankar Sinha , Timothy Thurgate
IPC分类号： H01L21/425 , H01L23/58
CPC分类号： H01L27/11568 , H01L21/26586 , H01L27/115 , H01L29/1041 , H01L29/66666 , H01L29/7827
摘要： A method of forming an electronic device including forming a first trench in a workpiece including a substrate, the first trench having side walls and a bottom surface extending for a width between the side walls and forming a charge-storage layer along the side walls and bottom surface of the first trench. The method further includes implanting ions within the substrate underlying the bottom surface of the first trench to form an implant region and annealing the implant region, wherein after annealing, the implant region extends the width of the bottom surface and along a portion of the side walls.
摘要翻译：一种形成电子器件的方法，包括在包括衬底的工件中形成第一沟槽，所述第一沟槽具有侧壁和在所述侧壁之间延伸宽度的底表面，并且沿着所述侧壁和底部形成电荷存储层第一沟槽的表面。该方法还包括在第一沟槽的底表面下方的衬底内注入离子以形成植入区域并退火植入区域，其中在退火之后，植入区域延伸底表面的宽度并沿着侧壁的一部分。

3. 发明授权

US07682905B2 Self aligned narrow storage elements for advanced memory device 有权
标题翻译：自对准窄存储元件，用于高级存储器件
公开(公告)号：US07682905B2
公开(公告)日：2010-03-23
申请号：US11746122
申请日：2007-05-09
申请人： Suketu Arun Parikh
发明人： Suketu Arun Parikh
IPC分类号： H01L21/8247
CPC分类号： H01L27/115 , H01L21/0337 , H01L21/0338 , H01L21/28282 , H01L21/28291 , H01L21/31144 , H01L27/11568 , H01L29/66833 , H01L29/792 , Y10S438/954
摘要： A method of forming a sub-lithographic charge storage element on a semiconductor substrate is provided. The method can involve providing first and second layers on a semiconductor substrate, a thickness of the first layer being larger than a thickness of the second layer; forming a spacer adjacent a side surface of the first layer and on a portion of an upper surface of the second layer; and removing an exposed portion of the second layer that is not covered by the spacer. By removing the exposed portion of the second layer while leaving a portion of the second layer that is protected by the spacer, the method can make a sub-lithographic charge storage element from the remaining portion of the second layer on the semiconductor substrate.
摘要翻译：提供了在半导体衬底上形成次光刻电荷存储元件的方法。该方法可以包括在半导体衬底上提供第一层和第二层，第一层的厚度大于第二层的厚度; 在所述第一层的侧表面和所述第二层的上表面的一部分上形成间隔物; 以及去除未被间隔物覆盖的第二层的暴露部分。通过去除第二层的暴露部分，同时留下被间隔物保护的第二层的一部分，该方法可以从半导体衬底上的第二层的剩余部分制造亚光刻电荷存储元件。

4. 发明授权

US08476695B2 Self aligned narrow storage elements for advanced memory device 有权
标题翻译：自对准窄存储元件，用于高级存储器件
公开(公告)号：US08476695B2
公开(公告)日：2013-07-02
申请号：US12697707
申请日：2010-02-01
申请人： Suketu Arun Parikh
发明人： Suketu Arun Parikh
IPC分类号： H01L29/792
CPC分类号： H01L27/115 , H01L21/0337 , H01L21/0338 , H01L21/28282 , H01L21/28291 , H01L21/31144 , H01L27/11568 , H01L29/66833 , H01L29/792 , Y10S438/954
摘要： A method of forming a sub-lithographic charge storage element on a semiconductor substrate is provided. The method can involve providing first and second layers on a semiconductor substrate, a thickness of the first layer being larger than a thickness of the second layer; forming a spacer adjacent a side surface of the first layer and on a portion of an upper surface of the second layer; and removing an exposed portion of the second layer that is not covered by the spacer. By removing the exposed portion of the second layer while leaving a portion of the second layer that is protected by the spacer, the method can make a sub-lithographic charge storage element from the remaining portion of the second layer on the semiconductor substrate.
摘要翻译：提供了在半导体衬底上形成次光刻电荷存储元件的方法。该方法可以包括在半导体衬底上提供第一层和第二层，第一层的厚度大于第二层的厚度; 在所述第一层的侧表面和所述第二层的上表面的一部分上形成间隔物; 以及去除未被间隔物覆盖的第二层的暴露部分。通过去除第二层的暴露部分，同时留下被间隔物保护的第二层的一部分，该方法可以从半导体衬底上的第二层的剩余部分制造亚光刻电荷存储元件。

5. 发明申请

US20100133605A1 SELF ALIGNED NARROW STORAGE ELEMENTS FOR ADVANCED MEMORY DEVICE 有权
标题翻译：用于高级存储器件的自对准的NARROW存储元件
公开(公告)号：US20100133605A1
公开(公告)日：2010-06-03
申请号：US12697707
申请日：2010-02-01
申请人： Suketu Arun Parikh
发明人： Suketu Arun Parikh
IPC分类号： H01L29/792
CPC分类号： H01L27/115 , H01L21/0337 , H01L21/0338 , H01L21/28282 , H01L21/28291 , H01L21/31144 , H01L27/11568 , H01L29/66833 , H01L29/792 , Y10S438/954
摘要： A method of forming a sub-lithographic charge storage element on a semiconductor substrate is provided. The method can involve providing first and second layers on a semiconductor substrate, a thickness of the first layer being larger than a thickness of the second layer; forming a spacer adjacent a side surface of the first layer and on a portion of an upper surface of the second layer; and removing an exposed portion of the second layer that is not covered by the spacer. By removing the exposed portion of the second layer while leaving a portion of the second layer that is protected by the spacer, the method can make a sub-lithographic charge storage element from the remaining portion of the second layer on the semiconductor substrate.
摘要翻译：提供了在半导体衬底上形成次光刻电荷存储元件的方法。该方法可以包括在半导体衬底上提供第一层和第二层，第一层的厚度大于第二层的厚度; 在所述第一层的侧表面和所述第二层的上表面的一部分上形成间隔物; 以及去除未被间隔物覆盖的第二层的暴露部分。通过去除第二层的暴露部分，同时留下被间隔物保护的第二层的一部分，该方法可以从半导体衬底上的第二层的剩余部分制造亚光刻电荷存储元件。

6. 发明申请

US20080280410A1 SELF ALIGNED NARROW STORAGE ELEMENTS FOR ADVANCED MEMORY DEVICE 有权
标题翻译：用于高级存储器件的自对准的NARROW存储元件
公开(公告)号：US20080280410A1
公开(公告)日：2008-11-13
申请号：US11746122
申请日：2007-05-09
申请人： Suketu Arun Parikh
发明人： Suketu Arun Parikh
IPC分类号： H01L21/8239 , H01L29/792
CPC分类号： H01L27/115 , H01L21/0337 , H01L21/0338 , H01L21/28282 , H01L21/28291 , H01L21/31144 , H01L27/11568 , H01L29/66833 , H01L29/792 , Y10S438/954
摘要： A method of forming a sub-lithographic charge storage element on a semiconductor substrate is provided. The method can involve providing first and second layers on a semiconductor substrate, a thickness of the first layer being larger than a thickness of the second layer; forming a spacer adjacent a side surface of the first layer and on a portion of an upper surface of the second layer; and removing an exposed portion of the second layer that is not covered by the spacer. By removing the exposed portion of the second layer while leaving a portion of the second layer that is protected by the spacer, the method can make a sub-lithographic charge storage element from the remaining portion of the second layer on the semiconductor substrate.
摘要翻译：提供了在半导体衬底上形成次光刻电荷存储元件的方法。该方法可以包括在半导体衬底上提供第一层和第二层，第一层的厚度大于第二层的厚度; 在所述第一层的侧表面和所述第二层的上表面的一部分上形成间隔物; 以及去除未被间隔物覆盖的第二层的暴露部分。通过去除第二层的暴露部分，同时留下被间隔物保护的第二层的一部分，该方法可以从半导体衬底上的第二层的剩余部分制造亚光刻电荷存储元件。

7. 发明授权

US08849438B2 Factory level process and final product performance control system 有权
标题翻译：工厂级流程和最终产品性能控制系统
公开(公告)号：US08849438B2
公开(公告)日：2014-09-30
申请号：US13299081
申请日：2011-11-17
申请人： Suketu Arun Parikh , Alexander T. Schwarm , Sanjiv Mittal , Charles Gay
发明人： Suketu Arun Parikh , Alexander T. Schwarm , Sanjiv Mittal , Charles Gay
IPC分类号： G06F17/00 , G05B13/02 , G06F19/00 , G01N37/00 , G06F11/30 , G21C17/00 , G06F11/00 , G05B19/418
CPC分类号： G05B19/41875 , G05B2219/32182 , Y02P90/12 , Y02P90/18 , Y02P90/22
摘要： A factory control server stores module configuration data for modules. The modules include processes for producing a final product and have corresponding module requirements. The factory control server analyzes in real-time actual product output data that is generated by a final product tester after a factory produces at least one final product to determine whether the actual product output data meets an expected product output. The factory control server analyzes actual module data in real-time to determine a new module requirement to cause new actual product output data for a subsequent final product to meet the expected product output in response to a determination that the actual product output data does not meet the expected product output. The factory control server notifies a module controller in real-time of the new module requirement. The module controller changes parameters in real-time to manufacture the subsequent final product.
摘要翻译：工厂控制服务器存储模块的模块配置数据。这些模块包括生产最终产品的过程，并具有相应的模块要求。工厂控制服务器在工厂生产至少一个最终产品之后分析由最终产品测试者生成的实时实际产品输出数据，以确定实际产品输出数据是否满足预期的产品输出。工厂控制服务器实时分析实际的模块数据，以确定新的模块要求，以便随后的最终产品产生新的实际产品输出数据以满足预期的产品输出以响应确定实际的产品输出数据不符合预期产品产量。工厂控制服务器实时通知模块控制器新模块要求。模块控制器实时更改参数以制造后续最终产品。

8. 发明申请

US20120130520A1 FACTORY LEVEL PROCESS AND FINAL PRODUCT PERFORMANCE CONTROL SYSTEM 有权
标题翻译：工厂级工艺和最终产品性能控制系统
公开(公告)号：US20120130520A1
公开(公告)日：2012-05-24
申请号：US13299081
申请日：2011-11-17
申请人： Suketu Arun Parikh , Alexander T. Schwarm , Sanjiv Mittal , Charles Gay
发明人： Suketu Arun Parikh , Alexander T. Schwarm , Sanjiv Mittal , Charles Gay
IPC分类号： G05B19/418
CPC分类号： G05B19/41875 , G05B2219/32182 , Y02P90/12 , Y02P90/18 , Y02P90/22
摘要： A factory control server stores module configuration data for modules. The modules include processes for producing a final product and have corresponding module requirements. The factory control server analyzes in real-time actual product output data that is generated by a final product tester after a factory produces at least one final product to determine whether the actual product output data meets an expected product output. The factory control server analyzes actual module data in real-time to determine a new module requirement to cause new actual product output data for a subsequent final product to meet the expected product output in response to a determination that the actual product output data does not meet the expected product output. The factory control server notifies a module controller in real-time of the new module requirement. The module controller changes parameters in real-time to manufacture the subsequent final product.
摘要翻译：工厂控制服务器存储模块的模块配置数据。这些模块包括生产最终产品的过程，并具有相应的模块要求。工厂控制服务器在工厂生产至少一个最终产品之后分析由最终产品测试者生成的实时实际产品输出数据，以确定实际产品输出数据是否满足预期的产品输出。工厂控制服务器实时分析实际的模块数据，以确定新的模块要求，以便随后的最终产品产生新的实际产品输出数据以满足预期的产品输出以响应确定实际的产品输出数据不符合预期产品产量。工厂控制服务器实时通知模块控制器新模块要求。模块控制器实时更改参数以制造后续最终产品。

9. 发明授权

US07781154B2 Method of forming damascene structure 有权
标题翻译：形成镶嵌结构的方法
公开(公告)号：US07781154B2
公开(公告)日：2010-08-24
申请号：US11390641
申请日：2006-03-28
申请人： Suketu Arun Parikh
发明人： Suketu Arun Parikh
IPC分类号： H01L21/00
CPC分类号： H01L21/76811 , H01L21/31144 , H01L21/76808
摘要： A method for forming a damascene structure utilizes dual hard mask layers and a thin etch stop layer, and does not require a sacrificial layer within the via. A floating etch stop layer can additionally be used. The dual hard masks may be formed of dielectric and neither of the hard masks is required to contain metal. The thin etch stop layer reduces capacitance problems.
摘要翻译：用于形成镶嵌结构的方法利用双硬掩模层和薄蚀刻停止层，并且不需要通孔内的牺牲层。另外可以使用浮动蚀刻停止层。双硬掩模可以由电介质形成，并且硬掩模都不需要包含金属。薄的蚀刻停止层减少电容问题。

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