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41. 发明授权

US06815292B1 Flash memory having improved core field isolation in select gate regions 有权
标题翻译：闪存在选择栅极区域具有改进的核心场隔离
公开(公告)号：US06815292B1
公开(公告)日：2004-11-09
申请号：US10260061
申请日：2002-09-27
申请人： Hao Fang , Mark S. Chang
发明人： Hao Fang , Mark S. Chang
IPC分类号： H01L2972
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/115 , H01L27/11531
摘要： A flash memory array having improved core field isolation in select gate regions via shallow trench isolation and field isolation implant after liner oxidation is disclosed. The flash memory array includes a core area and a periphery area, wherein the core area further includes a select gate region. The method of fabricating the flash memory array begins by patterning a layer of nitride over a substrate in active device locations. After the nitride is patterned, a silicon trench etch is performed to form trenches. After forming the trenches, a layer of liner oxide is grown in the trenches. Then, a field implant is performed in both the core area and periphery area to provide field isolation regions for the flash memory array with. Thereafter, poly1 is patterned in the core area to form floating gate and select word-lines.

42. 发明授权

US06773954B1 Methods of forming passive layers in organic memory cells 失效
标题翻译：在有机记忆细胞中形成钝化层的方法
公开(公告)号：US06773954B1
公开(公告)日：2004-08-10
申请号：US10313494
申请日：2002-12-05
申请人： Ramkumar Subramanian , Jane V. Oglesby , Sergey D. Lopatin , Mark S. Chang , Christopher F. Lyons , James J. Xie , Minh Van Ngo
发明人： Ramkumar Subramanian , Jane V. Oglesby , Sergey D. Lopatin , Mark S. Chang , Christopher F. Lyons , James J. Xie , Minh Van Ngo
IPC分类号： H01L5140
CPC分类号： G11C13/0014 , B82Y10/00 , G11C13/0016 , H01L27/28 , H01L51/0034 , H01L51/0035 , H01L51/0036 , H01L51/0037 , H01L51/0043 , H01L51/0053 , H01L51/0059 , H01L51/0062 , H01L51/0077 , H01L51/0078 , H01L51/0081 , H01L51/0085
摘要： Methods of making an organic memory cell made of two electrodes with a controllably conductive media between the two electrodes are disclosed. The controllably conductive Media contains an organic semiconductor layer and passive layer. In particular, novel methods of forming a electrode and adjacent passive layer are described.
摘要翻译：公开了在两个电极之间制造由具有可控导电介质的两个电极制成的有机存储单元的方法。可控导电介质包含有机半导体层和无源层。特别地，描述了形成电极和相邻钝化层的新颖方法。

43. 发明授权

US06764949B2 Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication 有权
公开(公告)号：US06764949B2
公开(公告)日：2004-07-20
申请号：US10334392
申请日：2002-12-30
申请人： Douglas J. Bonser , Marina V. Plat , Chih Yuh Yang , Scott A. Bell , Darin Chan , Philip A. Fisher , Christopher F. Lyons , Mark S. Chang , Pei-Yuan Gao , Marilyn I. Wright , Lu You , Srikanteswara Dakshina-Murthy
发明人： Douglas J. Bonser , Marina V. Plat , Chih Yuh Yang , Scott A. Bell , Darin Chan , Philip A. Fisher , Christopher F. Lyons , Mark S. Chang , Pei-Yuan Gao , Marilyn I. Wright , Lu You , Srikanteswara Dakshina-Murthy
IPC分类号： H01L2144
CPC分类号： H01L21/32139 , H01L21/0332
摘要： A hardmask stack is comprised of alternating layers of doped amorphous carbon and undoped amorphous carbon. The undoped amorphous carbon layers serve as buffer layers that constrain the effects of compressive stress within the doped amorphous carbon layers to prevent delamination. The stack is provided with a top capping layer. The layer beneath the capping layer is preferably undoped amorphous carbon to reduce photoresist poisoning. An alternative hardmask stack is comprised of alternating layers of capping material and amorphous carbon. The amorphous carbon layers may be doped or undoped. The capping material layers serve as buffer layers that constrain the effects of compressive stress within the amorphous carbon layers to prevent delamination. The top layer of the stack is formed of a capping material. The layer beneath the top layer is preferably undoped amorphous carbon to reduce photoresist poisoning. The lowest layer of the hardmask stack is preferably amorphous carbon to facilitate easy removal of the hardmask stack from underlying materials by an ashing process.

44. 发明授权

US06638358B1 Method and system for processing a semiconductor device 失效
标题翻译：用于处理半导体器件的方法和系统
公开(公告)号：US06638358B1
公开(公告)日：2003-10-28
申请号：US09483176
申请日：2000-01-13
申请人： Lu You , Mark S. Chang , Hao Fang
发明人： Lu You , Mark S. Chang , Hao Fang
IPC分类号： B05C500
CPC分类号： H01L21/02134 , H01L21/02282 , H01L21/3124 , H01L21/316 , H01L21/823468
摘要： The present invention is a method and system for processing a semiconductor device, the semiconductor device comprising at least two gate stacks and a spacer gap. The method and system comprise utilizing a spin-on technique at the transistor device level to provide an oxide spacer in the spacer gap and then curing the semiconductor device at a temperature above approximately 450° C. Through the use of a system/method in accordance with the present invention, the voids that are created in the spacer gaps during conventional semiconductor processing are eliminated. Furthermore, the oxide spacers posses the high quality characteristics that are typically provided through the use of the conventional CVD methodology. Accordingly, as a result of the use of the system/method in accordance with the present invention, the MOSFET oxide spacers are strengthened, which increases the reliability of the semiconductor device.
摘要翻译：本发明是用于处理半导体器件的方法和系统，该半导体器件包括至少两个栅极叠层和间隔物间隙。该方法和系统包括利用晶体管器件级上的旋涂技术在间隔物间隙中提供氧化物隔离物，然后在高于约450℃的温度下固化半导体器件。通过使用根据本发明的系统/方法利用本发明，消除了在常规半导体处理期间在间隔物间隙中产生的空隙。此外，氧化物间隔物具有通常通过使用常规CVD方法提供的高质量特性。因此，通过使用根据本发明的系统/方法的结果，MOSFET氧化物间隔物被加强，这增加了半导体器件的可靠性。

45. 发明授权

US06475847B1 Method for forming a semiconductor device with self-aligned contacts using a liner oxide layer 有权
标题翻译：使用衬垫氧化物层形成具有自对准触点的半导体器件的方法
公开(公告)号：US06475847B1
公开(公告)日：2002-11-05
申请号：US10109526
申请日：2002-03-27
申请人： Minh Van Ngo , Yu Sun , Fei Wang , Mark T. Ramsbey , Chi Chang , Angela T. Hui , Mark S. Chang
发明人： Minh Van Ngo , Yu Sun , Fei Wang , Mark T. Ramsbey , Chi Chang , Angela T. Hui , Mark S. Chang
IPC分类号： H01L218238
CPC分类号： H01L27/11521 , H01L21/76829 , H01L21/76897 , H01L27/115 , H01L2924/3011
摘要： A method for shrinking a semiconductor device and minimizing auto-doping problem is disclosed. An etch stop layer is eliminated and is replaced with a consumable liner oxide layer so that stacked gate structures of the device can be positioned closer together, thus permitting shrinking of the device. The liner oxide layer is formed directly over a substrate and in contact with stacked gate structures, sidewall spacers, and sources and drains formed on the substrate, and serves as an auto-doping barrier for the dielectric layer to prevent boron and phosphorous formed in the dielectric layer from auto-doping into the sources and drains.
摘要翻译：公开了一种缩小半导体器件并最小化自动掺杂问题的方法。蚀刻停止层被消除并且被可消耗的衬垫氧化物层代替，使得该器件的层叠栅极结构可以被更靠近地放置在一起，从而允许器件收缩。衬垫氧化物层直接形成在衬底上并与堆叠的栅极结构，侧壁间隔物以及形成在衬底上的源极和漏极接触，并且用作电介质层的自动掺杂势垒，以防止形成在衬底中的硼和磷电介质层自动掺入源和漏极。

46. 发明授权

US06326310B1 Method and system for providing shallow trench profile shaping through spacer and etching 失效
标题翻译：通过间隔和蚀刻提供浅沟槽轮廓成形的方法和系统
公开(公告)号：US06326310B1
公开(公告)日：2001-12-04
申请号：US08992623
申请日：1997-12-17
申请人： Mark S. Chang , Yowjuang W. Liu
发明人： Mark S. Chang , Yowjuang W. Liu
IPC分类号： H01L21311
CPC分类号： H01L21/3086 , H01L21/76232
摘要： A system and method for providing a trench in a material using semiconductor processing is disclosed. In one aspect, the method and system include (a) providing a spacer, (b) etching the material, and (c) repeating steps (a) and (b) a sufficient number of times to achieve a desired profile for the trench. The spacer is insensitive to an etch of the material. The material is exposed adjacent to the spacer. In another aspect, the method and system include (a) providing a spacer, (b) etching the material, (c) stripping the spacer, and (d) repeating steps (a) through (c) until a desired profile for the trench is achieved. Each time steps (a) through (c) are repeated via step (d), a thinner spacer is provided. In addition, the spacer is insensitive to an etch of the material. The material is exposed adjacent to the spacer.
摘要翻译：公开了一种使用半导体处理在材料中提供沟槽的系统和方法。在一个方面，该方法和系统包括（a）提供间隔物，（b）蚀刻该材料，和（c）重复步骤（a）和（b）足够的次数以达到沟槽所需的轮廓。间隔物对材料的蚀刻不敏感。材料与间隔物相邻地露出。在另一方面，该方法和系统包括（a）提供间隔物，（b）蚀刻该材料，（c）剥离间隔物，和（d）重复步骤（a）至（c）直到沟槽的期望曲线已完成。每次通过步骤（d）重复步骤（a）至（c）时，提供更薄的间隔物。此外，间隔物对材料的蚀刻不敏感。材料与间隔物相邻地露出。

47. 发明授权

US06306706B1 Method and system for fabricating a flash memory array 有权
标题翻译：用于制造闪存阵列的方法和系统
公开(公告)号：US06306706B1
公开(公告)日：2001-10-23
申请号：US09538922
申请日：2000-03-30
申请人： Maria C. Chan , Hao Fang , Mark S. Chang
发明人： Maria C. Chan , Hao Fang , Mark S. Chang
IPC分类号： H01L218247
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11531 , Y10T29/41
摘要： A method and system for fabricating a flash memory array comprising a core area and a periphery area is disclosed. The method and system comprises depositing a layer of poly2 over the core area and the periphery area, selectively etching the core area, and selectively etching the poly2 only in the periphery area wherein the occurrence of stringers is reduced. Through the use of the preferred embodiment of the present invention, the core and periphery areas are etched separately after the deposition of the poly2, thereby reducing the occurrence of stringers at the core/periphery interface. Accordingly, the occurrence of unwanted electrical shorting paths between the adjacent transistors is substantially reduced.
摘要翻译：公开了一种用于制造包括芯区域和外围区域的闪存阵列的方法和系统。该方法和系统包括在核心区域和外围区域上沉积多晶硅层2，选择性地蚀刻核心区域，并且仅在缩小桁条发生的周边区域中选择性地蚀刻聚二元体。通过使用本发明的优选实施例，在沉积poly2之后分别蚀刻芯和外围区域，从而减少在芯/周边界面处的桁条的发生。因此，相邻晶体管之间不需要的电短路径的发生显着减少。

48. 发明授权

US06200884B1 Method for shaping photoresist mask to improve high aspect ratio ion implantation 有权
标题翻译：光刻胶掩模整形以改善垂直离子注入的方法
公开(公告)号：US06200884B1
公开(公告)日：2001-03-13
申请号：US09364976
申请日：1999-07-31
申请人： Chih-Yuh Yang , Mark S. Chang
发明人： Chih-Yuh Yang , Mark S. Chang
IPC分类号： H01L21425
CPC分类号： H01L21/0274 , H01L21/266 , H01L21/31138
摘要： A method for making a ULSI MOSFET chip includes masking areas such as transistor gates with photoresist mask regions. Prior to ion implantation, the top shoulders of the mask regions are etched away, to round off the shoulders. This promotes subsequent efficient quasi-vertical ion implantation, commonly referred to as “high aspect ratio implantation” in the semiconductor industry.
摘要翻译：制造ULSI MOSFET芯片的方法包括具有光致抗蚀剂掩模区域的诸如晶体管栅极的掩模区域。在离子注入之前，掩模区域的顶部肩部被蚀刻掉，从而使肩部圆整。这促进随后的有效的准垂直离子注入，在半导体工业中通常被称为“高纵横比植入”。

49. 发明授权

US5965934A Processing techniques for achieving production-worthy, low dielectric, low interconnect resistance and high performance ICS 失效
标题翻译：用于实现生产有价值，低电介质，低互连电阻和高性能ICS的加工技术
公开(公告)号：US5965934A
公开(公告)日：1999-10-12
申请号：US681141
申请日：1996-07-22
申请人： Robin W. Cheung , Mark S. Chang
发明人： Robin W. Cheung , Mark S. Chang
IPC分类号： H01L21/28 , H01L21/027 , H01L21/768 , H01L23/532 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/53242 , H01L23/53228 , H01L23/53238 , H01L23/53252 , H01L23/5329 , H01L2924/0002 , Y10S148/10 , Y10S148/106 , Y10S438/95 , Y10S438/951
摘要： The interconnects in a semiconductor device contacting metal lines comprise a low resistance metal, such as copper, gold, silver, or platinum, and are separated by a material having a low dielectric constant, such as benzocyclobutene or a derivative thereof A tri-layer resist structure is used, together with a lift-off process, to form the interconnects. The low dielectric constant material provides a diffusion barrier to the diffusion of the low resistance metal. The tri-layer resist comprises a first layer of a dissolvable polymer, a second layer of a hard mask material, and a third layer of a resist material. The resulting structure provides an integrated circuit with increased speed and ease of fabrication.
摘要翻译：接触金属线的半导体器件中的互连包括诸如铜，金，银或铂的低电阻金属，并且由具有低介电常数的材料例如苯并环丁烯或其衍生物分离。三层抗蚀剂结构与剥离过程一起使用以形成互连。低介电常数材料为低电阻金属的扩散提供扩散阻挡层。三层抗蚀剂包括可溶解聚合物的第一层，硬掩模材料的第二层和抗蚀剂材料的第三层。所得到的结构提供了具有增加的速度和易于制造的集成电路。

50. 发明授权

US5559055A Method of decreased interlayer dielectric constant in a multilayer interconnect structure to increase device speed performance 失效
标题翻译：降低多层互连结构中层间介电常数的方法，以提高器件速度性能
公开(公告)号：US5559055A
公开(公告)日：1996-09-24
申请号：US360857
申请日：1994-12-21
申请人： Mark S. Chang , Robin W. Cheung
发明人： Mark S. Chang , Robin W. Cheung
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/7682 , Y10S148/05
摘要： The RC time constant of a semiconductor device is reduced by decreasing the capacitance C. The decrease in capacitance is achieved by replacing the interlayer silicon dioxide (dielectric constant of 4.0) with air (dielectric constant of 1.0). Alternatively, the air space can also be filled with another low dielectric constant material, such as an organic material having a dielectric constant in the range of about 2.2 to 3.4. In either case, the final effective dielectric constant of the device is lowered. As a result of lowering the effective dielectric constant, a smaller RC time constant is achieved, which results in higher device speed.
摘要翻译：通过降低电容C来减小半导体器件的RC时间常数。通过用空气（介电常数为1.0）代替层间二氧化硅（介电常数为4.0）来实现电容的减小。或者，空气空间还可以用另一种低介电常数材料填充，例如介电常数在约2.2至3.4范围内的有机材料。在任一情况下，器件的最终有效介电常数降低。作为降低有效介电常数的结果，实现较小的RC时间常数，这导致更高的器件速度。

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