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1. 发明授权

US06764949B2 Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication 有权
公开(公告)号：US06764949B2
公开(公告)日：2004-07-20
申请号：US10334392
申请日：2002-12-30
申请人： Douglas J. Bonser , Marina V. Plat , Chih Yuh Yang , Scott A. Bell , Darin Chan , Philip A. Fisher , Christopher F. Lyons , Mark S. Chang , Pei-Yuan Gao , Marilyn I. Wright , Lu You , Srikanteswara Dakshina-Murthy
发明人： Douglas J. Bonser , Marina V. Plat , Chih Yuh Yang , Scott A. Bell , Darin Chan , Philip A. Fisher , Christopher F. Lyons , Mark S. Chang , Pei-Yuan Gao , Marilyn I. Wright , Lu You , Srikanteswara Dakshina-Murthy
IPC分类号： H01L2144
CPC分类号： H01L21/32139 , H01L21/0332
摘要： A hardmask stack is comprised of alternating layers of doped amorphous carbon and undoped amorphous carbon. The undoped amorphous carbon layers serve as buffer layers that constrain the effects of compressive stress within the doped amorphous carbon layers to prevent delamination. The stack is provided with a top capping layer. The layer beneath the capping layer is preferably undoped amorphous carbon to reduce photoresist poisoning. An alternative hardmask stack is comprised of alternating layers of capping material and amorphous carbon. The amorphous carbon layers may be doped or undoped. The capping material layers serve as buffer layers that constrain the effects of compressive stress within the amorphous carbon layers to prevent delamination. The top layer of the stack is formed of a capping material. The layer beneath the top layer is preferably undoped amorphous carbon to reduce photoresist poisoning. The lowest layer of the hardmask stack is preferably amorphous carbon to facilitate easy removal of the hardmask stack from underlying materials by an ashing process.

2. 发明授权

US06773998B1 Modified film stack and patterning strategy for stress compensation and prevention of pattern distortion in amorphous carbon gate patterning 有权
标题翻译：改进的薄膜堆叠和图案化策略，用于应力补偿和防止无定形碳栅图案中的图案变形
公开(公告)号：US06773998B1
公开(公告)日：2004-08-10
申请号：US10445129
申请日：2003-05-20
申请人： Philip A. Fisher , Marina V. Plat , Chih-Yuh Yang , Christopher F. Lyons , Scott A. Bell , Douglas J. Bonser , Lu You , Srikanteswara Dakshina-Murthy
发明人： Philip A. Fisher , Marina V. Plat , Chih-Yuh Yang , Christopher F. Lyons , Scott A. Bell , Douglas J. Bonser , Lu You , Srikanteswara Dakshina-Murthy
IPC分类号： H01L21336
CPC分类号： H01L21/0276 , H01L21/0332 , H01L21/28123 , H01L21/31116 , H01L21/3146 , H01L21/32137 , H01L21/32139
摘要： A method for an integrated circuit includes the use of an amorphous carbon ARC mask. A layer of amorphous carbon material is deposited above a layer of conductive material, and a layer of anti-reflective coating (ARC) material is deposited over the layer of amorphous carbon material. The layer of amorphous carbon material and the layer of ARC material are etched to form a mask comprising an ARC material portion and an amorphous carbon portion. A feature may then be formed in the layer of conductive material by etching the layer of conductive material in accordance with the mask.
摘要翻译：集成电路的方法包括使用无定形碳ARC掩模。一层非晶碳材料沉积在导电材料层上方，并且一层抗反射涂层（ARC）材料沉积在无定形碳材料层上。蚀刻无定形碳材料层和ARC材料层以形成包含ARC材料部分和无定形碳部分的掩模。然后可以通过根据掩模蚀刻导电材料层而在导电材料层中形成特征。

3. 发明授权

US06764947B1 Method for reducing gate line deformation and reducing gate line widths in semiconductor devices 有权
标题翻译：减少半导体器件栅极线变形和减小栅极线宽度的方法
公开(公告)号：US06764947B1
公开(公告)日：2004-07-20
申请号：US10366801
申请日：2003-02-14
申请人： Darin Chan , Douglas J. Bonser , Marina V. Plat , Marilyn I. Wright , Chih Yuh Yang , Lu You , Scott A. Bell , Philip A. Fisher
发明人： Darin Chan , Douglas J. Bonser , Marina V. Plat , Marilyn I. Wright , Chih Yuh Yang , Lu You , Scott A. Bell , Philip A. Fisher
IPC分类号： H01L214763
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/28123 , H01L21/32139
摘要： A silicon oxide stress relief portion is provided between an amorphous carbon hardmask and a polysilicon layer to be etched to form a gate line. The stress relief portion relieves stress between the hardmask and the polysilicon, thereby reducing the risk of delamination of the hardmask prior to patterning of the polysilicon. The stress relief portion may be trimmed prior to patterning and used as an etch mask for patterning the polysilicon. The amorphous carbon hardmasked may be trimmed prior to patterning the stress relief portion to achieve a further reduction in gate line width.
摘要翻译：在非晶碳硬掩模和待蚀刻的多晶硅层之间设置氧化硅应力释放部分以形成栅极线。应力消除部分减轻硬掩模和多晶硅之间的应力，从而降低在多晶硅图案化之前硬掩模的分层的风险。应力消除部分可以在图案化之前被修整，并且用作图案化多晶硅的蚀刻掩模。在图案化应力释放部分之前，可以修剪硬掩模的无定形碳以实现栅极线宽度的进一步降低。

4. 发明授权

US07268066B2 Method for semiconductor gate line dimension reduction 有权
标题翻译：半导体栅极线尺寸减小的方法
公开(公告)号：US07268066B2
公开(公告)日：2007-09-11
申请号：US10922093
申请日：2004-08-19
申请人： Douglas J. Bonser , Marina V. Plat , Chih Yuh Yang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Christopher F. Lyons
发明人： Douglas J. Bonser , Marina V. Plat , Chih Yuh Yang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Christopher F. Lyons
IPC分类号： H01L21/4763
CPC分类号： H01L29/66477 , H01L21/28123 , H01L29/1045 , H01L29/1054 , H01L29/665
摘要： To reduce the width of a MOSFET gate, the gate is formed with a hardmask formed thereupon. An isotropic etch is then performed to trim the gate in order to reduce the width of the gate. The resulting gate may be formed with a width that is narrower than a minimum width achievable solely through conventional projection lithography techniques.
摘要翻译：为了减小MOSFET栅极的宽度，栅极形成有在其上形成的硬掩模。然后执行各向同性蚀刻以修剪栅极，以便减小栅极的宽度。所形成的栅极可以形成为比仅通过常规投影光刻技术可实现的最小宽度窄的宽度。

5. 发明授权

US06849530B2 Method for semiconductor gate line dimension reduction 失效
公开(公告)号：US06849530B2
公开(公告)日：2005-02-01
申请号：US10334337
申请日：2002-12-30
申请人： Douglas J. Bonser , Marina V. Plat , Chih Yuh Yang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Christopher F. Lyons
发明人： Douglas J. Bonser , Marina V. Plat , Chih Yuh Yang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Christopher F. Lyons
IPC分类号： H01L21/28 , H01L21/4763
CPC分类号： H01L21/28123
摘要： To reduce the width of a MOSFET gate, the gate is formed with a hardmask formed thereupon. An isotropic etch is then performed to trim the gate in order to reduce the width of the gate. The resulting gate may be formed with a width that is narrower than a minimum width achievable solely through conventional projection lithography techniques.

6. 发明授权

US06750127B1 Method for fabricating a semiconductor device using amorphous carbon having improved etch resistance 有权
标题翻译：使用具有改善的耐蚀性的非晶碳制造半导体器件的方法
公开(公告)号：US06750127B1
公开(公告)日：2004-06-15
申请号：US10367407
申请日：2003-02-14
申请人： Mark S. Chang , Darin Chan , Chih Yuh Yang , Lu You , Scott A. Bell , Srikanteswara Dakshina-Murthy , Douglas J. Bonser
发明人： Mark S. Chang , Darin Chan , Chih Yuh Yang , Lu You , Scott A. Bell , Srikanteswara Dakshina-Murthy , Douglas J. Bonser
IPC分类号： H01L213205
CPC分类号： H01L21/32139 , H01L21/0332 , H01L21/0337
摘要： An amorphous carbon layer is implanted with one or more dopants that enhance the etch resistivity of the amorphous carbon to etchants such as chlorine and HBr that are typically used to etch polysilicon. Such a layer may be pattern to form a handmask for etching polysilicon that provides improved pattern transfer accuracy compared to conventional undoped amorphous carbon.
摘要翻译：注入一个或多个掺杂剂的无定形碳层，其增强无定形碳对通常用于蚀刻多晶硅的蚀刻剂如氯和HBr的蚀刻电阻率。这样的层可以被图案化以形成用于蚀刻多晶硅的手掩模，其与常规未掺杂的无定形碳相比提供改进的图案转印精度。

7. 发明授权

US06797552B1 Method for defect reduction and enhanced control over critical dimensions and profiles in semiconductor devices 有权
标题翻译：在半导体器件中的缺陷减少和关键尺寸和轮廓的增强控制的方法
公开(公告)号：US06797552B1
公开(公告)日：2004-09-28
申请号：US10299434
申请日：2002-11-19
申请人： Mark S. Chang , Douglas J. Bonser , Marina V. Plat , Chih Yuh Yang , Scott A. Bell , Srikanteswara Dakshina-Murthy
发明人： Mark S. Chang , Douglas J. Bonser , Marina V. Plat , Chih Yuh Yang , Scott A. Bell , Srikanteswara Dakshina-Murthy
IPC分类号： H01L21336
CPC分类号： H01L21/823456 , H01L21/0332 , H01L21/31138 , H01L21/32137 , H01L21/32139
摘要： A layer of material is patterned anisotropically using a bi-layer hardmask structure. Residual photoresist from a photoresist mask used to pattern an upper layer of the bi-layer hardmask is removed prior to patterning of the polysilicon layer. Passivation agents are later introduced from an external source during patterning of the layer of material. This provides a substantially uniform supply of passivation agents to all parts of the layer of material as it is being etched, rather than relying on the generation of passivation agents from consumption of photoresist during etching, which can produce local non-uniformities of passivation agent availability owing to differences in photoresist thickness remaining on different sized features.
摘要翻译：使用双层硬掩模结构各向异性地图案化材料层。在用于图案化双层硬掩模的上层的光致抗蚀剂掩模的残余光致抗蚀剂在图案化多晶硅层之前被去除。在图案化材料层之后，钝化剂随后从外部源引入。这提供了当被蚀刻时材料层的所有部分基本上均匀地供应钝化剂，而不是依赖于在蚀刻期间消除光致抗蚀剂的钝化剂的产生，这可以产生钝化剂可用性的局部不均匀性由于在不同尺寸的特征上残留的光刻胶厚度的差异。

8. 发明授权

US06913958B1 Method for patterning a feature using a trimmed hardmask 失效
标题翻译：使用修剪后的硬掩模图案化特征的方法
公开(公告)号：US06913958B1
公开(公告)日：2005-07-05
申请号：US10366800
申请日：2003-02-14
申请人： Marina V. Plat , Marilyn I. Wright , Chih Yuh Yang , Douglas J. Bonser
发明人： Marina V. Plat , Marilyn I. Wright , Chih Yuh Yang , Douglas J. Bonser
IPC分类号： H01L21/033 , H01L21/28 , H01L21/311 , H01L21/3213 , H01L21/336 , H01L21/302 , H01L21/3205 , H01L21/84
CPC分类号： H01L21/0332 , H01L21/0337 , H01L21/28123 , H01L21/31116 , H01L21/31138 , H01L21/32139
摘要： In the formation of a semiconductor device, one or more hardmasks are formed during a process for patterning a device feature. One or more of the hardmasks is subjected to an isotropic etch to trim the hardmask prior to patterning an underlying layer. The trimmed hardmask layer is preferably an amorphous carbon layer.
摘要翻译：在形成半导体器件时，在用于图案化器件特征的工艺期间形成一个或多个硬掩模。对一个或多个硬掩模进行各向同性蚀刻，以在图案化底层之前对硬掩模进行修整。修整的硬掩模层优选为无定形碳层。

9. 发明授权

US06893967B1 L-shaped spacer incorporating or patterned using amorphous carbon or CVD organic materials 有权
标题翻译：使用无定形碳或CVD有机材料结合或图案化的L形间隔物
公开(公告)号：US06893967B1
公开(公告)日：2005-05-17
申请号：US10755911
申请日：2004-01-13
申请人： Marilyn I. Wright , Douglas J. Bonser , Lu You , Kay Hellig
发明人： Marilyn I. Wright , Douglas J. Bonser , Lu You , Kay Hellig
IPC分类号： H01L29/72
CPC分类号： H01L29/6656
摘要： A multilayer L-shaped spacer is formed of a lower portion comprising a CVD organic material or amorphous carbon, and an upper portion comprised of a protective material. The upper portion is patterned using a photoresist mask. During that patterning, the underlying substrate is protected by a layer of CVD organic material or amorphous carbon. The CVD organic material or amorphous carbon is then patterned using the patterned protective material as a mask. The chemistry used to pattern the CVD organic material or amorphous carbon is relatively harmless to the underlying substrate. Alternatively, an L-shaped spacer is patterned without using a photoresist mask by forming an amorphous carbon spacer around a gate that is covered with a conformal layer of a conventional spacer material. The conventional spacer material is patterned using the amorphous carbon spacer as an etch mask. The amorphous carbon spacer is easily formed without the need for lithographic patterning, and therefore this method is preferable to methods using photoresist masks.
摘要翻译：多层L型间隔件由包含CVD有机材料或无定形碳的下部和由保护材料构成的上部形成。使用光致抗蚀剂掩模对上部进行图案化。在该图案化期间，下面的衬底被CVD有机材料层或无定形碳保护。然后使用图案化的保护材料作为掩模对CVD有机材料或无定形碳进行图案化。用于对CVD有机材料或无定形碳进行图案化学的化学物质对于底层基材相对无害。或者，通过在被常规间隔物材料的共形层覆盖的栅极周围形成无定形碳隔离物，将L形间隔物图案化而不使用光致抗蚀剂掩模。使用无定形碳间隔物作为蚀刻掩模来对传统的间隔物材料进行图案化。非晶碳隔离物容易地形成而不需要平版印刷图案，因此该方法优于使用光致抗蚀剂掩模的方法。

10. 发明授权

US06900139B1 Method for photoresist trim endpoint detection 失效
标题翻译：光刻胶修饰端点检测方法
公开(公告)号：US06900139B1
公开(公告)日：2005-05-31
申请号：US10135175
申请日：2002-04-30
申请人： Srikanteswara Dakshina-Murthy , Douglas J. Bonser , Karen Turnquest
发明人： Srikanteswara Dakshina-Murthy , Douglas J. Bonser , Karen Turnquest
IPC分类号： H01L21/311 , H01L21/3213 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/31138 , H01L21/32139 , H01L21/76838
摘要： A method for forming semiconductor features, e.g., gates, line widths, thicknesses and spaces, produced by a photoresist trim procedure, in a closed loop process is presented. The methodology enables the use of optical emission spectroscopy and/or optical interferometry techniques for endpoint monitoring during resist trim etching of photoresist structures. Various types of material layers underlying photoresist structures are employed in order to provide an endpoint signal to enable closed loop control, with resultant improved targeting of photoresist mask and reproducibility. In addition, the method provides for in situ etch rate monitoring, and is not adversely affected by etch rate variances within an etching chamber during an etch process.
摘要翻译：提出了一种用于在闭环过程中形成由光致抗蚀剂修整过程产生的半导体特征（例如栅极，线宽，厚度和空间）的方法。该方法使得能够在抗蚀剂修饰蚀刻光致抗蚀剂结构期间使用光发射光谱学和/或光学干涉测量技术来进行端点监测。采用各种类型的光致抗蚀剂结构下面的材料层，以提供端点信号以实现闭环控制，从而改善光致抗蚀剂掩模的靶向性和再现性。此外，该方法提供了原位蚀刻速率监测，并且不会在蚀刻工艺期间蚀刻室内的蚀刻速率变化受到不利影响。

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