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1. 发明授权

US06420752B1 Semiconductor device with self-aligned contacts using a liner oxide layer 有权
标题翻译：具有使用衬垫氧化物层的自对准触点的半导体器件
公开(公告)号：US06420752B1
公开(公告)日：2002-07-16
申请号：US09502163
申请日：2000-02-11
申请人： Minh Van Ngo , Yu Sun , Fei Wang , Mark T. Ramsbey , Chi Chang , Angela T. Hui , Mark S. Chang
发明人： Minh Van Ngo , Yu Sun , Fei Wang , Mark T. Ramsbey , Chi Chang , Angela T. Hui , Mark S. Chang
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L21/76829 , H01L21/76897 , H01L27/115 , H01L2924/3011
摘要： A semiconductor device for minimizing auto-doping problems is disclosed. An etch stop layer is eliminated and is replaced with a consumable liner oxide layer so that stacked gate structures of the device can be positioned closer together, thus permitting shrinking of the device. The liner oxide layer is formed directly over a substrate and in contact with stacked gate structures, sidewall spacers, and sources and drains formed on the substrate, and serves as an auto-doping barrier for the dielectric layer to prevent boron and phosphorous formed in the dielectric layer from auto-doping into the sources and drains.
摘要翻译：公开了一种用于最小化自动掺杂问题的半导体器件。蚀刻停止层被消除并且被可消耗的衬垫氧化物层代替，使得该器件的层叠栅极结构可以被更靠近地放置在一起，从而允许器件收缩。衬垫氧化物层直接形成在衬底上并且与堆叠的栅极结构，侧壁间隔物以及形成在衬底上的源极和漏极接触并且用作介电层的自动掺杂势垒，以防止形成在衬底中的硼和磷电介质层自动掺入源和漏极。

2. 发明授权

US06475847B1 Method for forming a semiconductor device with self-aligned contacts using a liner oxide layer 有权
标题翻译：使用衬垫氧化物层形成具有自对准触点的半导体器件的方法
公开(公告)号：US06475847B1
公开(公告)日：2002-11-05
申请号：US10109526
申请日：2002-03-27
申请人： Minh Van Ngo , Yu Sun , Fei Wang , Mark T. Ramsbey , Chi Chang , Angela T. Hui , Mark S. Chang
发明人： Minh Van Ngo , Yu Sun , Fei Wang , Mark T. Ramsbey , Chi Chang , Angela T. Hui , Mark S. Chang
IPC分类号： H01L218238
CPC分类号： H01L27/11521 , H01L21/76829 , H01L21/76897 , H01L27/115 , H01L2924/3011
摘要： A method for shrinking a semiconductor device and minimizing auto-doping problem is disclosed. An etch stop layer is eliminated and is replaced with a consumable liner oxide layer so that stacked gate structures of the device can be positioned closer together, thus permitting shrinking of the device. The liner oxide layer is formed directly over a substrate and in contact with stacked gate structures, sidewall spacers, and sources and drains formed on the substrate, and serves as an auto-doping barrier for the dielectric layer to prevent boron and phosphorous formed in the dielectric layer from auto-doping into the sources and drains.
摘要翻译：公开了一种缩小半导体器件并最小化自动掺杂问题的方法。蚀刻停止层被消除并且被可消耗的衬垫氧化物层代替，使得该器件的层叠栅极结构可以被更靠近地放置在一起，从而允许器件收缩。衬垫氧化物层直接形成在衬底上并与堆叠的栅极结构，侧壁间隔物以及形成在衬底上的源极和漏极接触，并且用作电介质层的自动掺杂势垒，以防止形成在衬底中的硼和磷电介质层自动掺入源和漏极。

3. 发明授权

US06455373B1 Semiconductor device having gate edges protected from charge gain/loss 有权
标题翻译：具有防止电荷增益/损耗的栅极边缘的半导体器件
公开(公告)号：US06455373B1
公开(公告)日：2002-09-24
申请号：US09834419
申请日：2001-04-12
申请人： Tuan D. Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui , Yu Sun , Chi Chang
发明人： Tuan D. Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui , Yu Sun , Chi Chang
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L21/823468 , H01L27/105 , H01L27/11536
摘要： A plurality of core gate stacks and periphery gates on the substrate, each core gate stack and periphery gate having at least one side and first and second protective shoulders formed on said plurality of core gate stacks and periphery gates, such that a dopant can be implanted sequentially into source and drain regions of a substrate supporting the stacks to establish transistors and such that charge migration into said at least one side of the gate stacks during interlayer dielectric (ILD) formation and device metallization is prevented, at least the second shoulder being frabricated from at least one material selected from a group consisting essentially of nitride and silicon oxynitride (SiON).
摘要翻译：在基板上的多个核心栅极叠层和周边栅极，每个芯栅极叠层和周边栅极具有形成在所述多个芯栅极叠层和外围栅极上的至少一个侧面和第一和第二保护肩部，使得掺杂剂可被植入顺序地进入支撑堆叠的衬底的源极和漏极区域以建立晶体管，并且防止在层间电介质（ILD）形成和器件金属化期间电荷迁移到栅极叠层的所述至少一个侧面，至少第二肩部被破坏选自由氮化物和氮氧化硅（SiON）组成的组中的至少一种材料。

4. 发明授权

US06248627B1 Method for protecting gate edges from charge gain/loss in semiconductor device 有权
标题翻译：在半导体器件中保护栅极边缘免受电荷增益/损耗的方法
公开(公告)号：US06248627B1
公开(公告)日：2001-06-19
申请号：US09376658
申请日：1999-08-18
申请人： Tuan D. Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui , Yu Sun , Chi Chang
发明人： Tuan D. Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui , Yu Sun , Chi Chang
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L21/823468 , H01L27/105 , H01L27/11536
摘要： A method for making a ULSI MOSFET includes covering core gate stacks with a first protective layer, etching away the first layer such that intended source regions of the substrate are exposed, and implanting dopant into the source regions. A second protective layer is then deposited over the first layer and is etched back to conform to the first layer, covering only the sides of the gate stacks, and exposing intended drain regions of the substrate. Dopant is then implanted into the drain regions. During subsequent manufacturing steps including ILD formation and metallization, mobile ions and other process-induced charges are blocked from entering the floating gates of the gate stacks by the protective layers, thereby preventing unwanted charge gain/loss.
摘要翻译：制造ULSI MOSFET的方法包括用第一保护层覆盖芯栅极叠层，蚀刻掉第一层，使得衬底的预期源极区域暴露，并将掺杂剂注入到源极区域中。然后在第一层上沉积第二保护层，并将其回蚀刻以符合第一层，仅覆盖栅极堆叠的侧面，并暴露衬底的预期漏极区域。然后将掺杂剂注入漏区。在包括ILD形成和金属化的后续制造步骤期间，阻止移动离子和其它工艺感应电荷被保护层进入栅极堆叠的浮置栅极，从而防止不必要的电荷增益/损耗。

5. 发明授权

US06808996B1 Method for protecting gate edges from charge gain/loss in semiconductor device 有权
标题翻译：在半导体器件中保护栅极边缘免受电荷增益/损耗的方法
公开(公告)号：US06808996B1
公开(公告)日：2004-10-26
申请号：US09376659
申请日：1999-08-18
申请人： Tuan D. Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui , Yu Sun , Chi Chang
发明人： Tuan D. Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui , Yu Sun , Chi Chang
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method for making a ULSI MOSFET includes covering core gate stacks with a first protective layer, etching away the first layer such that intended source regions of the substrate are exposed, and implanting dopant into the source regions. A second protective layer is then deposited over the first layer and is etched back to conform to the first layer, covering only the sides of the gate stacks, and exposing intended drain regions of the substrate. Dopant is then implanted into the drain regions. During subsequent manufacturing steps including ILD formation and metallization, mobile ions and other process-induced charges are blocked from entering the floating gates of the gate stacks by the protective layers, thereby preventing unwanted charge gain/loss.
摘要翻译：制造ULSI MOSFET的方法包括用第一保护层覆盖芯栅极叠层，蚀刻掉第一层，使得衬底的预期源极区域暴露，并将掺杂剂注入到源极区域中。然后在第一层上沉积第二保护层，并将其回蚀刻以符合第一层，仅覆盖栅极堆叠的侧面，并暴露衬底的预期漏极区域。然后将掺杂剂注入漏区。在包括ILD形成和金属化的后续制造步骤期间，阻止移动离子和其它工艺感应电荷被保护层进入栅极堆叠的浮置栅极，从而防止不必要的电荷增益/损耗。

6. 发明授权

US06730564B1 Salicided gate for virtual ground arrays 有权
标题翻译：用于虚拟地面阵列的闸门
公开(公告)号：US06730564B1
公开(公告)日：2004-05-04
申请号：US10217821
申请日：2002-08-12
申请人： Mark T. Ramsbey , Yu Sun , Chi Chang , Hidehiko Shiraiwa
发明人： Mark T. Ramsbey , Yu Sun , Chi Chang , Hidehiko Shiraiwa
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11534 , Y10S438/954
摘要： The present invention provides a process for saliciding word lines in a virtual ground array flash memory device without causing shorting between bit lines. According to one aspect of the invention, saliciding takes place prior to patterning one or more layers of a memory cell stack. The unpatterned layers protect the substrate between word lines from becoming salicided. The invention provides virtual ground array flash memory devices with doped and salicided word lines, but no shorting between bit lines, even in virtual ground arrays where there are no oxide island isolation regions between word lines. Potential advantages of such structures include reduced size, reduced number of processing steps, and reduced exposure to high temperature cycling.
摘要翻译：本发明提供了一种在虚拟接地阵列闪存器件中对字线进行水印处理，而不引起位线之间的短路。根据本发明的一个方面，在对存储单元堆叠的一层或多层进行构图之前进行水化。未图案化的层保护字线之间的基板不会变成水银。本发明提供具有掺杂和含水字线的虚拟接地阵列闪存器件，但是即使在字线之间没有氧化物岛隔离区域的虚拟接地阵列中也不会在位线之间发生短路。这种结构的潜在优点包括减小的尺寸，减少的加工步骤数量以及降低暴露于高温循环。

7. 发明授权

US6160317A Method of spacer formation and source protection after self-aligned source formed and a device provided by such a method 有权
标题翻译：自对准源形成后的间隔物形成和源保护方法以及通过这种方法提供的器件
公开(公告)号：US6160317A
公开(公告)日：2000-12-12
申请号：US336057
申请日：1999-06-18
申请人： Yu Sun , Chi Chang , Mark T. Ramsbey
发明人： Yu Sun , Chi Chang , Mark T. Ramsbey
IPC分类号： H01L21/8247 , H01L27/105 , H01L27/088
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11536
摘要： The present invention provides a semiconductor device and a method for providing such a semiconductor device which allows a field oxide etch while minimizing the damage to the silicon. This method is particularly useful for smaller semiconductor devices, for example, such as a semiconductor device utilizing core source spacing less than 0.4 microns. A method according to the present invention for providing a semiconductor device comprises the steps of depositing a first spacer oxide layer over a core area and a peripheral area of a semiconductor device; etching the first spacer oxide layer at the source side of core cell area; depositing a second spacer oxide layer over the core area and the peripheral area, and etching the first and second spacer oxide layers over the peripheral area only.
摘要翻译：本发明提供了一种用于提供这种半导体器件的半导体器件和方法，其允许场氧化物蚀刻同时最小化对硅的损害。该方法对于较小的半导体器件特别有用，例如，诸如利用芯源间距小于0.4微米的半导体器件。根据本发明的用于提供半导体器件的方法包括以下步骤：在半导体器件的芯区域和周边区域上沉积第一间隔氧化物层; 在核心区域的源极处蚀刻第一间隔氧化物层; 在芯区域和外围区域上沉积第二间隔氧化物层，并且仅在周边区域上蚀刻第一和第二间隔氧化物层。

8. 发明授权

US06787840B1 Nitridated tunnel oxide barriers for flash memory technology circuitry 失效
标题翻译：用于闪存技术电路的氮化隧道氧化物屏障
公开(公告)号：US06787840B1
公开(公告)日：2004-09-07
申请号：US09492931
申请日：2000-01-27
申请人： Tuan Duc Pham , Mark T. Ramsbey , Yu Sun , Chi Chang
发明人： Tuan Duc Pham , Mark T. Ramsbey , Yu Sun , Chi Chang
IPC分类号： H01L27108
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546
摘要： A semiconductor chip having a plurality of flash memory devices, shallow trench isolation in the periphery region, and LOCOS isolation in the core region. A hard mask is used first to create the shallow trench isolation. The LOCOS isolation is then created. Subsequent etching is used to remove stringers. The flash memory is able to use shallow trench isolation to limit encroachment. The flash memory may also have a nitridated tunnel oxide barrier layer. A hard mask is used to prevent nitride contamination of the gate oxide layer. Periphery stacks have hate oxide layers of different thicknesses.
摘要翻译：具有多个闪存器件的半导体芯片，周边区域中的浅沟槽隔离以及芯区域中的LOCOS隔离。首先使用硬掩模来创建浅沟槽隔离。然后创建LOCOS隔离。随后的蚀刻用于去除桁条。闪存能够使用浅沟槽隔离来限制侵占。闪存也可以具有氮化的隧道氧化物阻挡层。使用硬掩模来防止栅极氧化物层的氮化物污染。外围堆叠具有不同厚度的恶性氧化物层。

9. 发明授权

US06605511B2 Method of forming nitridated tunnel oxide barriers for flash memory technology circuitry and STI and LOCOS isolation 失效
标题翻译：形成用于闪存技术电路的氮化隧道氧化物屏障的方法和STI和LOCOS隔离
公开(公告)号：US06605511B2
公开(公告)日：2003-08-12
申请号：US10295738
申请日：2002-11-15
申请人： Tuan Duc Pham , Mark T. Ramsbey , Yu Sun , Chi Chang
发明人： Tuan Duc Pham , Mark T. Ramsbey , Yu Sun , Chi Chang
IPC分类号： H01L218234
CPC分类号： H01L21/76202 , H01L21/76224 , H01L27/1052 , Y10S438/981
摘要： A method of fabricating an improved flash memory device, having shallow trench isolation in the periphery region and LOCOS isolation in the core region is provided, by first creating the shallow trench isolation using a hard mask; then creating the LOCOS isolation; and subsequently etching to remove stringers. The flash memory is able to use shallow trench isolation to limit encroachment. The flash memory may also have a nitridated tunnel oxide layer. A hard mask is used to prevent nitride contamination of the gate oxide layer.
摘要翻译：提供了一种通过首先使用硬掩模创建浅沟槽隔离来制造在外围区域中具有浅沟槽隔离和芯区域中的LOCOS隔离的改进的闪速存储器件的方法; 然后创建LOCOS隔离; 并随后蚀刻以除去桁条。闪存能够使用浅沟槽隔离来限制侵占。闪存也可以具有氮化隧道氧化物层。使用硬掩模来防止栅极氧化物层的氮化物污染。

10. 发明授权

US06284600B1 Species implantation for minimizing interface defect density in flash memory devices 有权
标题翻译：用于最小化闪存器件中的界面缺陷密度的物种植入
公开(公告)号：US06284600B1
公开(公告)日：2001-09-04
申请号：US09609468
申请日：2000-07-03
申请人： Yider Wu , Mark T. Ramsbey , Chi Chang , Yu Sun , Tuan Duc Pham , Jean Y. Yang
发明人： Yider Wu , Mark T. Ramsbey , Chi Chang , Yu Sun , Tuan Duc Pham , Jean Y. Yang
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/115
摘要： A predetermined species such as nitrogen is placed at an interface between a bit line junction and a dielectric layer of a control dielectric structure of a flash memory device to minimize degradation of such an interface by minimizing formation of interface defects during program or erase operations of the flash memory device. The predetermined species such as nitrogen is implanted into a bit line junction of the flash memory device. A thermal process is performed that heats up the semiconductor wafer such that the predetermined species such as nitrogen implanted within the semiconductor wafer thermally drifts to the interface between the bit line junction and the control dielectric structure during the thermal process. The predetermined species such as nitrogen at the interface minimizes formation of interface defects and thus degradation of the interface with time during the program or erase operations of the flash memory device.
摘要翻译：将诸如氮的预定物质放置在闪存存储器件的控制电介质结构的位线结和电介质层之间的界面处，以通过在编程或擦除操作期间最小化界面缺陷的形成来最小化这种界面的劣化闪存设备。将诸如氮的预定物质注入到闪速存储器件的位线结中。执行加热半导体晶片的热处理，使得在热处理期间注入到半导体晶片内的预定物质例如氮漂移到位线结与控制电介质结构之间的界面。在闪存器件的编程或擦除操作期间，预定种类例如接口处的氮使界面缺陷的形成最小化，从而使界面的时效性降低。

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