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1. 发明授权

US06764949B2 Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication 有权
公开(公告)号：US06764949B2
公开(公告)日：2004-07-20
申请号：US10334392
申请日：2002-12-30
申请人： Douglas J. Bonser , Marina V. Plat , Chih Yuh Yang , Scott A. Bell , Darin Chan , Philip A. Fisher , Christopher F. Lyons , Mark S. Chang , Pei-Yuan Gao , Marilyn I. Wright , Lu You , Srikanteswara Dakshina-Murthy
发明人： Douglas J. Bonser , Marina V. Plat , Chih Yuh Yang , Scott A. Bell , Darin Chan , Philip A. Fisher , Christopher F. Lyons , Mark S. Chang , Pei-Yuan Gao , Marilyn I. Wright , Lu You , Srikanteswara Dakshina-Murthy
IPC分类号： H01L2144
CPC分类号： H01L21/32139 , H01L21/0332
摘要： A hardmask stack is comprised of alternating layers of doped amorphous carbon and undoped amorphous carbon. The undoped amorphous carbon layers serve as buffer layers that constrain the effects of compressive stress within the doped amorphous carbon layers to prevent delamination. The stack is provided with a top capping layer. The layer beneath the capping layer is preferably undoped amorphous carbon to reduce photoresist poisoning. An alternative hardmask stack is comprised of alternating layers of capping material and amorphous carbon. The amorphous carbon layers may be doped or undoped. The capping material layers serve as buffer layers that constrain the effects of compressive stress within the amorphous carbon layers to prevent delamination. The top layer of the stack is formed of a capping material. The layer beneath the top layer is preferably undoped amorphous carbon to reduce photoresist poisoning. The lowest layer of the hardmask stack is preferably amorphous carbon to facilitate easy removal of the hardmask stack from underlying materials by an ashing process.

2. 发明授权

US06653735B1 CVD silicon carbide layer as a BARC and hard mask for gate patterning 有权
标题翻译： CVD碳化硅层作为BARC和用于栅极图案化的硬掩模
公开(公告)号：US06653735B1
公开(公告)日：2003-11-25
申请号：US10209447
申请日：2002-07-30
申请人： Chih Yuh Yang , Douglas Bonser , Pei-Yuan Gao , Lu You
发明人： Chih Yuh Yang , Douglas Bonser , Pei-Yuan Gao , Lu You
IPC分类号： H01L2348
CPC分类号： H01L21/0276 , H01L21/0332 , H01L21/32139
摘要： A BARC comprising materials having a lower pinhole density than that of silicon oxynitride and materials having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of polysilicon than that of amorphous carbon is employed to reduce deformation of a pattern to be formed in a patternable layer. The patternable layer is formed over a substrate. A multi-layered anti-reflective coating is formed over the patternable layer. A photoresist pattern is formed on the coating. The coating may comprise an amorphous carbon layer formed over the patternable layer and a SiC layer having a lower pinhole density than the pinhole density of SiON formed over the amorphous carbon layer. The coating may also be formed over a polysilicon layer and comprise a thermal expansion buffer layer having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of polysilicon than that of amorphous carbon.
摘要翻译：使用包含具有比氮氧化硅更小的针孔密度的材料的BARC和具有比非晶碳更接近于多晶硅热膨胀系数的热膨胀系数的材料来减少将形成的图案的变形可图案层。可图案层形成在衬底上。在可图案层上形成多层抗反射涂层。在涂层上形成光致抗蚀剂图案。涂层可以包括在可图案层上形成的无定形碳层和具有比在无定形碳层上形成的SiON的针孔密度小的针孔密度的SiC层。涂层也可以形成在多晶硅层上，并且包括热膨胀缓冲层，其热膨胀系数比无定形碳的热膨胀系数更接近于多晶硅的热膨胀系数。

3. 发明授权

US06803313B2 Method for forming a hardmask employing multiple independently formed layers of a pecvd material to reduce pinholes 有权
标题翻译：用于形成采用多个独立形成的pecvd材料层以减少针孔的硬掩模的方法
公开(公告)号：US06803313B2
公开(公告)日：2004-10-12
申请号：US10256368
申请日：2002-09-27
申请人： Pei-Yuan Gao , Lu You , Richard J. Huang
发明人： Pei-Yuan Gao , Lu You , Richard J. Huang
IPC分类号： H01L2144
CPC分类号： H01L21/0332 , H01L21/32139 , H01L2924/0002 , H01L2924/00
摘要： A bi-layer BARC/hardmask structure includes a layer of amorphous carbon and two or more distinct and independently formed layers of a PECVD material such as SiON formed on the amorphous carbon layer. By independently forming several layers of PECVD material, at least some pinholes that are present in the lowermost PECVD layer are closed by upper PECVD layers and therefore do not extend through all of the PECVD layers. As a result the upper surface of the uppermost PECVD layer has a lower pinhole density than the lower PECVD layer. This reduces photoresist poisoning by dopant in the amorphous carbon layer, and etching of the amorphous carbon layer by photoresist stripping chemistry.
摘要翻译：双层BARC /硬掩模结构包括非晶碳层和形成在无定形碳层上的诸如SiON的PECVD材料的两个或更多个不同且独立形成的层。通过独立地形成多层PECVD材料，存在于最低PECVD层中的至少一些针孔由上PECVD层封闭，因此不延伸穿过所有PECVD层。结果，最上面的PECVD层的上表面具有比下PECVD层更低的针孔密度。这减少了无定形碳层中的掺杂剂的光致抗蚀剂中毒，以及通过光刻胶剥离化学法蚀刻无定形碳层。

4. 发明申请

US20090176369A1 LOW-H PLASMA TREATMENT WITH N2 ANNEAL FOR ELECTRONIC MEMORY DEVICES 有权
标题翻译：用于电子存储器件的N2天线的低等离子体处理
公开(公告)号：US20090176369A1
公开(公告)日：2009-07-09
申请号：US11971331
申请日：2008-01-09
申请人： Alexander H. Nickel , Allen L. Evans , Minh Quoc Tran , Lu You , Minh Van Ngo , Pei-Yuan Gao , William S. Brennan , Eric Wilson , Sung Jin Kim , Hieu Trung Pham
发明人： Alexander H. Nickel , Allen L. Evans , Minh Quoc Tran , Lu You , Minh Van Ngo , Pei-Yuan Gao , William S. Brennan , Eric Wilson , Sung Jin Kim , Hieu Trung Pham
IPC分类号： H01L21/44
CPC分类号： H01L21/76877 , H01L21/76814 , H01L21/76828 , H01L21/76834 , H01L21/76883 , Y10S438/902
摘要： A method for forming a single damascene and/or dual damascene, contact and interconnect structure, comprising: performing front end processing, depositing copper including a copper barrier, annealing the copper in at least 90% N2 with less than 10% H2, performing planarization, performing in-situ low-H NH3 plasma treatment and low Si—H SiN etch stop layer deposition, and performing remaining back end processing.
摘要翻译：一种用于形成单个镶嵌和/或双镶嵌，接触和互连结构的方法，包括：执行前端处理，沉积包含铜屏障的铜，在至少90％的N 2中以小于10％的H 2退火铜，进行平面化，进行原位低H NH 3等离子体处理和低Si-H SiN蚀刻停止层沉积，并执行剩余的后端处理。

5. 发明授权

US08202810B2 Low-H plasma treatment with N2 anneal for electronic memory devices 有权
标题翻译：用于电子存储器件的N 2退火的低-H等离子体处理
公开(公告)号：US08202810B2
公开(公告)日：2012-06-19
申请号：US11971331
申请日：2008-01-09
申请人： Alexander H. Nickel , Allen L. Evans , Minh Quoc Tran , Lu You , Minh Van Ngo , Pei-Yuan Gao , William S. Brennan , Erik Wilson , Sung Jin Kim , Hieu Trung Pham
发明人： Alexander H. Nickel , Allen L. Evans , Minh Quoc Tran , Lu You , Minh Van Ngo , Pei-Yuan Gao , William S. Brennan , Erik Wilson , Sung Jin Kim , Hieu Trung Pham
IPC分类号： H01L21/31
CPC分类号： H01L21/76877 , H01L21/76814 , H01L21/76828 , H01L21/76834 , H01L21/76883 , Y10S438/902
摘要： A method for forming a single damascene and/or dual damascene, contact and interconnect structure, comprising: performing front end processing, depositing copper including a copper barrier, annealing the copper in at least 90% N2 with less than 10% H2, performing planarization, performing in-situ low-H NH3 plasma treatment and low Si—H SiN etch stop layer deposition, and performing remaining back end processing.
摘要翻译：一种用于形成单个镶嵌和/或双镶嵌，接触和互连结构的方法，包括：执行前端处理，沉积包含铜屏障的铜，在至少90％的N 2中以小于10％的H 2退火铜，进行平面化，进行原位低H NH 3等离子体处理和低Si-H SiN蚀刻停止层沉积，并执行剩余的后端处理。

6. 发明授权

US07183198B2 Method for forming a hardmask employing multiple independently formed layers of a capping material to reduce pinholes 有权
标题翻译：用于形成使用多个独立形成的封盖材料层以减少针孔的硬掩模的方法
公开(公告)号：US07183198B2
公开(公告)日：2007-02-27
申请号：US10962907
申请日：2004-10-12
申请人： Pei-Yuan Gao , Lu You , Richard J. Huang
发明人： Pei-Yuan Gao , Lu You , Richard J. Huang
IPC分类号： H01L21/4763
CPC分类号： H01L21/0332 , H01L21/32139 , H01L2924/0002 , H01L2924/00
摘要： A bi-layer BARC/hardmask structure includes a layer of amorphous carbon and two or more distinct and independently formed layers of a PECVD material such as SiON formed on the amorphous carbon layer. By independently forming several layers of PECVD material, at least some pinholes that are present in the lowermost PECVD layer are closed by upper PECVD layers and therefore do not extend through all of the PECVD layers. As a result the upper surface of the uppermost PECVD layer has a lower pinhole density than the lower PECVD layer. This reduces photoresist poisoning by dopant in the amorphous carbon layer, and etching of the amorphous carbon layer by photoresist stripping chemistry.
摘要翻译：双层BARC /硬掩模结构包括非晶碳层和形成在无定形碳层上的诸如SiON的PECVD材料的两个或更多个不同且独立形成的层。通过独立地形成多层PECVD材料，存在于最低PECVD层中的至少一些针孔由上PECVD层封闭，因此不延伸穿过所有PECVD层。结果，最上面的PECVD层的上表面具有比下PECVD层更低的针孔密度。这减少了无定形碳层中的掺杂剂的光致抗蚀剂中毒，以及通过光刻胶剥离化学法蚀刻无定形碳层。

7. 发明授权

US07033960B1 Multi-chamber deposition of silicon oxynitride film for patterning 失效
标题翻译：用于图案化的氮氧化硅膜的多室沉积
公开(公告)号：US07033960B1
公开(公告)日：2006-04-25
申请号：US10918378
申请日：2004-08-16
申请人： Lu You , Richard Huang , Pei-Yuan Gao
发明人： Lu You , Richard Huang , Pei-Yuan Gao
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/32139 , C23C16/345 , H01L21/0332 , H01L21/3145 , H01L21/3146 , Y10S438/95
摘要： Pinholes in a silicon oxynitride film are reduced by PECVD deposition of a plurality of silicon oxynitride sub-layers in a PECVD apparatus containing multiple chambers. Embodiments include forming a layer of amorphous carbon over a conductive layer, such as doped polycrystalline silicon, on a substrate, transferring the substrate to a multi-chamber PECVD tool and depositing 2 to 7, e.g., 5, sub-layers of dense silicon oxynitride at a total thickness of 300 to 700 Å.
摘要翻译：氧氮化硅膜中的针孔通过在包含多个室的PECVD装置中的多个氮氧化硅子层的PECVD沉积而减少。实施例包括在衬底上的导电层（例如掺杂多晶硅）上形成无定形碳层，将衬底转移到多室PECVD工具，并沉积2至7个例如5个致密氮氧化硅的子层总厚度为300至700埃。

8. 发明申请

US20050048771A1 Hardmask employing multiple layers of silicon oxynitride 有权
标题翻译：使用多层氮氧化硅的硬掩模
公开(公告)号：US20050048771A1
公开(公告)日：2005-03-03
申请号：US10962907
申请日：2004-10-12
申请人： Pei-Yuan Gao , Lu You , Richard Huang
发明人： Pei-Yuan Gao , Lu You , Richard Huang
IPC分类号： H01L21/033 , H01L21/3213 , H01L21/44 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/0332 , H01L21/32139 , H01L2924/0002 , H01L2924/00
摘要： A bi-layer BARC/hardmask structure includes a layer of amorphous carbon and two or more distinct and independently formed layers of a PECVD material such as SiON formed on the amorphous carbon layer. By independently forming several layers of PECVD material, at least some pinholes that are present in the lowermost PECVD layer are closed by upper PECVD layers and therefore do not extend through all of the PECVD layers. As a result the upper surface of the uppermost PECVD layer has a lower pinhole density than the lower PECVD layer. This reduces photoresist poisoning by dopant in the amorphous carbon layer, and etching of the amorphous carbon layer by photoresist stripping chemistry.
摘要翻译：双层BARC /硬掩模结构包括非晶碳层和形成在无定形碳层上的诸如SiON的PECVD材料的两个或更多个不同且独立形成的层。通过独立地形成多层PECVD材料，存在于最低PECVD层中的至少一些针孔由上PECVD层封闭，因此不延伸穿过所有PECVD层。结果，最上面的PECVD层的上表面具有比下PECVD层更低的针孔密度。这减少了无定形碳层中的掺杂剂的光致抗蚀剂中毒，以及通过光刻胶剥离化学法蚀刻无定形碳层。

9. 发明授权

US06627973B1 Void-free interlayer dielectric (ILD0) for 0.18-micron flash memory semiconductor device 有权
标题翻译：用于0.18微米闪存半导体器件的无空隙层间电介质（ILD0）
公开(公告)号：US06627973B1
公开(公告)日：2003-09-30
申请号：US10244129
申请日：2002-09-13
申请人： Minh Van Ngo , Robert A. Huertas , Lu You , King Wai Kelwin Ko , Pei-Yuan Gao
发明人： Minh Van Ngo , Robert A. Huertas , Lu You , King Wai Kelwin Ko , Pei-Yuan Gao
IPC分类号： H01L29167
CPC分类号： H01L21/02271 , C23C16/401 , H01L21/02129 , H01L21/022 , H01L21/31625 , H01L21/76801
摘要： A method of eliminating voids in the interlayer dielectric material of 0.18-&mgr;m flash memory semiconductor devices and a semiconductor device formed by the method. The present invention provides a method for eliminating voids in the interlayer dielectric of a 0.18-&mgr;m flash memory semiconductor device by providing a first BPTEOS layer, using a very low deposition rate and having a thickness in a range of approximately 3 kÅ; and providing a second BPTEOS layer, using a standard deposition rate and having a thickness in a range of approximately 13 kÅ, wherein both layers have an atomic dopant concentration of approximately 4.5% B and approximately 5% P. This two-step deposition process completely eliminates voids in the ILD for a 0.5-&mgr;m distance (gate-to-gate) as well as 0.38-&mgr;m distance (gate-to-gate) which is the future flash technology. A low dopant/TEOS flow performed at a higher pressure during the deposition of the first layer provides an excellent gap-filling capability which eliminates voiding. Further, the present invention has the advantage of in-situ deposition of the void-free ILD0 layer of the 0.18-&mgr;m flash memory semiconductor device having a sound dopant concentration.
摘要翻译：一种消除0.18微米闪速存储器半导体器件的层间电介质材料中的空隙的方法和通过该方法形成的半导体器件。本发明提供一种通过使用非常低的沉积速率并且具有在约3k范围内的厚度的第一BPTEOS层来消除0.18微米快闪存储器半导体器件的层间电介质中的空隙的方法; 并提供第二BPTEOS层，使用标准沉积速率并且具有在约13k范围内的厚度，其中两层的原子掺杂剂浓度为约4.5％B和约5％P。这两步沉积过程完全消除了0.5-mum距离（栅极到栅极）的ILD中的空隙以及将来闪存技术的0.38μm距离（栅极到栅极）。在第一层沉积期间在较高压力下执行的低掺杂剂/ TEOS流提供了优异的间隙填充能力，其消除了排尿。此外，本发明的优点是具有声掺杂剂浓度的0.18μm的闪存半导体器件的无空隙的ILD0层的原位沉积。

10. 发明授权

US06489253B1 Method of forming a void-free interlayer dielectric (ILD0) for 0.18-&mgr;m flash memory technology and semiconductor device thereby formed 失效
标题翻译：由此形成用于0.18微米快闪存储器技术的无空隙层间电介质（ILD0）和由此形成的半导体器件的方法
公开(公告)号：US06489253B1
公开(公告)日：2002-12-03
申请号：US09788045
申请日：2001-02-16
申请人： Minh Van Ngo , Robert A. Huertas , Lu You , King Wai Kelwin Ko , Pei-Yuan Gao
发明人： Minh Van Ngo , Robert A. Huertas , Lu You , King Wai Kelwin Ko , Pei-Yuan Gao
IPC分类号： H01L21469
CPC分类号： H01L21/02271 , C23C16/401 , H01L21/02129 , H01L21/022 , H01L21/31625 , H01L21/76801
摘要： A method of eliminating voids in the interlayer dielectric material of 0.18-&mgr;m flash memory semiconductor devices and a semiconductor device formed by the method. The present invention provides a method for eliminating voids in the interlayer dielectric of a 0.18-&mgr;m flash memory semiconductor device by providing a first BPTEOS layer, using a very low deposition rate and having a thickness in a range of approximately 3 kÅ; and providing a second BPTEOS layer, using a standard deposition rate and having a thickness in a range of approximately 13 kÅ, wherein both layers have an atomic dopant concentration of approximately 4.5% B and approximately 5% P. This two-step deposition process completely eliminates voids in the ILD for a 0.5-&mgr;m distance (gate-to-gate) as well as 0.38-&mgr;m distance (gate-to-gate) which is the future flash technology. A low dopant/TEOS flow performed at a higher pressure during the deposition of the first layer provides an excellent gap-filling capability which eliminates voiding. Further, the present invention has the advantage of in-situ deposition of the void-free ILD0 layer of the 0.18-&mgr;m flash memory semiconductor device having a sound dopant concentration.
摘要翻译：一种消除0.18微米闪速存储器半导体器件的层间电介质材料中的空隙的方法和通过该方法形成的半导体器件。本发明提供一种通过使用非常低的沉积速率并且具有在约3k范围内的厚度的第一BPTEOS层来消除0.18微米快闪存储器半导体器件的层间电介质中的空隙的方法; 并提供第二BPTEOS层，使用标准沉积速率并且具有在约13k范围内的厚度，其中两层的原子掺杂剂浓度为约4.5％B和约5％P。这两步沉积过程完全消除了0.5-mum距离（栅极到栅极）的ILD中的空隙以及将来闪存技术的0.38μm距离（栅极到栅极）。在第一层沉积期间在较高压力下执行的低掺杂剂/ TEOS流提供了优异的间隙填充能力，其消除了排尿。此外，本发明的优点是具有声掺杂剂浓度的0.18μm的闪存半导体器件的无空隙的ILD0层的原位沉积。

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