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41. 发明授权

US06706630B1 Method for forming an alloyed metal conductive element of an integrated circuit 有权
标题翻译：用于形成集成电路的合金化金属导电元件的方法
公开(公告)号：US06706630B1
公开(公告)日：2004-03-16
申请号：US10376399
申请日：2003-02-28
申请人： Amit P. Marathe
发明人： Amit P. Marathe
IPC分类号： H01L2144
CPC分类号： H01L21/76886 , H01L21/02074 , H01L21/3212 , H01L21/76838
摘要： The introduction of alloying elements into a metal conductive element is achieved in situ in conjunction with a post-CMP reducing treatment. The source of the alloying elements may be a source gas introduced into the plasma chamber, or a source material incorporated into a post-CMP residue through presence in a CMP slurry or a post-CMP rinsing agent, or applied to the substrate prior to plasma treatment. The alloying element is introduced into the metal conductive element by diffusion during plasma treatment.
摘要翻译：将金属导电元件引入到原位与CMP后还原处理相结合。合金元素的来源可以是引入到等离子体室中的源气体，或通过存在于CMP浆料或后CMP漂洗剂中而掺入后CMP残留物的源材料，或者在等离子体之前施加到基板上治疗。在等离子体处理期间，通过扩散将合金元素引入金属导电元件。

42. 发明授权

US06599835B1 Testing dielectric and barrier layers for integrated circuit interconnects 失效
标题翻译：测试用于集成电路互连的电介质层和阻挡层
公开(公告)号：US06599835B1
公开(公告)日：2003-07-29
申请号：US09905470
申请日：2001-07-13
申请人： Amit P. Marathe , Christy Mei-Chu Woo
发明人： Amit P. Marathe , Christy Mei-Chu Woo
IPC分类号： H01L2144
CPC分类号： G01R31/2853 , G01R31/129 , G01R31/2831
摘要： An integrated circuit test system and method therefor is provided having a semiconductor substrate with an electrical ground and a source of electrical potential. A dielectric layer with first and second openings is formed on the semiconductor substrate. First and second barrier layers are deposited on the dielectric layer to line the openings. A first conductor core is deposited over the first barrier layer to fill the first opening and is connected to a source of electrical potential. A second conductor core is deposited over the second barrier layer to fill the second opening and is connected to the electrical ground. A current measuring device is provided to measure leakage current flow between the first and second conductor cores.
摘要翻译：提供了具有具有电接地和电势源的半导体衬底的集成电路测试系统及其方法。在半导体衬底上形成具有第一和第二开口的电介质层。第一和第二阻挡层沉积在电介质层上以对开口进行排列。第一导体芯沉积在第一阻挡层上以填充第一开口并连接到电势源。第二导体芯沉积在第二阻挡层上以填充第二开口并且连接到电接地。提供电流测量装置以测量第一和第二导体芯之间的漏电流。

43. 发明授权

US06599827B1 Methods of forming capped copper interconnects with improved electromigration resistance 有权
标题翻译：形成具有改善的电迁移阻力的封盖铜互连的方法
公开(公告)号：US06599827B1
公开(公告)日：2003-07-29
申请号：US09846273
申请日：2001-05-02
申请人： Minh Van Ngo , Steven C. Avanzino , Amit P. Marathe , Hartmut Ruelke
发明人： Minh Van Ngo , Steven C. Avanzino , Amit P. Marathe , Hartmut Ruelke
IPC分类号： H01L214763
CPC分类号： H01L21/76834 , H01L21/76883
摘要： The electromigration resistance of capped Cu or Cu alloy interconnects is significantly improved by pumping out the deposition chamber after treating the exposed planarized surface of the Cu or Cu alloy with an ammonia-containing plasma, introducing NH3 and N2 into the deposition chamber, and then ramping up the introduction of SiH4 prior to initiating deposition of a silicon nitride capping layer. Embodiments include ramping up the introduction of SiH4 in two stages prior to initiating plasma enhanced chemical vapor deposition of the silicon nitride capping layer.
摘要翻译：通过在用含氨的等离子体处理暴露的Cu或Cu合金的平坦化表面之后，通过泵出沉积室来显着改善封盖的Cu或Cu合金互连的电迁移电阻，将NH 3和N 2引入沉积室，然后斜坡在开始沉积氮化硅覆盖层之前引入SiH4。实施例包括在引发氮化硅覆盖层的等离子体增强化学气相沉积之前分两阶段引入SiH4。

44. 发明授权

US06498397B1 Seed layer with annealed region for integrated circuit interconnects 有权
标题翻译：具有用于集成电路互连的退火区域的种子层
公开(公告)号：US06498397B1
公开(公告)日：2002-12-24
申请号：US09848979
申请日：2001-05-04
申请人： Krishnashree Achuthan , Amit P. Marathe
发明人： Krishnashree Achuthan , Amit P. Marathe
IPC分类号： H01L2348
CPC分类号： H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L2924/0002 , Y10S438/927 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. An barrier layer lines the opening and a seed layer is deposited to line the barrier layer. A conductor core fills the opening over the barrier layer to form a conductor channel. The seed layer is annealed to form an annealed region, which securely bonds the seed layer to the barrier layer and prevents electromigration along the surface between the seed and barrier layers.
摘要翻译：提供了具有半导体器件的半导体衬底的集成电路及其制造方法。电介质层位于半导体衬底上，其中设有开口。阻挡层对开口进行排列，并且沉积种子层以使阻挡层成线。导体芯填充阻挡层上的开口以形成导体通道。种子层被退火以形成退火区域，其将种子层牢固地结合到阻挡层并防止沿种子和阻挡层之间的表面的电迁移。

45. 发明授权

US06462417B1 Coherent alloy diffusion barrier for integrated circuit interconnects 有权
标题翻译：用于集成电路互连的相干合金扩散屏障
公开(公告)号：US06462417B1
公开(公告)日：2002-10-08
申请号：US09772750
申请日：2001-01-29
申请人： Pin-Chin Connie Wang , Amit P. Marathe , Minh Van Ngo , Suzette K. Pangrle
发明人： Pin-Chin Connie Wang , Amit P. Marathe , Minh Van Ngo , Suzette K. Pangrle
IPC分类号： H01L2348
CPC分类号： H01L21/76844 , H01L21/76843 , H01L21/76846 , H01L21/76855 , H01L21/76858 , H01L21/76873 , H01L21/76886 , H01L23/53209 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device and a device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has a channel opening, an alloy-barrier layer lining the channel opening, and a conductor core filling the channel opening. An alloy layer is deposited which contains an element capable of reacting during thermal treatment with both the conductor core and the channel dielectric layer to form an alloy-barrier to diffusion of the material of the conductor core to the channel dielectric layer. The alloy-barrier layer is reacted with the conductor core and the channel dielectric layer to form a compound which provides a bond which blocks surface diffusion and permits conductor core to conductor core diffusion in dual inlaid integrated circuits.
摘要翻译：提供了一种集成电路及其制造方法，其具有半导体衬底，半导体器件和形成在半导体衬底上的器件电介质层。器件电介质层上的沟道电介质层具有通道开口，衬在沟道开口的合金阻挡层和填充沟道开口的导体芯。沉积合金层，其包含能够在热处理期间与导体芯和沟道介电层两者反应的元件，以形成对导体芯的材料扩散到沟道介电层的合金阻挡层。合金阻挡层与导体芯和沟道电介质层反应形成一种化合物，其提供阻挡表面扩散的键，并允许导体芯在双重嵌入式集成电路中的芯体扩散。

46. 发明授权

US06445070B1 Coherent carbide diffusion barrier for integrated circuit interconnects 有权
标题翻译：用于集成电路互连的相干碳化物扩散屏障
公开(公告)号：US06445070B1
公开(公告)日：2002-09-03
申请号：US09772715
申请日：2001-01-29
申请人： Pin-Chin Connie Wang , Amit P. Marathe , Minh Van Ngo , Suzette K. Prangrle
发明人： Pin-Chin Connie Wang , Amit P. Marathe , Minh Van Ngo , Suzette K. Prangrle
IPC分类号： H01L2348
CPC分类号： H01L23/53223 , H01L23/5226 , H01L23/53238 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefore is provided having a semiconductor substrate with a semiconductor device and a device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has a channel opening, a barrier layer lining the channel opening, and a conductor core filling the channel opening. A barrier layer is deposited which contains an element capable of reacting during thermal treatment with both the conductor core and the channel dielectric layer to form a barrier to diffusion of the material of the conductor core to the channel dielectric layer. The barrier layer reacts with the conductor core and the channel dielectric layer to form a compound which provides a bond which blocks surface diffusion and permits conductor core to conductor core diffusion in dual inlaid integrated circuits.
摘要翻译：因此，提供了具有半导体器件的半导体衬底和形成在半导体衬底上的器件电介质层的集成电路和制造方法。器件电介质层上的沟道电介质层具有通道开口，衬在通道开口的阻挡层和填充通道开口的导体芯。沉积阻挡层，其包含能够在热处理期间与导体芯和沟道介电层两者反应的元件，以形成导体芯材料扩散到沟道介电层的障碍。阻挡层与导体芯和沟道介电层反应形成一种化合物，其提供阻挡表面扩散的键，并允许导体芯与双重镶嵌集成电路中的导体芯扩散。

47. 发明授权

US06426293B1 Minimizing resistance and electromigration of interconnect by adjusting anneal temperature and amount of seed layer dopant 失效
标题翻译：通过调整退火温度和种子层掺杂剂的量来最小化互连的电阻和电迁移
公开(公告)号：US06426293B1
公开(公告)日：2002-07-30
申请号：US09872717
申请日：2001-06-01
申请人： Pin-Chin C. Wang , Sergey Lopatin , Amit P. Marathe
发明人： Pin-Chin C. Wang , Sergey Lopatin , Amit P. Marathe
IPC分类号： H01L2144
CPC分类号： H01L21/76864 , H01L21/76843 , H01L21/76873 , H01L21/76874 , H01L21/76877 , H01L2221/1089
摘要： A plurality of test interconnect structures are formed with each test interconnect structure having a respective alloy seed layer and with a fill conductive material formed to fill the respective interconnect opening. The respective alloy seed layer of each of the test interconnect structures has a respective thickness and a respective concentration of an alloy dopant within a bulk conductive material. A respective thermal anneal process is performed at a respective thermal anneal temperature for each of the plurality of test interconnect structures. A respective resistance and a respective rate of electromigration failure is measured for each of the plurality of test interconnect structures. For forming an IC interconnect structure within an IC interconnect opening, an alloy seed layer is deposited onto sidewalls and a bottom wall of the IC interconnect opening, and the IC interconnect opening is filled by growing a fill conductive material from the alloy seed layer within the IC interconnect opening. A thermal anneal process is performed at a thermal anneal temperature. A desired thickness of the alloy seed layer, a desired concentration of the alloy dopant, and a desired thermal anneal temperature for the IC interconnect structure are adjusted depending on the respective thickness of the alloy seed layer, the respective concentration of the alloy dopant, and the respective thermal anneal temperature of one of the plurality of test interconnect structures having the respective resistance that is closest to a desired resistance and/or having a respective measured rate of electromigration failure that is closest to a desired rate of electromigration failure for the IC interconnect structure.
摘要翻译：形成多个测试互连结构，每个测试互连结构具有相应的合金种子层，并且形成有填充导电材料以填充相应的互连开口。每个测试互连结构的相应的合金种子层具有相应的厚度和相应的体积导电材料内的合金掺杂剂的浓度。对于多个测试互连结构中的每一个，在相应的热退火温度下执行相应的热退火工艺。针对多个测试互连结构中的每一个测量相应的电阻和相应的电迁移失败率。为了在IC互连开口内形成IC互连结构，将合金晶种层沉积在IC互连开口的侧壁和底壁上，并且通过从合金种子层内生长填充导电材料来填充IC互连开口 IC互连开口。热退火工艺在热退火温度下进行。根据合金种子层的各自的厚度，合金掺杂剂的相应浓度以及合金种子层的相应浓度，合金种子层的期望厚度，合金掺杂剂的期望浓度和IC互连结构的期望的热退火温度多个测试互连结构中的一个测试互连结构的相应热退火温度具有最接近期望电阻的相应电阻和/或具有最接近IC互连的期望的电迁移失败率的相应测量的电迁移失败率结构体。

48. 发明授权

US06348701B1 Method for determining metal concentration in a field area 失效
标题翻译：确定场区金属浓度的方法
公开(公告)号：US06348701B1
公开(公告)日：2002-02-19
申请号：US09421455
申请日：1999-10-19
申请人： Young-Chang Joo , Amit P. Marathe
发明人： Young-Chang Joo , Amit P. Marathe
IPC分类号： H01L2358
CPC分类号： H01L22/14 , H01L2924/0002 , H01L2924/00
摘要： The concentration of metal atoms in a field area between two trench structures is determined by applying a voltage on one of the trench structures and grounding the other. The resultant current flow between the trench structures is measured and used as an indicator of metal concentration in the field area.
摘要翻译：两个沟槽结构之间的场区域中的金属原子的浓度通过在一个沟槽结构上施加电压并将另一个接地而确定。测量沟槽结构之间的所得电流，并将其用作场区域中的金属浓度的指标。

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