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1. 发明申请

US20110018565A1 DIELECTRIC BREAKDOWN LIFETIME ENHANCEMENT USING ALTERNATING CURRENT (AC) CAPACITANCE 有权
标题翻译：使用替代电流（AC）电容进行电介质断路寿命延长
公开(公告)号：US20110018565A1
公开(公告)日：2011-01-27
申请号：US12506837
申请日：2009-07-21
申请人： Kok Yong Yiang , Rick Francis , Amit P. Marathe , Van-Hung Pham
发明人： Kok Yong Yiang , Rick Francis , Amit P. Marathe , Van-Hung Pham
IPC分类号： G01R31/02 , G01R31/26 , G01R31/20
CPC分类号： G01R31/2623
摘要： A time-to-breakdown for a dielectric layer in a semiconductor device is determined based upon a sudden change in capacitance. An alternating voltage, greater in magnitude than an operating voltage of the device, is applied to the semiconductor device, capacitance is measured across the dielectric layer during the application of the voltage until a sudden change in capacitance occurs, thereby indicating a breakdown in the dielectric layer, and the breakdown time is scaled to the operating voltage.
摘要翻译：基于电容的突然变化来确定半导体器件中的电介质层的击穿时间。在半导体器件上施加大于该器件的工作电压的大小的交变电压，在施加电压期间在电介质层两端测量电容，直到发生电容的突然变化，从而表明电介质中的击穿层，并且击穿时间被缩放到工作电压。

2. 发明授权

US07379924B1 Quantifying and predicting the impact of line edge roughness on device reliability and performance 失效
标题翻译：量化和预测线边缘粗糙度对器件可靠性和性能的影响
公开(公告)号：US07379924B1
公开(公告)日：2008-05-27
申请号：US11001151
申请日：2004-12-01
申请人： Amit P. Marathe , Calvin T. Gabriel
发明人： Amit P. Marathe , Calvin T. Gabriel
IPC分类号： G06F15/18 , G05B13/00
CPC分类号： H01L22/20
摘要： Systems and methods are disclosed for testing semiconductors at the wafer level, specifically, systems and methods are disclosed that quantify line-edge roughness in terms of electrical properties and the impact of the line-edge roughness on device reliability and performance. A voltage ramp dielectric breakdown (VRDB) test is used to measure the breakdown voltage of the inter-digitated fingers of a semiconductor device. The distribution of breakdown voltage is used to measure the median breakdown voltage and the outliers which fan the extrinsic tail. Thereby, VRDB is used to quantify the impact LER will have on device reliability and performance. The systems and methods also provide a feedback tool to the fabrication process to control line edge roughness to a desired specification.
摘要翻译：公开了用于在晶片级测试半导体的系统和方法，具体地，公开了在电特性方面量化线边缘粗糙度以及线边缘粗糙度对器件可靠性和性能的影响的系统和方法。使用电压斜坡绝缘击穿（VRDB）测试来测量半导体器件的数字间指状物的击穿电压。击穿电压的分布用于测量中间击穿电压和外来尾部的异常值。因此，VRDB用于量化LER对器件可靠性和性能的影响。这些系统和方法还为制造过程提供反馈工具，以将线边缘粗糙度控制到期望的规格。

3. 发明授权

US07310155B1 Extraction of tool independent line-edge-roughness (LER) measurements using in-line programmed LER and reliability structures 失效
标题翻译：使用在线编程的LER和可靠性结构提取工具独立的线边粗糙度（LER）测量
公开(公告)号：US07310155B1
公开(公告)日：2007-12-18
申请号：US10958149
申请日：2004-10-04
申请人： Luigi Capodieci , Amit P. Marathe , Bhanwar Singh , Ramkumar Subramanian
发明人： Luigi Capodieci , Amit P. Marathe , Bhanwar Singh , Ramkumar Subramanian
IPC分类号： G01B11/04 , G01B11/14
CPC分类号： G01B11/303 , G01N21/47 , G01N21/9501
摘要： A system that facilitates extraction of line edge roughness measurements that are independent of proprietorship of a metrology device comprises a structure patterned onto silicon with known line edge roughness values associated therewith. A metrology device obtains line edge roughness measurements from the structure, and a correcting component generates an inverse function based upon a comparison between the known line edge roughness values and the measured line edge roughness values. The metrology device can thereafter measure line edge roughness upon a second structure patterned on the silicon, and the inverse function can be applied to such measured line edge roughness values to enable obtainment of line edge roughness measurements that are independent of proprietorship of the metrology device.
摘要翻译：有助于提取独立于计量装置所有权的线边缘粗糙度测量的系统包括利用与其相关联的已知线边缘粗糙度值图案化到硅上的结构。测量装置从该结构获得线边缘粗糙度测量，并且校正部件基于已知的线边缘粗糙度值与所测量的线边缘粗糙度值之间的比较产生反向函数。测量装置此后可以在硅上图案化的第二结构上测量线边缘粗糙度，并且可以将反函数应用于这种测量的线边缘粗糙度值，以使得能够获得独立于计量装置所有权的线边缘粗糙度测量。

4. 发明授权

US07146588B1 Predicting EM reliability by decoupling extrinsic and intrinsic sigma 失效
标题翻译：通过去除外在和内在的sigma来预测EM的可靠性
公开(公告)号：US07146588B1
公开(公告)日：2006-12-05
申请号：US10909438
申请日：2004-08-02
申请人： Amit P. Marathe , Darrell Erb
发明人： Amit P. Marathe , Darrell Erb
IPC分类号： G06F17/50 , G01R27/28
CPC分类号： G01R31/2858
摘要： Systems and methods are disclosed that facilitate predicting electromigration (EM) reliability in semiconductor wafers via decoupling intrinsic and extrinsic components of EM reliability. Electrical cross-sections of wafer test lines can be determined and individual currents can be forced through the test lines to force a constant current density across a test wafer. An EM reliability test can be performed to determine a purely intrinsic component of EM reliability. A single current can then be applied to all test lines and a second EM reliability test can be performed to determine total EM reliability. Standard deviations, or sigma, of failure distributions can be derived for each EM test. Intrinsic sigma can be subtracted from total sigma to yield an extrinsic sigma associated with process variation in wafer fabrication. Sigmas can then be utilized to predict EM reliability when process variations are adjusted, without application of a damaging package-level EM test.
摘要翻译：公开了通过解耦EM可靠性的内在和外在分量来促进预测半导体晶片中的电迁移（EM）可靠性的系统和方法。可以确定晶片测试线的电气横截面，并且可以通过测试线强制单独的电流，以迫使测试晶片上的恒定电流密度。可以进行EM可靠性测试，以确定EM可靠性的纯内在分量。然后可以将单个电流施加到所有测试线，并且可以执行第二EM可靠性测试以确定总EM可靠性。可以为每个EM测试导出故障分布的标准偏差或σ。可以从总西格玛中减去本征σ，以产生与晶片制造中的工艺变化相关的外在西格玛。然后，当调整过程变化时，可以利用Sigma来预测EM可靠性，而不应用损坏的封装级EM测试。

5. 发明授权

US07084062B1 Use of Ta-capped metal line to improve formation of memory element films 有权
标题翻译：使用钽盖金属线改善记忆元素膜的形成
公开(公告)号：US07084062B1
公开(公告)日：2006-08-01
申请号：US11033653
申请日：2005-01-12
申请人： Steven C. Avanzino , Amit P. Marathe
发明人： Steven C. Avanzino , Amit P. Marathe
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/76852 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/14 , H01L45/146 , H01L45/16
摘要： Disclosed are methods for deposition of improved memory element films for semiconductor devices. The methods involve providing a hard mask over an upper surface of a metal line of a semiconductor substrate where vias are to be placed, recess etching the mask substantially in all upper surfaces except where vias are to be placed, depositing a Ta-containing capping layer over substantially all the metal line surfaces except the surface where vias are to be placed, polishing the Ta-containing capping layer to produce a damascened Ta-containing cap while exposing the metal line at the via forming surface, depositing a dielectric layer, patterning the dielectric layer to form a via to expose a portion of the metal line, and depositing memory element films. The improved Ta—Cu interface of the subject invention mitigates and/or eliminates lateral growth of memory element films and copper voiding under the dielectric layer at the top surface of the metal line, and thereby enhances reliability and performance of semiconductor devices.
摘要翻译：公开了用于沉积用于半导体器件的改进的存储元件膜的方法。所述方法包括在要放置通孔的半导体衬底的金属线的上表面上提供硬掩模，基本上在除了要放置通孔之外的所有上表面中蚀刻掩模，沉积含Ta的覆盖层在除了要放置通孔的表面之外的基本上所有的金属线表面上，抛光含Ta的封盖层，以在露出金属线在通孔形成表面的同时产生一个镶嵌的含Ta盖，沉积介电层，电介质层以形成通孔以暴露金属线的一部分，以及沉积存储元件膜。本发明的改进的Ta-Cu界面缓和了和/或消除了金属线顶表面下的介质层下存储元件膜的横向生长和铜空隙化，从而提高了半导体器件的可靠性和性能。

6. 发明授权

US06939803B2 Method for forming conductor reservoir volume for integrated circuit interconnects 有权
标题翻译：用于形成集成电路互连的导体储存器容积的方法
公开(公告)号：US06939803B2
公开(公告)日：2005-09-06
申请号：US10225656
申请日：2002-08-21
申请人： Amit P. Marathe , Pin-Chin Connie Wang , Christy Mei-Chu Woo
发明人： Amit P. Marathe , Pin-Chin Connie Wang , Christy Mei-Chu Woo
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/44
CPC分类号： H01L21/76844 , H01L21/76838 , H01L21/76873 , H01L21/76874 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A first dielectric layer on the device dielectric layer has an opening formed therein including a conductor reservoir volume. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. A second dielectric layer is formed on the first dielectric layer and has a second channel and via opening provided therein. A barrier layer lines the second channel and via opening except over the first channel opening. A conductor core fills the second channel and via opening over the barrier layer and the first conductor core to form the second channel and via. The conductor reservoir volume provides a supply of conductor material to prevent the formation of voids in the first channel and in the via.
摘要翻译：提供了具有半导体器件的半导体衬底的集成电路及其制造方法。在半导体衬底上形成器件电介质层。器件介电层上的第一介电层具有形成在其中的开口，其中包括导体储存器体积。屏障层对通道开口进行排列。导体芯填充阻挡层上的开口。第二电介质层形成在第一电介质层上并具有设置在其中的第二通道和通孔。除了第一通道开口之外，阻挡层沿着第二通道和通孔开口。导体芯填充第二通道并通过阻挡层和第一导体芯上的开口形成第二通道和通孔。导体储存器容积提供导体材料供应，以防止在第一通道和通孔中形成空隙。

7. 发明授权

US06858511B1 Method of semiconductor via testing 失效
标题翻译：半导体通过测试方法
公开(公告)号：US06858511B1
公开(公告)日：2005-02-22
申请号：US10256805
申请日：2002-09-26
申请人： Amit P. Marathe
发明人： Amit P. Marathe
IPC分类号： H01L21/66 , H01L21/331 , H01L21/76
CPC分类号： H01L22/14 , Y10S257/92
摘要： A semiconductor wafer having a via test structure is provided which includes a semiconductor substrate having a plurality of semiconductor devices. A dielectric layer deposited over the semiconductor substrate has second and fourth channels unconnected to the plurality of semiconductor devices. A via dielectric layer deposited over the channel dielectric layer has first and second vias and third and fourth vias respectively open to opposite ends of the second channel and the fourth channel. A second dielectric layer over the via dielectric layer has first, third, and fifth channels respectively connected to the first via, the second and third vias, and the fourth via. The first channel, the first via, the second channel, the second via, the third channel, the third via, the fourth channel, the fourth via, and the fifth channel are connected in series and the first and fifth channel are probed to determine the presence or absence of voids in the vias.
摘要翻译：提供具有通孔测试结构的半导体晶片，其包括具有多个半导体器件的半导体衬底。沉积在半导体衬底上的电介质层具有未连接到多个半导体器件的第二和第四通道。沉积在沟道电介质层上的通孔电介质层具有分别向第二通道和第四通道的相对端开口的第一和第二通孔和第三和第四通孔。通孔电介质层上的第二介电层具有分别连接到第一通孔，第二和第三通孔以及第四通孔的第一，第三和第五通道。第一通道，第一通道，第二通道，第二通孔，第三通道，第三通孔，第四通道，第四通孔和第五通道串联连接，第一通道和第五通道被探测以确定通孔中存在或不存在空隙。

8. 发明授权

US06710452B1 Coherent diffusion barriers for integrated circuit interconnects 有权
标题翻译：用于集成电路互连的相干扩散屏障
公开(公告)号：US06710452B1
公开(公告)日：2004-03-23
申请号：US09618964
申请日：2000-07-19
申请人： Pin-Chin Connie Wang , Matthew S. Buynoski , Suzette K. Pangrle , Amit P. Marathe
发明人： Pin-Chin Connie Wang , Matthew S. Buynoski , Suzette K. Pangrle , Amit P. Marathe
IPC分类号： H01L2348
CPC分类号： H01L21/76843 , H01L21/76844 , H01L21/76855 , H01L21/76864 , H01L21/76873 , H01L21/76886 , H01L21/76888 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device and a device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has a channel opening, a barrier layer lining the channel opening, and a conductor core filling the channel opening. The barrier layer has a more negative heat of formation than the channel dielectric layer whereby the barrier layer is reacts with and forms a barrier to diffusion of the material of the conductor core to the channel dielectric layer. The barrier layer also forms a stable compound with the conductor core to form a coherent barrier layer bonding the channel dielectric to the conductor core.
摘要翻译：提供了一种集成电路及其制造方法，其具有半导体衬底，半导体器件和形成在半导体衬底上的器件电介质层。器件电介质层上的沟道电介质层具有通道开口，衬在通道开口的阻挡层和填充通道开口的导体芯。阻挡层具有比通道介电层更加负的形成热量，由此阻挡层与导体芯的材料扩散到沟道介电层上形成阻挡层。阻挡层还与导体芯形成稳定的化合物，以形成将沟道电介质结合到导体芯的相干势垒层。

9. 发明授权

US06621290B1 Characterization of barrier layers in integrated circuit interconnects 失效
标题翻译：集成电路互连中势垒层的表征
公开(公告)号：US06621290B1
公开(公告)日：2003-09-16
申请号：US09905283
申请日：2001-07-13
申请人： Amit P. Marathe , Pin-Chin Connie Wang
发明人： Amit P. Marathe , Pin-Chin Connie Wang
IPC分类号： G01R3126
CPC分类号： H01L22/14 , H01L2924/0002 , H01L2924/00
摘要： A test structure and method for testing a semiconductor material is provided with a semiconductor wafer having an electrical ground and a source of electrical potential. A conductor layer is placed over the semiconductor wafer and a semiconductor material is placed over the conductor layer. A dielectric layer is placed over the semiconductor material. Conductive top and bottom layers are placed over the dielectric layer and the bottom of the semiconductor wafer. The conductive top layer is connected to the electrical ground. The conductive bottom layer is connected to the source of electrical potential. The current flow is measured from the conductive bottom layer to the conductive top layer.
摘要翻译：用于测试半导体材料的测试结构和方法设置有具有电接地和电势源的半导体晶片。导体层放置在半导体晶片上方，半导体材料放置在导体层上。介电层放置在半导体材料上。导电顶层和底层放置在电介质层和半导体晶片的底部之上。导电顶层连接到电气接地。导电底层连接到电位源。从导电底层到导电顶层测量电流。

10. 发明授权

US06472757B2 Conductor reservoir volume for integrated circuit interconnects 有权
公开(公告)号：US06472757B2
公开(公告)日：2002-10-29
申请号：US09758994
申请日：2001-01-11
申请人： Amit P. Marathe , Pin-Chin Connie Wang , Christy Mei-Chu Woo
发明人： Amit P. Marathe , Pin-Chin Connie Wang , Christy Mei-Chu Woo
IPC分类号： H01L23528
CPC分类号： H01L21/76844 , H01L21/76838 , H01L21/76873 , H01L21/76874 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A first dielectric layer on the device dielectric layer has an opening formed therein including a conductor reservoir volume. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. A second dielectric layer is formed on the first dielectric layer and has a second channel and via opening provided therein. A barrier layer lines the second channel and via opening except over the first channel opening. A conductor core fills the second channel and via opening over the barrier layer and the first conductor core to form the second channel and via. The conductor reservoir volume provides a supply of conductor material to prevent the formation of voids in the first channel and in the via.

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