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1. 发明授权

US06426293B1 Minimizing resistance and electromigration of interconnect by adjusting anneal temperature and amount of seed layer dopant 失效
标题翻译：通过调整退火温度和种子层掺杂剂的量来最小化互连的电阻和电迁移
公开(公告)号：US06426293B1
公开(公告)日：2002-07-30
申请号：US09872717
申请日：2001-06-01
申请人： Pin-Chin C. Wang , Sergey Lopatin , Amit P. Marathe
发明人： Pin-Chin C. Wang , Sergey Lopatin , Amit P. Marathe
IPC分类号： H01L2144
CPC分类号： H01L21/76864 , H01L21/76843 , H01L21/76873 , H01L21/76874 , H01L21/76877 , H01L2221/1089
摘要： A plurality of test interconnect structures are formed with each test interconnect structure having a respective alloy seed layer and with a fill conductive material formed to fill the respective interconnect opening. The respective alloy seed layer of each of the test interconnect structures has a respective thickness and a respective concentration of an alloy dopant within a bulk conductive material. A respective thermal anneal process is performed at a respective thermal anneal temperature for each of the plurality of test interconnect structures. A respective resistance and a respective rate of electromigration failure is measured for each of the plurality of test interconnect structures. For forming an IC interconnect structure within an IC interconnect opening, an alloy seed layer is deposited onto sidewalls and a bottom wall of the IC interconnect opening, and the IC interconnect opening is filled by growing a fill conductive material from the alloy seed layer within the IC interconnect opening. A thermal anneal process is performed at a thermal anneal temperature. A desired thickness of the alloy seed layer, a desired concentration of the alloy dopant, and a desired thermal anneal temperature for the IC interconnect structure are adjusted depending on the respective thickness of the alloy seed layer, the respective concentration of the alloy dopant, and the respective thermal anneal temperature of one of the plurality of test interconnect structures having the respective resistance that is closest to a desired resistance and/or having a respective measured rate of electromigration failure that is closest to a desired rate of electromigration failure for the IC interconnect structure.
摘要翻译：形成多个测试互连结构，每个测试互连结构具有相应的合金种子层，并且形成有填充导电材料以填充相应的互连开口。每个测试互连结构的相应的合金种子层具有相应的厚度和相应的体积导电材料内的合金掺杂剂的浓度。对于多个测试互连结构中的每一个，在相应的热退火温度下执行相应的热退火工艺。针对多个测试互连结构中的每一个测量相应的电阻和相应的电迁移失败率。为了在IC互连开口内形成IC互连结构，将合金晶种层沉积在IC互连开口的侧壁和底壁上，并且通过从合金种子层内生长填充导电材料来填充IC互连开口 IC互连开口。热退火工艺在热退火温度下进行。根据合金种子层的各自的厚度，合金掺杂剂的相应浓度以及合金种子层的相应浓度，合金种子层的期望厚度，合金掺杂剂的期望浓度和IC互连结构的期望的热退火温度多个测试互连结构中的一个测试互连结构的相应热退火温度具有最接近期望电阻的相应电阻和/或具有最接近IC互连的期望的电迁移失败率的相应测量的电迁移失败率结构体。

2. 发明授权

US06528412B1 Depositing an adhesion skin layer and a conformal seed layer to fill an interconnect opening 有权
标题翻译：沉积粘合表皮层和保形种子层以填充互连开口
公开(公告)号：US06528412B1
公开(公告)日：2003-03-04
申请号：US09844727
申请日：2001-04-30
申请人： Pin-Chin C. Wang , Sergey Lopatin
发明人： Pin-Chin C. Wang , Sergey Lopatin
IPC分类号： H01L214763
CPC分类号： H01L21/76843 , H01L21/76826 , H01L21/76831 , H01L21/76846 , H01L21/76862 , H01L21/76864 , H01L21/76868 , H01L23/53238 , H01L2924/0002 , Y10S977/712 , Y10S977/723 , Y10S977/81 , Y10S977/89 , H01L2924/00
摘要： For filling an interconnect opening within an insulating layer on a semiconductor wafer, an adhesion skin layer is deposited conformally onto an underlying material comprised of one of a barrier material or a dielectric material at sidewalls and a bottom wall of the interconnect opening. The adhesion skin layer includes a metal alloy doping element. A conformal seed layer is deposited onto the adhesion skin layer using a conformal deposition process, such as an ECD (electrochemical deposition) or a CVD (chemical-vapor-deposition) process. The adhesion skin layer promotes adhesion of the conformal seed layer to the underlying material at the sidewalls and the bottom wall of the interconnect opening. The interconnect opening is filled with a conductive material grown from the conformal seed layer. In this manner, the adhesion skin layer promotes adhesion of the conformal seed layer to the underlying material to minimize electromigration failure of the interconnect. In addition, the seed layer formed by conventional PVD (physical-vapor-deposition) processes is avoided with the present invention. Instead, the relatively thin adhesion skin layer and the relatively thin conformal seed layer are used for plating the conductive fill. With such relatively thin layers, an interconnect opening having a high aspect ratio is filled with minimized void formation.
摘要翻译：为了在半导体晶片上的绝缘层内填充互连开口，将粘合表皮层保形地沉积在由互连开口的侧壁和底壁处的阻挡材料或电介质材料之一构成的下层材料上。粘合性表皮层包括金属合金掺杂元素。使用诸如ECD（电化学沉积）或CVD（化学气相沉积）工艺的共形沉积工艺将保形种子层沉积到粘附表皮层上。附着表皮层促进保形种子层在互连开口的侧壁和底壁处的下层材料的附着。互连开口填充有从保形晶种层生长的导电材料。以这种方式，粘合表皮层促进保形种子层与底层材料的粘附，以最小化互连的电迁移失效。此外，通过本发明避免了通过常规PVD（物理 - 气相沉积）方法形成的晶种层。相反，使用相对薄的粘合表皮层和相对薄的保形晶种层来镀覆导电填料。利用这种相对薄的层，具有高纵横比的互连开口填充有最小化的空隙形成。

3. 发明授权

US06228759B1 Method of forming an alloy precipitate to surround interconnect to minimize electromigration 有权
标题翻译：形成合金沉淀物以围绕互连以最小化电迁移的方法
公开(公告)号：US06228759B1
公开(公告)日：2001-05-08
申请号：US09561622
申请日：2000-05-02
申请人： Pin-Chin C. Wang , Christy M. Woo , Sergey Lopatin
发明人： Pin-Chin C. Wang , Christy M. Woo , Sergey Lopatin
IPC分类号： H01L214763
CPC分类号： H01L21/76804 , H01L21/2855 , H01L21/76843 , H01L21/76849 , H01L21/76867 , H01L21/76873 , H01L21/76877 , H01L21/76886 , H01L2221/1089
摘要： An alloy precipitate is formed to surround a conductive fill within an interconnect opening, including especially a top surface of the conductive fill, to prevent drift of material from the conductive fill into the insulating layer that is surrounding the interconnect opening. An alloy material is deposited non-conformally such that the alloy material is deposited substantially only toward a top of the sidewalls of an interconnect opening and substantially only toward a center of the bottom wall of the interconnect opening. The interconnect opening is filled with the conductive material by growing the conductive material from a seed layer of the conductive material to form a conductive fill of the conductive material within the interconnect opening. The semiconductor wafer is heated to anneal the conductive fill within the interconnect opening such that the conductive fill forms into a substantially single grain structure. During the thermal anneal, reactant within the alloy material migrates along a top surface of the conductive fill and along a grain boundary of the conductive fill. An alloy precipitate is formed from a reaction between the reactant and the conductive material at the top surface and at the grain boundary of the conductive fill when the semiconductor wafer is then cooled down. The alloy precipitate at the top surface and at the grain boundary of the conductive fill prevents drift of the conductive material along the top surface and along the grain boundary of the conductive fill and into the insulating layer surrounding the interconnect opening.
摘要翻译：形成合金沉淀物以包围互连开口内的导电填料，特别包括导电填料的顶表面，以防止材料从导电填料漂移到围绕互连开口的绝缘层中。合金材料被非保形地沉积，使得合金材料基本上仅沉积在互连开口的侧壁的顶部并且基本上仅朝向互连开口的底壁的中心。通过从导电材料的种子层生长导电材料以在互连开口内形成导电材料的导电填充物，从而用导电材料填充互连开口。加热半导体晶片以使互连开口内的导电填充物退火，使得导电填料形成基本上单一的晶粒结构。在热退火期间，合金材料内的反应物沿着导电填料的顶表面沿导电填料的晶界迁移。当半导体晶片然后冷却时，在导电填料的顶表面和晶界处的反应物和导电材料之间的反应形成合金沉淀。在导电填料的顶表面和晶界处的合金沉淀物防止导电材料沿着顶表面和沿着导电填料的晶界并漂浮到围绕互连开口的绝缘层中。

4. 发明授权

US06447933B1 Formation of alloy material using alternating depositions of alloy doping element and bulk material 失效
公开(公告)号：US06447933B1
公开(公告)日：2002-09-10
申请号：US09845616
申请日：2001-04-30
申请人： Pin-Chin C. Wang , Sergey Lopatin
发明人： Pin-Chin C. Wang , Sergey Lopatin
IPC分类号： B32B1500
CPC分类号： H01L21/76846 , C23C26/00 , H01L21/28562 , H01L21/32051 , H01L21/76843 , H01L21/76858 , H01L21/76873 , H01L21/76886 , H01L2221/1089 , Y10T428/12632
摘要： An alloy material is formed on an underlying material, and the alloy material comprises an alloy doping element mixed into a bulk material. A first layer of material including the alloy doping element is deposited on the underlying material using a first type of deposition process. The first type of deposition process is corrosion resistive to the underlying material according to one aspect of the present invention. A second layer of material including the bulk material is deposited on the first layer of material using a second type of deposition process. A thermal anneal may be performed by heating the first layer of material and the second layer of material such that the alloy doping element is mixed into the bulk material to form the alloy material on the underlying material. The alloy doping element of the first layer of material deposited on the underlying material promotes adhesion of the alloy material to the underlying material. The present invention may be used to particular advantage when the underlying material is a diffusion barrier material deposited on sidewalls and a bottom wall of an interconnect opening, and when the alloy material is a copper alloy formed on the diffusion barrier material. In this manner, a plurality of deposition processes are used for forming a stack of layers of materials comprising the alloy material. The first type of deposition process for depositing the first layer of material on the underlying material is corrosion resistive to the underlying material. Corrosion to the underlying material is undesired because corrosion to the underlying material may degrade the adhesion of the interconnect to the underlying material to increase undesired electromigration failure of the interconnect. The second deposition process for depositing the second layer of material on the first layer of material may be a faster deposition process for depositing the bulk material of the alloy.

5. 发明授权

US06833625B1 Self-aligned barrier formed with an alloy having at least two dopant elements for minimized resistance of interconnect 有权
标题翻译：由具有至少两个掺杂元素的合金形成的自对准屏障，用于最小化互连电阻
公开(公告)号：US06833625B1
公开(公告)日：2004-12-21
申请号：US10690434
申请日：2003-10-21
申请人： Pin-Chin C. Wang , Fei Wang
发明人： Pin-Chin C. Wang , Fei Wang
IPC分类号： H01L2348
CPC分类号： H01L21/76846 , H01L21/76807 , H01L21/76828 , H01L21/76831 , H01L21/76838 , H01L21/76867 , H01L21/76877 , Y10S977/84
摘要： For fabricating an interconnect structure formed within an interconnect opening surrounded by dielectric material, the interconnect opening is filled with a conductive fill material comprised of a bulk conductive fill material doped with a first dopant element and a second dopant element that is different from the first dopant element. The dielectric material is comprised of a first dielectric reactant element and a second dielectric reactant element. A diffusion barrier material is formed from a reaction of the first dielectric reactant element and the first dopant element that diffuses from the conductive fill material to the walls to the interconnect opening. In addition, a boundary material is formed from a reaction of the second dielectric reactant element and the second dopant element that diffused from the conductive fill material to the walls of the interconnect opening. The diffusion barrier material and the boundary material form a self-aligned self-aligned skin layer on the walls of the interconnect opening between the conductive fill material and the dielectric material. The self-aligned skin layer prevents diffusion of the conductive fill material into the dielectric material, and the formation of the boundary material prevents diffusion of the second dielectric reactant element into the conductive fill material, such that resistance of the interconnect structure is minimized.
摘要翻译：为了制造形成在由电介质材料包围的互连开口内的互连结构，互连开口用由掺杂有第一掺杂剂元素的体导电填充材料和与第一掺杂剂不同的第二掺杂剂元素组成的导电填充材料填充元件。电介质材料包括第一介电反应物元件和第二介电反应元件。扩散阻挡材料由第一介电反应物元件和第一掺杂剂元素的反应形成，第一掺杂元素从导电填充材料扩散到壁到互连开口。此外，边界材料由第二介电反应物元件和从导电填充材料扩散到互连开口的壁的第二掺杂剂元素的反应形成。扩散阻挡材料和边界材料在导电填充材料和介电材料之间的互连开口的壁上形成自对准的自对准表皮层。自对准表皮层防止导电填充材料扩散到介电材料中，并且边界材料的形成防止第二电介质反应物元件扩散到导电填充材料中，使得互连结构的电阻最小化。

6. 发明授权

US06831003B1 Continuous barrier for interconnect structure formed in porous dielectric material with minimized electromigration 有权
标题翻译：在具有最小化电迁移的多孔电介质材料中形成的互连结构的连续屏障
公开(公告)号：US06831003B1
公开(公告)日：2004-12-14
申请号：US10161451
申请日：2002-05-31
申请人： Richard J. Huang , Pin-Chin C. Wang , Darrell M. Erb
发明人： Richard J. Huang , Pin-Chin C. Wang , Darrell M. Erb
IPC分类号： H01L214763
CPC分类号： H01L21/76843 , H01L21/76844 , H01L21/76865
摘要： For filling an interconnect opening within a porous dielectric material, a diffusion barrier material is deposited onto at least one sidewall of the interconnect opening. A thickness of the diffusion barrier material is equal to or greater than a radius of a pore opened at the sidewall to substantially fill the opened pore. The thickness of the diffusion barrier material is equal to or greater than a mean radius of pores opened at the sidewall to substantially fill a majority of the opened pores. Or, the thickness of the diffusion barrier material is equal to or greater than a radius of a largest pore opened at the sidewall to substantially fill all opened pores. The interconnect opening is then filled with a conductive fill material.
摘要翻译：为了填充多孔电介质材料内的互连开口，扩散阻挡材料沉积在互连开口的至少一个侧壁上。扩散阻挡材料的厚度等于或大于在侧壁开口的孔的半径，以基本上填充开孔。扩散阻挡材料的厚度等于或大于在侧壁处开口的孔的平均半径，以基本上填充大部分开孔。或者，扩散阻挡材料的厚度等于或大于在侧壁处开口的最大孔的半径，以基本上填充所有打开的孔。然后用导电填充材料填充互连开口。

7. 发明授权

US06358840B1 Forming and filling a recess in interconnect with alloy to minimize electromigration 有权
标题翻译：形成并填充与合金互连的凹槽以最小化电迁移
公开(公告)号：US06358840B1
公开(公告)日：2002-03-19
申请号：US09655699
申请日：2000-09-06
申请人： Pin-Chin C. Wang , Christy M. Woo
发明人： Pin-Chin C. Wang , Christy M. Woo
IPC分类号： H01L214763
CPC分类号： H01L21/76877 , H01L21/76886 , H01L21/76888 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： In a method for filling an interconnect opening to form an interconnect of an integrated circuit, the interconnect opening is formed within an insulating layer. The interconnect opening is partially filled with a conductive material to form a recess within the conductive material toward a top of the interconnect opening, and the recess is disposed within the interconnect opening. An alloy is conformally deposited to fill the recess. Any conductive material and the alloy on the insulating layer are polished away such that the conductive material and the alloy are contained within the interconnect opening. A thermal anneal is then performed such that the conductive material and the alloy form into a conductive fill of a single grain structure within the interconnect opening. An additional encapsulating material is formed to cover a top surface of the conductive fill during the thermal anneal from the dopant of the alloy diffusing out of the alloy and along the top surface of the conductive fill. A bulk encapsulating layer is formed on top of the additional encapsulating material and on top of the insulating layer. The present invention may be used to particular advantage when the conductive material that partially fills the interconnect opening is copper, and when the alloy that fills the recess is a copper alloy with a dopant metal having a solid solubility in copper that is less than 0.1 atomic percent at room temperature and having a concentration in the copper alloy that is greater than the solid solubility in the copper alloy. In this manner, the additional encapsulating material on the top surface of the conductive fill prevents lateral drift of the conductive material comprising the conductive fill along a bottom surface of the bulk encapsulating layer.
摘要翻译：在用于填充互连开口以形成集成电路的互连的方法中，互连开口形成在绝缘层内。互连开口部分地填充有导电材料，以在导电材料内朝向互连开口的顶部形成凹部，并且凹槽设置在互连开口内。保形地沉积合金以填充凹部。任何导电材料和绝缘层上的合金被抛光，使得导电材料和合金被包含在互连开口内。然后进行热退火，使得导电材料和合金形成在互连开口内的单个晶粒结构的导电填料中。形成另外的封装材料以在从合金扩散出合金的掺杂剂和导电填料的顶表面进行热退火期间覆盖导电填料的顶表面。在附加的封装材料的顶部和绝缘层的顶部上形成大量封装层。当部分填充互连开口的导电材料是铜时，并且当填充凹槽的合金是具有小于0.1原子的在铜中具有固溶度的掺杂剂金属的铜合金时，本发明可以被用于特别的优点在铜合金中的浓度大于在铜合金中的固溶度。以这种方式，导电填料的顶表面上的另外的封装材料防止包含导电填料的导电材料沿大块封装层的底表面的横向偏移。

8. 发明授权

US06664185B1 Self-aligned barrier formed with an alloy having at least two dopant elements for minimized resistance of interconnect 有权
标题翻译：由具有至少两个掺杂元素的合金形成的自对准屏障，用于最小化互连电阻
公开(公告)号：US06664185B1
公开(公告)日：2003-12-16
申请号：US10132235
申请日：2002-04-25
申请人： Pin-Chin C. Wang , Fei Wang
发明人： Pin-Chin C. Wang , Fei Wang
IPC分类号： H01L2144
CPC分类号： H01L21/76846 , H01L21/76807 , H01L21/76828 , H01L21/76831 , H01L21/76838 , H01L21/76867 , H01L21/76877 , Y10S977/84
摘要： For fabricating an interconnect structure within a dielectric material comprised of at least one dielectric reactant element, an interconnect opening formed within the dielectric material is filled with a conductive fill material comprised of first and second dopant elements that are different. A diffusion barrier material, that surrounds the conductive fill material, is formed from a reaction of the first dopant element and a dielectric reactant element. Also, a boundary material, that surrounds the conductive fill material, is formed from a reaction of the second dopant element and a dielectric reactant element. The boundary material prevents diffusion of a dielectric reactant element from the dielectric material into the conductive fill material.
摘要翻译：为了在由至少一个介电反应物元件构成的电介质材料内制造互连结构，在电介质材料内形成的互连开口用由不同的第一和第二掺杂元素构成的导电填充材料填充。围绕导电填充材料的扩散阻挡材料由第一掺杂剂元素和介电反应物元件的反应形成。此外，围绕导电填充材料的边界材料由第二掺杂剂元素和介电反应物元件的反应形成。边界材料防止介电反应物元件从电介质材料扩散到导电填充材料中。

9. 发明授权

US06573179B1 Forming a strong interface between interconnect and encapsulation to minimize electromigration 有权
标题翻译：在互连和封装之间形成强大的接口，以最小化电迁移
公开(公告)号：US06573179B1
公开(公告)日：2003-06-03
申请号：US09496223
申请日：2000-02-01
申请人： Pin-Chin C. Wang , Lu You
发明人： Pin-Chin C. Wang , Lu You
IPC分类号： H01L2144
CPC分类号： H01L21/76849 , H01L21/76856 , Y10S977/89
摘要： A strong interface is formed between an interconnect and an encapsulating layer to prevent the lateral drift of material from the interconnect along the bottom of the encapsulating layer. Diffusion barrier material is deposited on the top surface of the interconnect using a selective deposition process. The diffusion barrier material may be epitaxially grown from the interconnect during the selective deposition of the diffusion barrier material on the top surface of the interconnect to promote adhesion of the diffusion barrier material to the interconnect. An encapsulating layer is deposited on top of the diffusion barrier material. The diffusion barrier material and the encapsulating layer are comprised of a similar chemical element to promote adhesion of the diffusion barrier material to the encapsulating layer. The diffusion barrier material on the top surface of the interconnect prevents lateral drift of material comprising the interconnect along the encapsulating layer. When the layer of encapsulating dielectric is comprised of silicon nitride, a nitrided surface may be formed on top of the diffusion barrier material by exposing the top of the diffusion barrier material to nitrogen plasma before depositing the encapsulating layer of silicon nitride on top of the diffusion barrier material. The present invention may be used to particular advantage when the interconnect is a copper interconnect and when the layer of encapsulating layer is comprised of silicon nitride.
摘要翻译：在互连和封装层之间形成强的界面，以防止材料沿封装层的底部从互连件的横向漂移。使用选择性沉积工艺将扩散阻挡材料沉积在互连的顶表面上。在扩散阻挡材料选择性地沉积在互连的顶表面上时，扩散阻挡材料可以从互连外延生长，以促进扩散阻挡材料与互连的粘附。封装层沉积在扩散阻挡材料的顶部上。扩散阻挡材料和封装层由类似的化学元素组成，以促进扩散阻挡材料与封装层的粘附。互连顶表面上的扩散阻挡材料防止沿包封层包含互连的材料的横向漂移。当封装电介质层由氮化硅组成时，可以在扩散阻挡材料的顶部上形成氮化表面，该方法是在将扩散阻挡材料的顶部暴露于氮等离子体之前，将氮化硅封装层沉积在扩散层顶部阻隔材料。当互连是铜互连并且当封装层由氮化硅构成时，本发明可以被用于特别的优点。

10. 发明授权

US06387806B1 Filling an interconnect opening with different types of alloys to enhance interconnect reliability 有权
标题翻译：用不同类型的合金填充互连开口以增强互连的可靠性
公开(公告)号：US06387806B1
公开(公告)日：2002-05-14
申请号：US09655700
申请日：2000-09-06
申请人： Pin-Chin C. Wang , Christy M. Woo
发明人： Pin-Chin C. Wang , Christy M. Woo
IPC分类号： H01L2144
CPC分类号： H01L21/76849 , H01L21/76804 , H01L21/7684 , H01L21/76843 , H01L21/76867 , H01L21/76873 , H01L21/76877 , H01L21/76888 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An interconnect opening of an integrated circuit is filled with a conductive fill, such as copper, with the interconnect opening being within an insulating layer on a semiconductor wafer. A seed layer of a first alloy is deposited conformally onto sidewalls and a bottom wall of the interconnect opening. The first alloy is comprised of a first metal dopant in a bulk conductive material. The first metal dopant has a relatively high solid solubility in the bulk conductive material, and the first metal dopant has a concentration in the bulk conductive material of the seed layer that is lower than the solid solubility of the first metal dopant in the bulk conductive material. At least a portion of the conductive fill grown from the seed layer is comprised of a second alloy with a second metal dopant having a relatively low solid solubility in the bulk conductive material, and the second metal dopant has a concentration in the conductive fill that is higher than the solid solubility of the second metal dopant in the bulk conductive material. A thermal anneal is performed to form an additional encapsulating material that covers a top surface of the conductive fill, and the additional encapsulating material is formed from the second metal dopant diffusing out of the conductive fill during the thermal anneal. A layer of bulk passivation material is formed over the additional encapsulating material and the insulating layer. Use of the first alloy of the seed layer prevents agglomeration of the bulk conductive material of the seed layer at the sidewalls of the interconnect opening. The additional encapsulating material prevents drift of material from the conductive fill along the bottom surface of the layer of bulk passivation material and into the surrounding insulating layer.
摘要翻译：集成电路的互连开口填充有诸如铜的导电填料，其中互连开口位于半导体晶片上的绝缘层内。第一合金的籽晶层保形地沉积在互连开口的侧壁和底壁上。第一合金由块状导电材料中的第一金属掺杂剂构成。第一金属掺杂剂在体导电材料中具有相对高的固溶度，并且第一金属掺杂剂在晶种层的本体导电材料中的浓度低于第一金属掺杂剂在体导电材料中的固溶度。从种子层生长的至少一部分导电填料由具有在本体导电材料中具有相对低的固溶度的第二金属掺杂剂的第二合金构成，并且第二金属掺杂剂在导电填料中的浓度为高于第二金属掺杂剂在体导电材料中的固溶度。进行热退火以形成覆盖导电填料的顶表面的另外的封装材料，并且另外的封装材料由热退火期间从导电填料中扩散出的第二金属掺杂剂形成。在附加的封装材料和绝缘层上形成一层体积钝化材料。种子层的第一合金的使用防止种子层的体导电材料在互连开口的侧壁处的聚集。附加的封装材料防止材料沿着主体钝化材料层的底表面漂移到导电填料中并进入周围绝缘层。

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