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1. 发明授权

US06426293B1 Minimizing resistance and electromigration of interconnect by adjusting anneal temperature and amount of seed layer dopant 失效
标题翻译：通过调整退火温度和种子层掺杂剂的量来最小化互连的电阻和电迁移
公开(公告)号：US06426293B1
公开(公告)日：2002-07-30
申请号：US09872717
申请日：2001-06-01
申请人： Pin-Chin C. Wang , Sergey Lopatin , Amit P. Marathe
发明人： Pin-Chin C. Wang , Sergey Lopatin , Amit P. Marathe
IPC分类号： H01L2144
CPC分类号： H01L21/76864 , H01L21/76843 , H01L21/76873 , H01L21/76874 , H01L21/76877 , H01L2221/1089
摘要： A plurality of test interconnect structures are formed with each test interconnect structure having a respective alloy seed layer and with a fill conductive material formed to fill the respective interconnect opening. The respective alloy seed layer of each of the test interconnect structures has a respective thickness and a respective concentration of an alloy dopant within a bulk conductive material. A respective thermal anneal process is performed at a respective thermal anneal temperature for each of the plurality of test interconnect structures. A respective resistance and a respective rate of electromigration failure is measured for each of the plurality of test interconnect structures. For forming an IC interconnect structure within an IC interconnect opening, an alloy seed layer is deposited onto sidewalls and a bottom wall of the IC interconnect opening, and the IC interconnect opening is filled by growing a fill conductive material from the alloy seed layer within the IC interconnect opening. A thermal anneal process is performed at a thermal anneal temperature. A desired thickness of the alloy seed layer, a desired concentration of the alloy dopant, and a desired thermal anneal temperature for the IC interconnect structure are adjusted depending on the respective thickness of the alloy seed layer, the respective concentration of the alloy dopant, and the respective thermal anneal temperature of one of the plurality of test interconnect structures having the respective resistance that is closest to a desired resistance and/or having a respective measured rate of electromigration failure that is closest to a desired rate of electromigration failure for the IC interconnect structure.
摘要翻译：形成多个测试互连结构，每个测试互连结构具有相应的合金种子层，并且形成有填充导电材料以填充相应的互连开口。每个测试互连结构的相应的合金种子层具有相应的厚度和相应的体积导电材料内的合金掺杂剂的浓度。对于多个测试互连结构中的每一个，在相应的热退火温度下执行相应的热退火工艺。针对多个测试互连结构中的每一个测量相应的电阻和相应的电迁移失败率。为了在IC互连开口内形成IC互连结构，将合金晶种层沉积在IC互连开口的侧壁和底壁上，并且通过从合金种子层内生长填充导电材料来填充IC互连开口 IC互连开口。热退火工艺在热退火温度下进行。根据合金种子层的各自的厚度，合金掺杂剂的相应浓度以及合金种子层的相应浓度，合金种子层的期望厚度，合金掺杂剂的期望浓度和IC互连结构的期望的热退火温度多个测试互连结构中的一个测试互连结构的相应热退火温度具有最接近期望电阻的相应电阻和/或具有最接近IC互连的期望的电迁移失败率的相应测量的电迁移失败率结构体。

2. 发明授权

US06528412B1 Depositing an adhesion skin layer and a conformal seed layer to fill an interconnect opening 有权
标题翻译：沉积粘合表皮层和保形种子层以填充互连开口
公开(公告)号：US06528412B1
公开(公告)日：2003-03-04
申请号：US09844727
申请日：2001-04-30
申请人： Pin-Chin C. Wang , Sergey Lopatin
发明人： Pin-Chin C. Wang , Sergey Lopatin
IPC分类号： H01L214763
CPC分类号： H01L21/76843 , H01L21/76826 , H01L21/76831 , H01L21/76846 , H01L21/76862 , H01L21/76864 , H01L21/76868 , H01L23/53238 , H01L2924/0002 , Y10S977/712 , Y10S977/723 , Y10S977/81 , Y10S977/89 , H01L2924/00
摘要： For filling an interconnect opening within an insulating layer on a semiconductor wafer, an adhesion skin layer is deposited conformally onto an underlying material comprised of one of a barrier material or a dielectric material at sidewalls and a bottom wall of the interconnect opening. The adhesion skin layer includes a metal alloy doping element. A conformal seed layer is deposited onto the adhesion skin layer using a conformal deposition process, such as an ECD (electrochemical deposition) or a CVD (chemical-vapor-deposition) process. The adhesion skin layer promotes adhesion of the conformal seed layer to the underlying material at the sidewalls and the bottom wall of the interconnect opening. The interconnect opening is filled with a conductive material grown from the conformal seed layer. In this manner, the adhesion skin layer promotes adhesion of the conformal seed layer to the underlying material to minimize electromigration failure of the interconnect. In addition, the seed layer formed by conventional PVD (physical-vapor-deposition) processes is avoided with the present invention. Instead, the relatively thin adhesion skin layer and the relatively thin conformal seed layer are used for plating the conductive fill. With such relatively thin layers, an interconnect opening having a high aspect ratio is filled with minimized void formation.
摘要翻译：为了在半导体晶片上的绝缘层内填充互连开口，将粘合表皮层保形地沉积在由互连开口的侧壁和底壁处的阻挡材料或电介质材料之一构成的下层材料上。粘合性表皮层包括金属合金掺杂元素。使用诸如ECD（电化学沉积）或CVD（化学气相沉积）工艺的共形沉积工艺将保形种子层沉积到粘附表皮层上。附着表皮层促进保形种子层在互连开口的侧壁和底壁处的下层材料的附着。互连开口填充有从保形晶种层生长的导电材料。以这种方式，粘合表皮层促进保形种子层与底层材料的粘附，以最小化互连的电迁移失效。此外，通过本发明避免了通过常规PVD（物理 - 气相沉积）方法形成的晶种层。相反，使用相对薄的粘合表皮层和相对薄的保形晶种层来镀覆导电填料。利用这种相对薄的层，具有高纵横比的互连开口填充有最小化的空隙形成。

3. 发明授权

US06228759B1 Method of forming an alloy precipitate to surround interconnect to minimize electromigration 有权
标题翻译：形成合金沉淀物以围绕互连以最小化电迁移的方法
公开(公告)号：US06228759B1
公开(公告)日：2001-05-08
申请号：US09561622
申请日：2000-05-02
申请人： Pin-Chin C. Wang , Christy M. Woo , Sergey Lopatin
发明人： Pin-Chin C. Wang , Christy M. Woo , Sergey Lopatin
IPC分类号： H01L214763
CPC分类号： H01L21/76804 , H01L21/2855 , H01L21/76843 , H01L21/76849 , H01L21/76867 , H01L21/76873 , H01L21/76877 , H01L21/76886 , H01L2221/1089
摘要： An alloy precipitate is formed to surround a conductive fill within an interconnect opening, including especially a top surface of the conductive fill, to prevent drift of material from the conductive fill into the insulating layer that is surrounding the interconnect opening. An alloy material is deposited non-conformally such that the alloy material is deposited substantially only toward a top of the sidewalls of an interconnect opening and substantially only toward a center of the bottom wall of the interconnect opening. The interconnect opening is filled with the conductive material by growing the conductive material from a seed layer of the conductive material to form a conductive fill of the conductive material within the interconnect opening. The semiconductor wafer is heated to anneal the conductive fill within the interconnect opening such that the conductive fill forms into a substantially single grain structure. During the thermal anneal, reactant within the alloy material migrates along a top surface of the conductive fill and along a grain boundary of the conductive fill. An alloy precipitate is formed from a reaction between the reactant and the conductive material at the top surface and at the grain boundary of the conductive fill when the semiconductor wafer is then cooled down. The alloy precipitate at the top surface and at the grain boundary of the conductive fill prevents drift of the conductive material along the top surface and along the grain boundary of the conductive fill and into the insulating layer surrounding the interconnect opening.
摘要翻译：形成合金沉淀物以包围互连开口内的导电填料，特别包括导电填料的顶表面，以防止材料从导电填料漂移到围绕互连开口的绝缘层中。合金材料被非保形地沉积，使得合金材料基本上仅沉积在互连开口的侧壁的顶部并且基本上仅朝向互连开口的底壁的中心。通过从导电材料的种子层生长导电材料以在互连开口内形成导电材料的导电填充物，从而用导电材料填充互连开口。加热半导体晶片以使互连开口内的导电填充物退火，使得导电填料形成基本上单一的晶粒结构。在热退火期间，合金材料内的反应物沿着导电填料的顶表面沿导电填料的晶界迁移。当半导体晶片然后冷却时，在导电填料的顶表面和晶界处的反应物和导电材料之间的反应形成合金沉淀。在导电填料的顶表面和晶界处的合金沉淀物防止导电材料沿着顶表面和沿着导电填料的晶界并漂浮到围绕互连开口的绝缘层中。

4. 发明授权

US06447933B1 Formation of alloy material using alternating depositions of alloy doping element and bulk material 失效
公开(公告)号：US06447933B1
公开(公告)日：2002-09-10
申请号：US09845616
申请日：2001-04-30
申请人： Pin-Chin C. Wang , Sergey Lopatin
发明人： Pin-Chin C. Wang , Sergey Lopatin
IPC分类号： B32B1500
CPC分类号： H01L21/76846 , C23C26/00 , H01L21/28562 , H01L21/32051 , H01L21/76843 , H01L21/76858 , H01L21/76873 , H01L21/76886 , H01L2221/1089 , Y10T428/12632
摘要： An alloy material is formed on an underlying material, and the alloy material comprises an alloy doping element mixed into a bulk material. A first layer of material including the alloy doping element is deposited on the underlying material using a first type of deposition process. The first type of deposition process is corrosion resistive to the underlying material according to one aspect of the present invention. A second layer of material including the bulk material is deposited on the first layer of material using a second type of deposition process. A thermal anneal may be performed by heating the first layer of material and the second layer of material such that the alloy doping element is mixed into the bulk material to form the alloy material on the underlying material. The alloy doping element of the first layer of material deposited on the underlying material promotes adhesion of the alloy material to the underlying material. The present invention may be used to particular advantage when the underlying material is a diffusion barrier material deposited on sidewalls and a bottom wall of an interconnect opening, and when the alloy material is a copper alloy formed on the diffusion barrier material. In this manner, a plurality of deposition processes are used for forming a stack of layers of materials comprising the alloy material. The first type of deposition process for depositing the first layer of material on the underlying material is corrosion resistive to the underlying material. Corrosion to the underlying material is undesired because corrosion to the underlying material may degrade the adhesion of the interconnect to the underlying material to increase undesired electromigration failure of the interconnect. The second deposition process for depositing the second layer of material on the first layer of material may be a faster deposition process for depositing the bulk material of the alloy.

5. 发明授权

US07945086B2 Tungsten plug deposition quality evaluation method by EBACE technology 有权
标题翻译：钨丝塞沉积质量评估方法采用EBACE技术
公开(公告)号：US07945086B2
公开(公告)日：2011-05-17
申请号：US11622793
申请日：2007-01-12
申请人： Yehiel Gotkis , Sergey Lopatin , Mehran Nasser-Ghodsi
发明人： Yehiel Gotkis , Sergey Lopatin , Mehran Nasser-Ghodsi
IPC分类号： G06K9/00 , H01L21/3205
CPC分类号： H01L22/12 , H01L22/34
摘要： A first embodiment of the invention relates to a method for evaluating the quality of structures on an integrated circuit wafer. Test structures formed on either on the integrated or on a test wafer are exposed to an electron beam and an electron-beam activated chemical etch. The electron-beam activated etching gas or vapor etches the test structures, which are analyzed after etching to determine a measure of quality of the test structures. The measure of quality may be used in a statistical process control to adjust the parameters used to form device structures on the integrated circuit wafer. The test structures are formed on an integrated circuit wafer having two or more die. Each die has one or more integrated circuit structures. The test structures are formed on scribe lines between two or more adjacent die. Each test structure may correspond in dimensions and/or composition to one or more of the integrated circuit structures.
摘要翻译：本发明的第一实施例涉及一种用于评估集成电路晶片上的结构质量的方法。在集成的或在测试晶片上形成的测试结构暴露于电子束和电子束活化的化学蚀刻。电子束活化的蚀刻气体或蒸气蚀刻测试结构，其在蚀刻后分析以确定测试结构的质量的度量。可以在统计过程控制中使用质量测量来调整用于在集成电路晶片上形成器件结构的参数。测试结构形成在具有两个或更多个管芯的集成电路晶片上。每个管芯具有一个或多个集成电路结构。测试结构形成在两个或更多相邻模具之间的划线上。每个测试结构可以在尺寸和/或组成上与一个或多个集成电路结构相对应。

6. 发明申请

US20110031113A1 ELECTROPLATING APPARATUS 审中-公开
标题翻译：电镀设备
公开(公告)号：US20110031113A1
公开(公告)日：2011-02-10
申请号：US12906008
申请日：2010-10-15
申请人： Sergey Lopatin , Nicolay Y. Kovarsky , David Eaglesham , John O. Dukovic , Charles Gay
发明人： Sergey Lopatin , Nicolay Y. Kovarsky , David Eaglesham , John O. Dukovic , Charles Gay
IPC分类号： C25D17/00
CPC分类号： H01L31/022425 , C25D5/022 , C25D5/10 , C25D7/126 , Y02E10/50
摘要： Embodiments of the invention contemplate the formation of a low cost solar cell using a novel high speed electroplating method and apparatus to form a metal contact structure having selectively formed metal lines using an electrochemical plating process. The apparatus and methods described herein remove the need to perform one or more high temperature screen printing processes to form conductive features on the surface of a solar cell substrate. The resistance of interconnects formed in a solar cell device greatly affects the efficiency of the solar cell. It is thus desirable to form a solar cell device that has a low resistance connection that is reliable and cost effective. Therefore, one or more embodiments of the invention described herein are adapted to form a low cost and reliable interconnecting layer using an electrochemical plating process containing a common metal, such as copper.
摘要翻译：本发明的实施例考虑使用新颖的高速电镀方法和装置形成低成本太阳能电池，以形成具有使用电化学电镀工艺的选择性形成的金属线的金属接触结构。本文所述的装置和方法消除了执行一个或多个高温丝网印刷工艺以在太阳能电池基板的表面上形成导电特征的需要。在太阳能电池器件中形成的互连的电阻极大地影响太阳能电池的效率。因此，希望形成具有可靠和成本有效的低电阻连接的太阳能电池装置。因此，本文描述的本发明的一个或多个实施例适用于使用包含普通金属（例如铜）的电化学电镀工艺形成低成本且可靠的互连层。

7. 发明授权

US07879730B2 Etch selectivity enhancement in electron beam activated chemical etch 有权
标题翻译：电子束激活化学蚀刻中的蚀刻选择性增强
公开(公告)号：US07879730B2
公开(公告)日：2011-02-01
申请号：US11622605
申请日：2007-01-12
申请人： Mehran Naser-Ghodsi , Garrett Pickard , Rudy F. Garcia , Tzu-Chin Chuang , Ming Lun Yu , Kenneth Krzeczowski , Matthew Lent , Sergey Lopatin , Chris Huang , Niles K. MacDonald
发明人： Mehran Naser-Ghodsi , Garrett Pickard , Rudy F. Garcia , Tzu-Chin Chuang , Ming Lun Yu , Kenneth Krzeczowski , Matthew Lent , Sergey Lopatin , Chris Huang , Niles K. MacDonald
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： C23F4/00 , H01J2237/31744 , H01L21/3065 , H01L21/32136
摘要： Etch selectivity enhancement during electron beam activated chemical etch (EBACE) is disclosed. A target or portion thereof may be exposed to a gas composition of a type that etches the target when the gas composition and/or target are exposed to an electron beam. By directing an electron beam toward the target in the vicinity of the gas composition, an interaction between the electron beam and the gas composition etches a portion of the target exposed to both the gas composition and the electron beam. Selectivity of etching of the target due to interaction between the electron beam and gas composition may be enhanced in a number of ways.
摘要翻译：公开了电子束激活化学蚀刻（EBACE）期间的蚀刻选择性增强。当气体组合物和/或靶暴露于电子束时，靶或其部分可暴露于蚀刻靶的类型的气体组合物。通过在气体组合物附近引导电子束朝向靶，电子束和气体组成之间的相互作用会蚀刻暴露于气体组成和电子束两者的靶的一部分。可以以多种方式增强由于电子束和气体组成之间的相互作用而导致的靶的蚀刻选择性。

8. 发明申请

US20080128013A1 ELECTROPLATING ON ROLL-TO-ROLL FLEXIBLE SOLAR CELL SUBSTRATES 失效
标题翻译：在滚动到滚动的柔性太阳能电池基板上进行电镀
公开(公告)号：US20080128013A1
公开(公告)日：2008-06-05
申请号：US11566200
申请日：2006-12-01
申请人： Sergey Lopatin , David Eaglesham , Charles Gay
发明人： Sergey Lopatin , David Eaglesham , Charles Gay
IPC分类号： H01L31/042 , C23C14/00
CPC分类号： C25D5/022 , C25D5/18 , C25D7/08 , C25D17/00 , C25D17/001 , H01L31/022425 , H01L31/02245 , H01L31/022466 , H01L31/03926 , H01L31/0465 , H01L31/0508 , H01L31/0512 , H01L31/0516 , H01L31/188 , Y02E10/50
摘要： Embodiments of the invention contemplate the formation of a low cost flexible solar cell using a novel electroplating method and apparatus to form a metal contact structure. The apparatus and methods described herein remove the need to perform one or more high temperature screen printing processes to form conductive features on the surface of a solar cell substrate. The resistance of interconnects formed in a solar cell device greatly affects the efficiency of the solar cell. Solar cell substrates that may benefit from the invention include flexible substrates may have an active region that contains organic material, single crystal silicon, multi-crystalline silicon, polycrystalline silicon, germanium, and gallium arsenide, cadmium telluride, cadmium sulfide, copper indium gallium selenide, copper indium selenide, gallilium indium phosphide, as well as heterojunction cells that are used to convert sunlight to electrical power. The flexible substrates may have a flexible base that is adapted to support the active region of the solar cell device.
摘要翻译：本发明的实施例考虑使用新颖的电镀方法和装置形成金属接触结构来形成低成本的柔性太阳能电池。本文所述的装置和方法消除了执行一个或多个高温丝网印刷工艺以在太阳能电池基板的表面上形成导电特征的需要。在太阳能电池器件中形成的互连的电阻极大地影响太阳能电池的效率。可以受益于本发明的太阳能电池基板包括柔性基板可以具有含有有机材料，单晶硅，多晶硅，多晶硅，锗和砷化镓，碲化镉，硫化镉，铜铟镓硒的有源区，铜铟硒化铟，磷化铟镓，以及用于将阳光转换成电力的异质结电池。柔性基板可以具有适于支撑太阳能电池装置的有源区域的柔性基座。

9. 发明申请

US20080092947A1 PULSE PLATING OF A LOW STRESS FILM ON A SOLAR CELL SUBSTRATE 审中-公开
标题翻译：在太阳能电池基板上的低应力膜的脉冲电镀
公开(公告)号：US20080092947A1
公开(公告)日：2008-04-24
申请号：US11552497
申请日：2006-10-24
申请人： Sergey Lopatin , Charles Gay , David Eaglesham , John O. Dukovic , Nicolay Y. Kovarsky
发明人： Sergey Lopatin , Charles Gay , David Eaglesham , John O. Dukovic , Nicolay Y. Kovarsky
IPC分类号： H01L31/00
CPC分类号： H01L31/022425 , H01L31/02245 , Y02E10/50
摘要： Embodiments of the invention contemplate the formation of a low cost solar cell metal contact structure that has improved electrical and mechanical properties through the use of an electrochemical plating process. The resistance of interconnects formed in a solar cell device greatly affects the efficiency of the solar cell. It is thus desirable to form a solar cell device that has a low resistance connections that is reliable and cost effective. One or more embodiments of the invention described herein are adapted to form a low cost and reliable interconnecting layer using an electrochemical plating process containing common metal, such as copper. However, generally the electroplated portions of the interconnecting layer may contain a substantially pure metal or a metal alloy layer. Methods are discussed herein that are used to form a solar cell containing conductive metal interconnect layer(s) that have a low intrinsic stress.
摘要翻译：本发明的实施例考虑到通过使用电化学电镀工艺形成具有改善的电气和机械性能的低成本太阳能电池金属接触结构。在太阳能电池器件中形成的互连的电阻极大地影响太阳能电池的效率。因此，希望形成具有可靠和成本有效的低电阻连接的太阳能电池装置。使用本文所述的本发明的一个或多个实施例适用于使用包含普通金属（例如铜）的电化学电镀工艺形成低成本且可靠的互连层。然而，通常互连层的电镀部分可以包含基本上纯的金属或金属合金层。本文讨论了用于形成含有具有低固有应力的导电金属互连层的太阳能电池的方法。

10. 发明授权

US07273813B2 Wafer cleaning solution for cobalt electroless application 有权
标题翻译：用于钴无电镀的晶圆清洗液
公开(公告)号：US07273813B2
公开(公告)日：2007-09-25
申请号：US11053501
申请日：2005-02-08
申请人： Ramin Emami , Timothy Weidman , Sergey Lopatin , Hongbin Fang , Arulkumar Shanmugasundram
发明人： Ramin Emami , Timothy Weidman , Sergey Lopatin , Hongbin Fang , Arulkumar Shanmugasundram
IPC分类号： H01L21/44
CPC分类号： C23C18/1844 , C11D7/06 , C11D7/08 , C11D7/265 , C11D11/0047 , C23F1/18 , C23G1/103 , H01L21/02074 , H01L21/76826 , H01L21/76849 , H01L21/76877 , H01L21/76883
摘要： A method and cleaning solution that removes contaminants from a dielectric material and polished surfaces of copper interconnect structures prior to an electroless deposition of a capping layer without substantially adversely affecting the interconnect formed therefrom are disclosed. The cleaning solution includes combinations of a core mixture and sulfuric acid or sulfonic compounds such as sulfonic acids that include methanesulfonic acid. In one embodiment, the core mixture includes a citric acid solution and a pH adjuster such as tetra-methyl ammonium hydroxide or ammonia. One embodiment of the method includes providing a planarized substrate, applying the cleaning solution to the substrate to simultaneously clean at least one metal feature and a dielectric material of the substrate, and depositing the metal capping layer selectively on the at least one metal feature using electroless deposition.
摘要翻译：公开了一种方法和清洁溶液，其在电绝缘沉积覆盖层之前从电介质材料和铜互连结构的抛光表面去除污染物，而基本上不利地影响由其形成的互连。清洁溶液包括核混合物和硫酸或磺酸化合物如包括甲磺酸的磺酸的组合。在一个实施方案中，核心混合物包括柠檬酸溶液和pH调节剂如四甲基氢氧化铵或氨。该方法的一个实施例包括提供平坦化的基板，将清洁溶液施加到基板上以同时清洁基板的至少一个金属特征和介电材料，并且使用无电镀将金属覆盖层选择性地沉积在至少一个金属特征上沉积

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