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41. 发明授权

US06525985B2 Semiconductor memory device 失效
公开(公告)号：US06525985B2
公开(公告)日：2003-02-25
申请号：US09577366
申请日：2000-05-23
申请人： Hiroyuki Mizuno , Suguru Tachibana , Koichiro Ishibashi , Kenichi Osada
发明人： Hiroyuki Mizuno , Suguru Tachibana , Koichiro Ishibashi , Kenichi Osada
IPC分类号： G11C514
CPC分类号： G11C7/18 , G06F12/0893 , G11C5/063 , G11C7/06 , G11C7/22 , G11C2207/108 , Y02D10/13
摘要： A memory structure/circuit has at least two memory cell arrays connected to each other in a hierarchy. The bit lines of the two or more memory cell arrays are connected by hierarchy switches. The memory cells of one of the arrays can be read out faster than the others by using the hierarchy switches to select one array without selecting the other arrays. So the data that is read with higher frequency can be selectively read out faster if it is stored in the faster access memory array. If the data in the faster access memory cell array includes a copy of the data in the other array, it can be used as a cache memory. A tag array and data array in combination that are connected to another tag array and data array in combination through hierarchy switch connections can provide a cache memory that is direct mapped or set associative, and also full associative. The memory device can be used in a semiconductor data processor having a CPU in which the memory device is connected to the CPU through a bus, wherein both the CPU and the memory device are formed on a single semiconductor substrate. The memory device can also be an off-chip device.

42. 发明授权

US06515894B2 Semiconductor memory apparatus, semiconductor apparatus, data processing apparatus and computer system 失效
公开(公告)号：US06515894B2
公开(公告)日：2003-02-04
申请号：US09988197
申请日：2001-11-19
申请人： Kenichi Osada , Hisayuki Higuchi , Koichiro Ishibashi
发明人： Kenichi Osada , Hisayuki Higuchi , Koichiro Ishibashi
IPC分类号： G11C1100
CPC分类号： G11C7/18 , G06F12/0802 , G11C7/065
摘要： A semiconductor memory apparatus is provided with a memory array, a first global bit line connected to a sense amplifier, a second global bit line connected to a write amplifier, and a selection circuit for connecting a plurality of bit lines selectively to the first global bit line and the second global bit line.

43. 发明授权

US06436753B1 Semiconductor integrated circuit and method for manufacturing the same 有权
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US06436753B1
公开(公告)日：2002-08-20
申请号：US09372007
申请日：1999-08-11
申请人： Shuji Ikeda , Yasuko Yoshida , Masayuki Kojima , Kenji Shiozawa , Mitsuyuki Kimura , Norio Nakagawa , Koichiro Ishibashi , Yasuhisa Shimazaki , Kenichi Osada , Kunio Uchiyama
发明人： Shuji Ikeda , Yasuko Yoshida , Masayuki Kojima , Kenji Shiozawa , Mitsuyuki Kimura , Norio Nakagawa , Koichiro Ishibashi , Yasuhisa Shimazaki , Kenichi Osada , Kunio Uchiyama
IPC分类号： H01L218244
CPC分类号： H01L27/105 , H01L27/1052
摘要： An operational margin of a memory of a semiconductor integrated circuit device including an SRAM is improved. In order to set the Vth of driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance QL forming memory cells of an SRAM, relatively and intentionally higher than the Vth of predetermined MISFETs of SRAM peripheral circuits and logic circuits, such as a microprocessor, an impurity introduction step is introduced to set the Vth of the driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance, separately from an impurity introduction step for setting the Vth of the predetermined MISFETs.
摘要翻译：提高了包括SRAM的半导体集成电路器件的存储器的操作裕度。为了设置驱动MISFET Qd的Vth，对于形成SRAM的存储单元的负载电阻QL的转移MISFET Qt和MISFET相对有意地高于诸如微处理器的SRAM外围电路和逻辑电路的预定MISFET的Vth，引入杂质引入步骤，用于设置用于设置预定MISFET的Vth的杂质引入步骤的驱动MISFET Qd，负载电阻的转移MISFET Qt和MISFET的Vth。

44. 发明授权

US06396732B1 Semiconductor memory apparatus, semiconductor apparatus, data processing apparatus and computer system 失效
公开(公告)号：US06396732B1
公开(公告)日：2002-05-28
申请号：US09577149
申请日：2000-05-24
申请人： Kenichi Osada , Hisayuki Higuchi , Koichiro Ishibashi
发明人： Kenichi Osada , Hisayuki Higuchi , Koichiro Ishibashi
IPC分类号： G11C1100
CPC分类号： G11C7/18 , G06F12/0802 , G11C7/065
摘要： A semiconductor memory apparatus is provided with a memory array, a first global bit line connected to a sense amplifier, a second global bit line connected to a write amplifier, and a selection circuit for connecting a plurality of bit lines selectively to the first global bit line and the second global bit line.

45. 发明授权

US06295218B1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06295218B1
公开(公告)日：2001-09-25
申请号：US09549230
申请日：2000-04-13
申请人： Kenichi Osada , Koichiro Ishibashi
发明人： Kenichi Osada , Koichiro Ishibashi
IPC分类号： G11C1500
CPC分类号： G06F12/1027 , G06F12/0864 , G11C15/00 , G11C15/04
摘要： A memory device having a plurality of blocks, each of a plurality of blocks comprising a memory array having a plurality of word lines and a plurality of memory cells connected to the word lines, an associative cell array for outputting a hit signal by comparing a first address inputted thereto with internal data and a decoder circuit for selecting one line by decoding a second address and wherein one of the word lines is selected based on the line selected by the decoder circuit and the hit signal.
摘要翻译：一种存储器件，具有多个块，多个块中的每一个包括具有多个字线的存储器阵列和连接到所述字线的多个存储器单元;相关单元阵列，用于通过比较第一用内部数据输入的地址，以及通过解码第二地址来选择一行的解码器电路，并且其中基于由解码器电路选择的行和命中信号来选择一个字线。

46. 发明授权

US5943284A Semiconductor memory device 失效
公开(公告)号：US5943284A
公开(公告)日：1999-08-24
申请号：US705315
申请日：1996-08-29
申请人： Hiroyuki Mizuno , Suguru Tachibana , Koichiro Ishibashi , Kenichi Osada
发明人： Hiroyuki Mizuno , Suguru Tachibana , Koichiro Ishibashi , Kenichi Osada
IPC分类号： G11C11/41 , G06F12/08 , G11C5/06 , G11C7/06 , G11C7/18 , G11C7/22 , G11C11/401 , G11C11/409 , G11C13/00
CPC分类号： G11C7/18 , G06F12/0893 , G11C5/063 , G11C7/06 , G11C7/22 , G11C2207/108 , Y02B60/1225
摘要： A memory structure/circuit has at least two memory cell arrays connected to each other in a hierarchy. The bit lines of the two or more memory cell arrays are connected by hierarchy switches. The memory cells of one of the arrays can be read out faster than the others by using the hierarchy switches to select one array without selecting the other arrays. So the data that is read with higher frequency can be selectively read out faster if it is stored in the faster access memory array. If the data in the faster access memory cell array includes a copy of the data in the other array, it can be used as a cache memory. A tag array and data array in combination that are connected to another tag array and data array in combination through hierarchy switch connections can provide a cache memory that is direct mapped or set associative, and also full associative. The memory device can be used in a semiconductor data processor having a CPU in which the memory device is connected to the CPU through a bus, wherein both the CPU and the memory device are formed on a single semiconductor substrate. The memory device can also be an off-chip device.

47. 发明授权

US09286968B2 Semiconductor integrated circuit device including SRAM cell array and a wiring layer for supplying voltage to well regions of SRAM cells provided on a region exterior of SRAM cell array 有权
标题翻译：包括SRAM单元阵列的半导体集成电路器件和用于向SRAM单元阵列的外部区域上提供的SRAM单元的阱区域提供电压的布线层
公开(公告)号：US09286968B2
公开(公告)日：2016-03-15
申请号：US13616435
申请日：2012-09-14
申请人： Kenichi Osada , Masataka Minami , Shuji Ikeda , Koichiro Ishibashi
发明人： Kenichi Osada , Masataka Minami , Shuji Ikeda , Koichiro Ishibashi
IPC分类号： H01L29/76 , H01L27/11 , G11C11/412
CPC分类号： H01L27/1104 , G11C11/412 , G11C11/417 , H01L27/11 , H01L29/4916 , H01L29/783 , Y10S257/904
摘要： Prior known static random access memory (SRAM) cells required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supply power to the substrate are formed in parallel to word lines.
摘要翻译：现有已知的静态随机存取存储器（SRAM）单元需要将扩散层弯曲成键状形状，以便与其中形成有P型阱区的衬底电接触，这将导致不对称性的降低导致微图案化困难。为了避免这个问题，构成SRAM单元的逆变器的P型阱区被细分成两部分，它们设置在N型阱区NW1的相对侧上，并形成为扩散形成晶体管的层没有曲率，同时使得布局方向在平行于阱边界线和位线的方向上运行。在阵列的中间位置处，与基板平行地形成用于向基板供电的区域。

48. 发明申请

US20100301422A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20100301422A1
公开(公告)日：2010-12-02
申请号：US12821329
申请日：2010-06-23
申请人： Kenichi Osada , Masataka Minami , Shuji Ikeda , Koichiro Ishibashi
发明人： Kenichi Osada , Masataka Minami , Shuji Ikeda , Koichiro Ishibashi
IPC分类号： H01L27/11
CPC分类号： H01L27/1104 , G11C11/412 , G11C11/417 , H01L27/11 , H01L29/4916 , H01L29/783 , Y10S257/904
摘要： Prior known static random access memory (SRAM) cells required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supply power to the substrate are formed in parallel to word lines in such a manner that one region is provided per group of thirty two memory cell rows or sixty four cell rows.
摘要翻译：现有已知的静态随机存取存储器（SRAM）单元需要将扩散层弯曲成键状形状，以便与其中形成有P型阱区的衬底电接触，这将导致不对称性的降低导致出现微图案化困难的问题。为了避免这个问题，构成SRAM单元的逆变器的P型阱区被细分成两部分，它们设置在N型阱区NW1的相对侧上，并形成为扩散形成晶体管的层没有曲率，同时使得布局方向在平行于阱边界线和位线的方向上运行。在阵列的中间位置处，用于向衬底供电的区域形成为平行于字线，以这样的方式，每组三十二个存储单元行或六十六个单元行提供一个区域。

49. 发明授权

US07589993B2 Semiconductor memory device with memory cells operated by boosted voltage 有权
标题翻译：具有由升压电压工作的存储单元的半导体存储器件
公开(公告)号：US07589993B2
公开(公告)日：2009-09-15
申请号：US12133343
申请日：2008-06-04
申请人： Masanao Yamaoka , Kenichi Osada , Koichiro Ishibashi
发明人： Masanao Yamaoka , Kenichi Osada , Koichiro Ishibashi
IPC分类号： G11C11/00
CPC分类号： G11C11/417 , G11C11/412 , Y10S257/903
摘要： A memory using an SRAM memory cell intended for low-voltage operation is designed to decrease the threshold value of MOS transistors constituting the memory cell without substantial decrease in the static noise margin, which is the operational margin of the memory cell. To this end, a voltage Vdd′ higher than a power supply voltage Vdd of a power supply line for peripheral circuits is supplied from a power supply line for memory cells as a power supply voltage for memory cells. Since the conductance of driver MOS transistors is in-creased, the threshold voltage of the MOS transistors within the memory cells can be reduced without reducing the static noise margin. Further the ratio of width between the driver MOS transistor and a transfer MOS transistor can be set to 1, thereby allowing a reduction in the memory cell area.
摘要翻译：使用用于低电压操作的SRAM存储单元的存储器被设计为降低构成存储器单元的MOS晶体管的阈值，而不会显着降低静态噪声容限，这是存储单元的操作余量。为此，作为存储单元的电源电压，从用于存储单元的电源线提供高于外围电路用电源线的电源电压Vdd的电压Vdd'。由于驱动器MOS晶体管的电导被增加，所以可以在不降低静态噪声容限的情况下减小存储单元内的MOS晶体管的阈值电压。此外，可以将驱动器MOS晶体管和转移MOS晶体管之间的宽度比设置为1，从而允许存储单元区域的减小。

50. 发明授权

US07388238B2 Semiconductor integrated circuit device with reduced leakage current 有权
公开(公告)号：US07388238B2
公开(公告)日：2008-06-17
申请号：US11452275
申请日：2006-06-14
申请人： Kenichi Osada , Koichiro Ishibashi , Yoshikazu Saitoh , Akio Nishida , Masaru Nakamichi , Naoki Kitai
发明人： Kenichi Osada , Koichiro Ishibashi , Yoshikazu Saitoh , Akio Nishida , Masaru Nakamichi , Naoki Kitai
IPC分类号： H01L27/10
CPC分类号： G11C11/412 , G11C11/40 , G11C11/413 , G11C11/418 , H01L21/823475 , H01L21/823493 , H01L21/823814 , H01L21/82385 , H01L27/088 , H01L27/092 , H01L27/105 , H01L27/1052 , H01L27/11 , H01L27/1104 , H01L27/1116 , H03K19/0016
摘要： The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

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