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1. 发明授权

US06753231B2 Semiconductor integrated circuit and method for manufacturing the same 有权
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US06753231B2
公开(公告)日：2004-06-22
申请号：US10379543
申请日：2003-03-06
申请人： Shuji Ikeda , Yasuko Yoshida , Masayuki Kojima , Kenji Shiozawa , Mitsuyuki Kimura , Norio Nakagawa , Koichiro Ishibashi , Yasuhisa Shimazaki , Kenichi Osada , Kunio Uchiyama
发明人： Shuji Ikeda , Yasuko Yoshida , Masayuki Kojima , Kenji Shiozawa , Mitsuyuki Kimura , Norio Nakagawa , Koichiro Ishibashi , Yasuhisa Shimazaki , Kenichi Osada , Kunio Uchiyama
IPC分类号： H01L21336
CPC分类号： H01L27/105 , H01L27/1052
摘要： An operational margin of a memory of a semiconductor integrated circuit device including an SRAM is improved. In order to set the Vth of driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance QL forming memory cells of an SRAM, relatively and intentionally higher than the Vth of predetermined MISFETs of SRAM peripheral circuits and logic circuits such as microprocessor, an impurity introduction step is introduced to set the Vth of the driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance, separately from an impurity introduction step for setting the Vth of the predetermined MISFETs.
摘要翻译：提高了包括SRAM的半导体集成电路器件的存储器的操作裕度。为了设置驱动MISFET Qd的Vth，传输用于形成SRAM的存储单元的负载电阻QL的MISFET Qt和MISFET相对有意地高于SRAM外围电路和诸如微处理器的逻辑电路的预定MISFET的Vth，杂质介绍引入步骤，用于设置驱动MISFET Qd的Vth，用于负载电阻的传输MISFET Qt和MISFET，与用于设置预定MISFET的Vth的杂质引入步骤分开。

2. 发明授权

US06559006B2 Semiconductor integrated circuit and method for manufacturing the same 有权
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US06559006B2
公开(公告)日：2003-05-06
申请号：US10157978
申请日：2002-05-31
申请人： Shuji Ikeda , Yasuko Yoshida , Masayuki Kojima , Kenji Shiozawa , Mitsuyuki Kimura , Norio Nakagawa , Koichiro Ishibashi , Yasuhisa Shimazaki , Kenichi Osada , Kunio Uchiyama
发明人： Shuji Ikeda , Yasuko Yoshida , Masayuki Kojima , Kenji Shiozawa , Mitsuyuki Kimura , Norio Nakagawa , Koichiro Ishibashi , Yasuhisa Shimazaki , Kenichi Osada , Kunio Uchiyama
IPC分类号： H01L218242
CPC分类号： H01L27/105 , H01L27/1052
摘要： An operational margin of a memory of a semiconductor integrated circuit device including an SRAM is improved. In order to set the Vth of driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance QL forming memory cells of an SRAM, relatively and intentionally higher than the Vth of predetermined MISFETs of SRAM peripheral circuits and logic circuits such as microprocessor, an impurity introduction step is introduced to set the Vth of the driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance, separately from an impurity introduction step for setting the Vth of the predetermined MISFETs.
摘要翻译：提高了包括SRAM的半导体集成电路器件的存储器的操作裕度。为了设置驱动MISFET Qd的Vth，传输用于形成SRAM的存储单元的负载电阻QL的MISFET Qt和MISFET相对有意地高于SRAM外围电路和诸如微处理器的逻辑电路的预定MISFET的Vth，杂质介绍引入步骤，用于设置驱动MISFET Qd的Vth，用于负载电阻的传输MISFET Qt和MISFET，与用于设置预定MISFET的Vth的杂质引入步骤分开。

3. 发明授权

US06436753B1 Semiconductor integrated circuit and method for manufacturing the same 有权
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US06436753B1
公开(公告)日：2002-08-20
申请号：US09372007
申请日：1999-08-11
申请人： Shuji Ikeda , Yasuko Yoshida , Masayuki Kojima , Kenji Shiozawa , Mitsuyuki Kimura , Norio Nakagawa , Koichiro Ishibashi , Yasuhisa Shimazaki , Kenichi Osada , Kunio Uchiyama
发明人： Shuji Ikeda , Yasuko Yoshida , Masayuki Kojima , Kenji Shiozawa , Mitsuyuki Kimura , Norio Nakagawa , Koichiro Ishibashi , Yasuhisa Shimazaki , Kenichi Osada , Kunio Uchiyama
IPC分类号： H01L218244
CPC分类号： H01L27/105 , H01L27/1052
摘要： An operational margin of a memory of a semiconductor integrated circuit device including an SRAM is improved. In order to set the Vth of driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance QL forming memory cells of an SRAM, relatively and intentionally higher than the Vth of predetermined MISFETs of SRAM peripheral circuits and logic circuits, such as a microprocessor, an impurity introduction step is introduced to set the Vth of the driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance, separately from an impurity introduction step for setting the Vth of the predetermined MISFETs.
摘要翻译：提高了包括SRAM的半导体集成电路器件的存储器的操作裕度。为了设置驱动MISFET Qd的Vth，对于形成SRAM的存储单元的负载电阻QL的转移MISFET Qt和MISFET相对有意地高于诸如微处理器的SRAM外围电路和逻辑电路的预定MISFET的Vth，引入杂质引入步骤，用于设置用于设置预定MISFET的Vth的杂质引入步骤的驱动MISFET Qd，负载电阻的转移MISFET Qt和MISFET的Vth。

4. 发明授权

US06403446B1 Method for manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06403446B1
公开(公告)日：2002-06-11
申请号：US09536447
申请日：2000-03-28
申请人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Yasuko Yoshida , Norio Suzuki , Masayuki Kojima , Kota Funayama
发明人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Yasuko Yoshida , Norio Suzuki , Masayuki Kojima , Kota Funayama
IPC分类号： H01L2176
CPC分类号： H01L21/76232 , Y10S148/05
摘要： Manufacturing a semiconductor device avoiding an increase of transistor leak current or reduction of the withstanding voltage characteristics is by at least one of: The pad oxide film is removed along the substrate surface from the upper edge of the groove over a distance ranging from 5 to 40 nm: The exposed surface of the semiconductor substrate undergoes removal by isotropic etching within 20 nm; and oxidizing a groove portion formed in a semiconductor substrate in an oxidation environment with a gas ratio of hydrogen (H2) to oxygen (O2) being less than or equal to 0.5, an increase of the curvature radius beyond 3nm is achieved without associating the risk of creation of any level difference on the substrate surface at or near the upper groove edge portions in a groove separation structure. This eliminates either an increase of transistor leak current or reduction of the withstanding voltage characteristics thereof otherwise occurring due to local electric field concentration near or around the terminate ends of a gate electrode film which in turn leads to an ability to improve electrical reliability of transistors used.
摘要翻译：制造半导体器件避免晶体管泄漏电流的增加或耐压特性的降低是至少以下之一：衬垫氧化膜沿着衬底表面从沟槽的上边缘移除5至40的距离 nm：通过各向同性蚀刻在20nm内去除半导体衬底的暴露表面; 并且在氧（H2）与氧气（O2）的气体比小于或等于0.5的氧化环境中氧化形成在半导体衬底中的沟槽部分，实现曲率半径超过3nm的增加，而不会使风险在槽分离结构中的上槽边缘部分处或附近在基板表面上产生任何水平差。这消除了晶体管泄漏电流的增加或由于栅极电极膜的端部附近或周围的局部电场浓度而导致的耐压特性的降低，这进而导致提高使用的晶体管的电可靠性的能力。

5. 发明授权

US6090684A Method for manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US6090684A
公开(公告)日：2000-07-18
申请号：US363184
申请日：1999-07-29
申请人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Yasuko Yoshida , Norio Suzuki , Masayuki Kojima , Kota Funayama
发明人： Norio Ishitsuka , Hideo Miura , Shuji Ikeda , Yasuko Yoshida , Norio Suzuki , Masayuki Kojima , Kota Funayama
IPC分类号： H01L21/76 , H01L21/762 , H01L29/78
CPC分类号： H01L21/76232 , Y10S148/05
摘要： A shallow groove isolation structure (SGI) electrically insulates adjoining transistors on a semiconductor substrate. A pad oxide film is formed on the semiconductor substrate and an oxidation inhibition film is formed on the pad oxide film. Parts of the oxide inhibition film and pad oxide film are removed to form the groove. In particular, the pad oxide film is removed from an upper edge of the groove within a range of 5 to 40 nm. A region of the groove is oxidized in an oxidation environment with a cast ratio of hydrogen (H.sub.2) to oxygen (O.sub.2) being less than or equal to 0.5. At this ratio, the oxidizing progresses under low stress at the upper groove edges of the substrate thereby enabling rounding of the upper groove edges without creating a level difference at or near the upper groove edge on the substrate surface.
摘要翻译：浅沟隔离结构（SGI）使半导体衬底上的相邻晶体管电绝缘。在半导体基板上形成衬垫氧化膜，在衬垫氧化膜上形成氧化抑制膜。除去氧化物抑制膜和垫氧化膜的一部分以形成槽。特别地，在5〜40nm的范围内，从槽的上边缘去除衬垫氧化膜。凹槽的区域在氢（H 2）与氧（O 2）的铸造比小于或等于0.5的氧化环境中被氧化。在该比例下，在基板的上槽边缘处的低应力下氧化进行，从而能够在上槽边缘的四舍五入，而不会在基板表面上的上槽边缘处或附近产生水平差。

6. 发明授权

US06562695B1 Semiconductor integrated circuit device and method of manufacturing involving the scale-down width of shallow groove isolation using round processing 有权
标题翻译：半导体集成电路器件及其制造方法涉及使用圆形加工的浅槽隔离的缩小宽度
公开(公告)号：US06562695B1
公开(公告)日：2003-05-13
申请号：US09889018
申请日：2001-07-10
申请人： Norio Suzuki , Hiroyuki Ichizoe , Masayuki Kojima , Keiji Okamoto , Shinichi Horibe , Kozo Watanabe , Yasuko Yoshida , Shuji Ikeda , Akira Takamatsu , Norio Ishitsuka , Atsushi Ogishima , Maki Shimoda
发明人： Norio Suzuki , Hiroyuki Ichizoe , Masayuki Kojima , Keiji Okamoto , Shinichi Horibe , Kozo Watanabe , Yasuko Yoshida , Shuji Ikeda , Akira Takamatsu , Norio Ishitsuka , Atsushi Ogishima , Maki Shimoda
IPC分类号： H01L2176
CPC分类号： H01L21/76229 , H01L21/76224 , H01L21/76232 , H01L27/10852 , H01L28/91
摘要： Grooves are defined in a substrate having device isolation regions by dry etching using silicon nitride films and side wall spacers as masks. Thereafter, the side wall spacers lying on side walls of the silicon nitride films are removed and the substrate is subjected to thermal oxidation, whereby the surface of the substrate at a peripheral portion of each active region is subjected to so-called round processing so as to have a sectional shape having a convex rounded shape.
摘要翻译：通过使用氮化硅膜和侧壁间隔物作为掩模的干蚀刻将沟槽限定在具有器件隔离区的衬底中。此后，除去位于氮化硅膜侧壁上的侧壁隔离物，并对衬底进行热氧化，由此在每个有源区的周边部分的衬底表面进行所谓的圆形处理，以便具有凸形圆形的截面形状。

7. 发明授权

US07397104B2 Semiconductor integrated circuit device and a method of manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US07397104B2
公开(公告)日：2008-07-08
申请号：US10778081
申请日：2004-02-17
申请人： Norio Suzuki , Hiroyuki Ichizoe , Masayuki Kojima , Keiji Okamoto , Shinichi Horibe , Kozo Watanabe , Yasuko Yoshida , Shuji Ikeda , Akira Takamatsu , Norio Ishitsuka , Atsushi Ogishima , Maki Shimoda
发明人： Norio Suzuki , Hiroyuki Ichizoe , Masayuki Kojima , Keiji Okamoto , Shinichi Horibe , Kozo Watanabe , Yasuko Yoshida , Shuji Ikeda , Akira Takamatsu , Norio Ishitsuka , Atsushi Ogishima , Maki Shimoda
IPC分类号： H01L21/00
CPC分类号： H01L21/76229 , H01L21/76224 , H01L21/76232 , H01L27/10852 , H01L28/91
摘要： A semiconductor integrated circuit device is provided which includes an active region, a shallow groove isolation adjacent to the active region, and a semiconductor element formed in the active region and having a gate. The sum of a width of the active region and a width of the shallow groove isolation constitutes a minimum pitch in the direction of a gate width of the gate, and the width of the active region is set larger than one-half of the minimum pitch.
摘要翻译：提供一种半导体集成电路器件，其包括有源区，与有源区相邻的浅槽隔离，以及形成在有源区中并具有栅极的半导体元件。有源区的宽度和浅槽隔离的宽度的和构成栅极的栅极宽度方向上的最小间距，并且有源区的宽度被设定为大于最小间距的一半。

8. 发明授权

US06720234B2 Semiconductor integrated circuit device and method of manufacturing involving the scale-down width of shallow groove isolation using round processing 有权
标题翻译：半导体集成电路器件及其制造方法涉及使用圆形加工的浅槽隔离的缩小宽度
公开(公告)号：US06720234B2
公开(公告)日：2004-04-13
申请号：US10366423
申请日：2003-02-14
申请人： Norio Suzuki , Hiroyuki Ichizoe , Masayuki Kojima , Keiji Okamoto , Shinichi Horibe , Kozo Watanabe , Yasuko Yoshida , Shuji Ikeda , Akira Takamatsu , Norio Ishitsuka , Atsushi Ogishima , Maki Shimoda
发明人： Norio Suzuki , Hiroyuki Ichizoe , Masayuki Kojima , Keiji Okamoto , Shinichi Horibe , Kozo Watanabe , Yasuko Yoshida , Shuji Ikeda , Akira Takamatsu , Norio Ishitsuka , Atsushi Ogishima , Maki Shimoda
IPC分类号： H01L2176
CPC分类号： H01L21/76229 , H01L21/76224 , H01L21/76232 , H01L27/10852 , H01L28/91
摘要： Grooves are defined in a substrate having device isolation regions by dry etching using silicon nitride films and side wall spacers as masks. Thereafter, the side wall spacers lying on side walls of the silicon nitride films are removed and the substrate is subjected to thermal oxidation, whereby the surface of the substrate at a peripheral portion of each active region is subjected to so-called round processing so as to have a sectional shape having a convex rounded shape.
摘要翻译：通过使用氮化硅膜和侧壁间隔物作为掩模的干蚀刻将沟槽限定在具有器件隔离区的衬底中。此后，除去位于氮化硅膜侧壁上的侧壁隔离物，并对衬底进行热氧化，由此在每个有源区的周边部分的衬底表面进行所谓的圆形处理，以便具有凸形圆形的截面形状。

9. 发明申请

US20060128094A1 Semiconductor integrated circuit device and method of manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US20060128094A1
公开(公告)日：2006-06-15
申请号：US11342695
申请日：2006-01-31
申请人： Akio Nishida , Yasuko Yoshida , Shuji Ikeda
发明人： Akio Nishida , Yasuko Yoshida , Shuji Ikeda
IPC分类号： H01L21/8242
CPC分类号： H01L27/11 , H01L27/1104
摘要： In order to provide a semiconductor integrated circuit device such as a high-performance semiconductor integrated circuit device capable of reducing a soft error developed in each memory cell of a SRAM, the surface of a wiring of a cross-connecting portion, of a SRAM memory cell having a pair of n-channel type MISFETs whose gate electrodes and drains are respectively cross-connected, is formed in a shape that protrudes from the surface of a silicon oxide film. A silicon nitride film used as a capacitive insulating film, and an upper electrode are formed on the wiring. A capacitance can be formed of the wiring, the silicon nitride film and the upper electrode.
摘要翻译：为了提供一种半导体集成电路器件，例如能够减少在SRAM的每个存储单元中产生的软错误的高性能半导体集成电路器件，SRAM存储器的交叉连接部分的布线表面其栅电极和漏极分别交叉连接的一对n沟道型MISFET形成为从氧化硅膜的表面突出的形状。在布线上形成用作电容绝缘膜的氮化硅膜和上电极。电容可以由布线，氮化硅膜和上电极形成。

10. 发明授权

US5880497A Semiconductor integrated circuit device having capacitance element and process of manufacturing the same 失效
标题翻译：具有电容元件的半导体集成电路器件及其制造方法
公开(公告)号：US5880497A
公开(公告)日：1999-03-09
申请号：US592235
申请日：1996-01-26
申请人： Shuji Ikeda , Koichi Imato , Kazuo Yoshizaki , Kohji Yamasaki , Soichiro Hashiba , Keiichi Yoshizumi , Yasuko Yoshida , Kousuke Okuyama , Mitsugu Oshima , Kazushi Tomita , Tsuyoshi Tabata , Kazushi Fukuda , Junichi Takano , Toshiaki Yamanaka , Chiemi Hashimoto , Motoko Kawashima , Fumiyuki Kanai , Takashi Hashimoto
发明人： Shuji Ikeda , Koichi Imato , Kazuo Yoshizaki , Kohji Yamasaki , Soichiro Hashiba , Keiichi Yoshizumi , Yasuko Yoshida , Kousuke Okuyama , Mitsugu Oshima , Kazushi Tomita , Tsuyoshi Tabata , Kazushi Fukuda , Junichi Takano , Toshiaki Yamanaka , Chiemi Hashimoto , Motoko Kawashima , Fumiyuki Kanai , Takashi Hashimoto
IPC分类号： H01L27/11
CPC分类号： H01L27/1108 , Y10S257/903 , Y10S257/904
摘要： A SRAM having its memory cell constructed to include transfer MISFETs to be controlled by word lines and a flip-flop circuit having driver MISFETs and load MISFETs. Plate electrodes of large area fixed on predetermined power source lines are arranged over the load MISFETs such that the plate electrodes over the offset region of the load MISFETs are formed with an opening. A silicon nitride film having a thickness permeable to hydrogen but not to humidity is formed over the transfer MISFETs and the driver MISFETs formed over the main surface of a semiconductor substrate and the load MISFETs formed of a polycrystalline silicon film deposited on the driver MISFETs.
摘要翻译：其存储单元被构造成包括由字线控制的转移MISFET和具有驱动器MISFET和负载MISFET的触发器电路的SRAM。固定在预定电源线上的大面积平板电极布置在负载MISFET上，使得负载MISFET的偏移区域上的平板电极形成开口。在半导体衬底的主表面上形成的转移MISFET和驱动器MISFET上形成具有可渗透氢而不湿度的氮化硅膜，以及沉积在驱动器MISFET上的多晶硅膜形成的负载MISFET。

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