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1. 发明授权

US08711607B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08711607B2
公开(公告)日：2014-04-29
申请号：US13110068
申请日：2011-05-18
申请人： Masanao Yamaoka , Koichiro Ishibashi , Shigezumi Matsui , Kenichi Osada
发明人： Masanao Yamaoka , Koichiro Ishibashi , Shigezumi Matsui , Kenichi Osada
IPC分类号： G11C11/00
CPC分类号： G11C11/419 , G11C5/146 , G11C5/147 , G11C11/4125 , G11C11/417 , G11C2207/2227
摘要： A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.
摘要翻译：系统LSI中的逻辑电路设置有电源开关，以便在待机时切断开关，从而减少漏电流。同时，系统LSI的SRAM电路控制衬底偏置以减少漏电流。

2. 发明授权

US08482083B2 Semiconductor integrated circuit device including SRAM memory cells having two P-channel MOS transistors and four N-channel MOS transistors and with four wiring layers serving as their gate electrodes 有权
标题翻译：半导体集成电路器件包括具有两个P沟道MOS晶体管和四个N沟道MOS晶体管以及四个布线层作为其栅电极的SRAM存储单元
公开(公告)号：US08482083B2
公开(公告)日：2013-07-09
申请号：US12821329
申请日：2010-06-23
申请人： Kenichi Osada , Masataka Minami , Shuji Ikeda , Koichiro Ishibashi
发明人： Kenichi Osada , Masataka Minami , Shuji Ikeda , Koichiro Ishibashi
IPC分类号： H01L29/76 , H01L27/11
CPC分类号： H01L27/1104 , G11C11/412 , G11C11/417 , H01L27/11 , H01L29/4916 , H01L29/783 , Y10S257/904
摘要： Prior known static random access memory (SRAM) cells required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supply power to the substrate are formed in parallel to word lines in such a manner that one region is provided per group of thirty two memory cell rows or sixty four cell rows.
摘要翻译：现有已知的静态随机存取存储器（SRAM）单元需要将扩散层弯曲成键状形状，以便与其中形成有P型阱区的衬底电接触，这将导致不对称性的降低导致出现微图案化困难的问题。为了避免这个问题，构成SRAM单元的逆变器的P型阱区被细分成两部分，它们设置在N型阱区NW1的相对侧上，并形成为扩散形成晶体管的层没有曲率，同时使得布局方向在平行于阱边界线和位线的方向上运行。在阵列的中间位置处，用于向衬底供电的区域形成为平行于字线，以这样的方式，每组三十二个存储单元行或六十六个单元行提供一个区域。

3. 发明授权

US07781846B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07781846B2
公开(公告)日：2010-08-24
申请号：US12348524
申请日：2009-01-05
申请人： Kenichi Osada , Masataka Minami , Shuji Ikeda , Koichiro Ishibashi
发明人： Kenichi Osada , Masataka Minami , Shuji Ikeda , Koichiro Ishibashi
IPC分类号： H01L29/76 , H01L27/11
CPC分类号： H01L27/1104 , G11C11/412 , G11C11/417 , H01L27/11 , H01L29/4916 , H01L29/783 , Y10S257/904
摘要： Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.
摘要翻译：现有的已知的静态随机存取存储器（SRAM）单元需要将扩散层弯曲成键状形状，以便与其中形成有P型阱区的衬底进行电接触，这将导致不对称性导致了微图案化困难的问题的发生。为了避免这个问题，构成SRAM单元的逆变器的P型阱区被细分成两部分，它们设置在N型阱区NW1的相对侧上，并形成为扩散形成晶体管的层没有曲率，同时使得布局方向在平行于阱边界线和位线的方向上运行。在阵列的中间位置处，以与字线平行的方式形成用于向基板供电的区域，以每组三十二个存储单元行或六十四个单元行提供一个区域。

4. 发明授权

US07646662B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07646662B2
公开(公告)日：2010-01-12
申请号：US12325783
申请日：2008-12-01
申请人： Masanao Yamaoka , Koichiro Ishibashi , Shigezumi Matsui , Kenichi Osada
发明人： Masanao Yamaoka , Koichiro Ishibashi , Shigezumi Matsui , Kenichi Osada
IPC分类号： G11C5/14
CPC分类号： G11C11/419 , G11C5/146 , G11C5/147 , G11C11/4125 , G11C11/417 , G11C2207/2227
摘要： A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.
摘要翻译：系统LSI中的逻辑电路具有电源开关，以便在待机时切断开关，从而减少漏电流。同时，系统LSI的SRAM电路控制衬底偏置以减少漏电流。

5. 发明授权

US07569881B2 Semiconductor integrated circuit device with reduced leakage current 有权
公开(公告)号：US07569881B2
公开(公告)日：2009-08-04
申请号：US12078992
申请日：2008-04-09
申请人： Kenichi Osada , Koichiro Ishibashi , Yoshikazu Saitoh , Akio Nishida , Masaru Nakamichi , Naoki Kitai
发明人： Kenichi Osada , Koichiro Ishibashi , Yoshikazu Saitoh , Akio Nishida , Masaru Nakamichi , Naoki Kitai
IPC分类号： H01L29/788 , H01L21/8242
CPC分类号： G11C11/412 , G11C11/40 , G11C11/413 , G11C11/418 , H01L21/823475 , H01L21/823493 , H01L21/823814 , H01L21/82385 , H01L27/088 , H01L27/092 , H01L27/105 , H01L27/1052 , H01L27/11 , H01L27/1104 , H01L27/1116 , H03K19/0016
摘要： The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

6. 发明申请

US20090010042A1 Semiconductor integrated circuit device 有权
公开(公告)号：US20090010042A1
公开(公告)日：2009-01-08
申请号：US12216716
申请日：2008-07-10
申请人： Koichiro Ishibashi , Kenichi Osada
发明人： Koichiro Ishibashi , Kenichi Osada
IPC分类号： G11C11/34
CPC分类号： G11C11/404 , G11C11/412 , G11C11/419 , G11C2207/104 , H01L21/823807 , H01L21/823857 , H01L27/0922 , H01L27/1052 , H01L27/10873 , H01L27/10894 , H01L27/11 , H01L27/1104 , Y10S257/903
摘要： In an integrated circuit device, there are various optimum gate lengths, thickness of gate oxide films, and threshold voltages according to the characteristics of circuits. In a semiconductor integrated circuit device in which the circuits are integrated on the same substrate, the manufacturing process is complicated in order to set the circuits to the optimum values. As a result, in association with deterioration in the yield and increase in the number of manufacturing days, the manufacturing cost increases. In order to solve the problems, according to the invention, transistors of high and low thresholds are used in a logic circuit, a memory cell uses a transistor of the same high threshold voltage and a low threshold voltage transistor, and an input/output circuit uses a transistor having the same high threshold voltage and the same concentration in a channel, and a thicker gate oxide film.

7. 发明申请

US20080247220A1 SEMICONDUCTOR MEMORY DEVICE WITH MEMORY CELLS OPERATED BY BOOSTED VOLTAGE 有权
标题翻译：具有由升压电压操作的存储器电池的半导体存储器件
公开(公告)号：US20080247220A1
公开(公告)日：2008-10-09
申请号：US12133343
申请日：2008-06-04
申请人： Masanao Yamaoka , Kenichi Osada , Koichiro Ishibashi
发明人： Masanao Yamaoka , Kenichi Osada , Koichiro Ishibashi
IPC分类号： G11C11/00
CPC分类号： G11C11/417 , G11C11/412 , Y10S257/903
摘要： A memory using an SRAM memory cell intended for low-voltage operation is designed to decrease the threshold value of MOS transistors constituting the memory cell without substantial decrease in the static noise margin, which is the operational margin of the memory cell. To this end, a voltage Vdd′ higher than a power supply voltage Vdd of a power supply line for peripheral circuits is supplied from a power supply line for memory cells as a power supply voltage for memory cells. Since the conductance of driver MOS transistors is in-creased, the threshold voltage of the MOS transistors within the memory cells can be reduced without reducing the static noise margin. Further the ratio of width between the driver MOS transistor and a transfer MOS transistor can be set to 1, thereby allowing a reduction in the memory cell area.
摘要翻译：使用用于低电压操作的SRAM存储单元的存储器被设计为降低构成存储器单元的MOS晶体管的阈值，而不会显着降低静态噪声容限，这是存储单元的操作余量。为此，作为存储单元的电源电压，从用于存储单元的电源线提供高于外围电路用电源线的电源电压Vdd的电压Vdd'。由于驱动器MOS晶体管的电导被增加，所以可以在不降低静态噪声容限的情况下减小存储单元内的MOS晶体管的阈值电压。此外，可以将驱动器MOS晶体管和转移MOS晶体管之间的宽度比设置为1，从而允许存储单元区域的减小。

8. 发明授权

US07406643B2 Semiconductor integrated circuit device, method of manufacturing the device, and computer readable medium 失效
标题翻译：半导体集成电路器件，该器件的制造方法以及计算机可读介质
公开(公告)号：US07406643B2
公开(公告)日：2008-07-29
申请号：US10860051
申请日：2004-06-04
申请人： Kenichi Osada , Koichiro Ishibashi , Kazuo Yano , Tetsuro Honmura
发明人： Kenichi Osada , Koichiro Ishibashi , Kazuo Yano , Tetsuro Honmura
IPC分类号： G01R31/28 , G11C7/00
CPC分类号： G11C29/028 , G11C15/00 , G11C29/50 , G11C29/50012 , G11C2029/0403
摘要： A semiconductor integrated circuit device which guarantees the characteristics of writing to and reading from the built-in memory even when the manufacturing process conditions are varied, a method of manufacturing the device, and a medium for storing a processing procedure for deciding the number of delay circuits built in the device used for designing. The semiconductor integrated circuit device is provided with a cache memory which includes a BIST circuit composed of a pattern generator, a pattern comparator, an output register, a register controlled by a register control a register write signal; a variable delay circuit controlled by the register; word lines, and a sense amplifier enable signal line. The timing for enabling the sense amplifier is changed and the memory is measured by a BIST circuit at the timing, thereby deciding the optimal timing.
摘要翻译：一种半导体集成电路器件，即使在制造工艺条件变化时也保证写入和读取内部存储器的特性，制造器件的方法以及用于存储用于确定延迟次数的处理过程的介质电路内置在用于设计的设备中。半导体集成电路器件具有高速缓冲存储器，其包括由模式发生器，模式比较器，输出寄存器，由寄存器控制的寄存器控制寄存器写入信号组成的BIST电路; 由寄存器控制的可变延迟电路; 字线和读出放大器使能信号线。改变启用读出放大器的定时，并且通过BIST电路在定时测量存储器，由此决定最佳定时。

9. 发明申请

US20070286001A1 Semiconductor integrated circuit with memory redundancy circuit 有权
公开(公告)号：US20070286001A1
公开(公告)日：2007-12-13
申请号：US11783123
申请日：2007-04-06
申请人： Kenichi Osada , Koichiro Ishibashi , Yoshikazu Saitou , Masashige Harada , Takehiko Kijima
发明人： Kenichi Osada , Koichiro Ishibashi , Yoshikazu Saitou , Masashige Harada , Takehiko Kijima
IPC分类号： G11C7/00
CPC分类号： G06F11/1008 , G11C29/848
摘要： A semiconductor integrated circuit with memory redundancy circuit to address the problems of increased area, power consumption and access time which is caused by using an ECC circuit for error correction. The circuit comprises: a plurality of memory mats; a local bus, parallel to word lines, which transfers read data and write data from memory cells; a global bus for writing, parallel to data lines, which transfers write data from an input pad IO; a global bus for reading, parallel to data lines, which transfers read data to an output pad IO; and at least one error correction circuit located at an intersection of the global buses and the local bus. Reading and writing may each be completed in a single cycle, and during a write operation, data which is different from data previously read is written. By this configuration, an increase in area and power consumption can be avoided and errors such as soft errors can be corrected.

10. 发明授权

US07219272B2 Semiconductor integrated circuit with memory redundancy circuit 有权
标题翻译：半导体集成电路与存储器冗余电路
公开(公告)号：US07219272B2
公开(公告)日：2007-05-15
申请号：US10170583
申请日：2002-06-14
申请人： Kenichi Osada , Koichiro Ishibashi , Yoshikazu Saitou , Masashige Harada , Takehiko Kijima
发明人： Kenichi Osada , Koichiro Ishibashi , Yoshikazu Saitou , Masashige Harada , Takehiko Kijima
IPC分类号： G11C29/00 , G06F11/00 , G11C7/00
CPC分类号： G06F11/1008 , G11C29/848
摘要： A semiconductor integrated circuit with memory redundancy circuit to address the problems of increased area, power consumption and access time which is caused by using an ECC circuit for error correction. The circuit comprises: a plurality of memory mats; a local bus, parallel to word lines, which transfers read data and write data from memory cells; a global bus for writing, parallel to data lines, which transfers write data from an input pad IO; a global bus for reading, parallel to data lines, which transfers read data to an output pad IO; and at least one error correction circuit located at an intersection of the global buses and the local bus. Reading and writing may each be completed in a single cycle, and during a write operation, data which is different from data previously read is written. By this configuration, an increase in area and power consumption can be avoided and errors such as soft errors can be corrected.
摘要翻译：一种具有存储器冗余电路的半导体集成电路，用于解决由使用ECC电路进行纠错引起的增加的面积，功耗和访问时间的问题。该电路包括：多个存储垫; 平行于字线的本地总线，其传送读取数据并从存储器单元写入数据; 与数据线并行的写入全局总线，其从输入焊盘IO传送写入数据; 用于读取数据线的全局总线，其将读取的数据传送到输出焊盘IO; 以及位于全局总线和本地总线的交叉点处的至少一个纠错电路。读取和写入可以在单个周期中完成，并且在写入操作期间，写入与先前读取的数据不同的数据。通过这种配置，可以避免面积和功耗的增加，并且可以校正诸如软错误的错误。

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