专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06559006B2 Semiconductor integrated circuit and method for manufacturing the same 有权
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US06559006B2
公开(公告)日：2003-05-06
申请号：US10157978
申请日：2002-05-31
申请人： Shuji Ikeda , Yasuko Yoshida , Masayuki Kojima , Kenji Shiozawa , Mitsuyuki Kimura , Norio Nakagawa , Koichiro Ishibashi , Yasuhisa Shimazaki , Kenichi Osada , Kunio Uchiyama
发明人： Shuji Ikeda , Yasuko Yoshida , Masayuki Kojima , Kenji Shiozawa , Mitsuyuki Kimura , Norio Nakagawa , Koichiro Ishibashi , Yasuhisa Shimazaki , Kenichi Osada , Kunio Uchiyama
IPC分类号： H01L218242
CPC分类号： H01L27/105 , H01L27/1052
摘要： An operational margin of a memory of a semiconductor integrated circuit device including an SRAM is improved. In order to set the Vth of driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance QL forming memory cells of an SRAM, relatively and intentionally higher than the Vth of predetermined MISFETs of SRAM peripheral circuits and logic circuits such as microprocessor, an impurity introduction step is introduced to set the Vth of the driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance, separately from an impurity introduction step for setting the Vth of the predetermined MISFETs.
摘要翻译：提高了包括SRAM的半导体集成电路器件的存储器的操作裕度。为了设置驱动MISFET Qd的Vth，传输用于形成SRAM的存储单元的负载电阻QL的MISFET Qt和MISFET相对有意地高于SRAM外围电路和诸如微处理器的逻辑电路的预定MISFET的Vth，杂质介绍引入步骤，用于设置驱动MISFET Qd的Vth，用于负载电阻的传输MISFET Qt和MISFET，与用于设置预定MISFET的Vth的杂质引入步骤分开。

2. 发明授权

US06436753B1 Semiconductor integrated circuit and method for manufacturing the same 有权
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US06436753B1
公开(公告)日：2002-08-20
申请号：US09372007
申请日：1999-08-11
申请人： Shuji Ikeda , Yasuko Yoshida , Masayuki Kojima , Kenji Shiozawa , Mitsuyuki Kimura , Norio Nakagawa , Koichiro Ishibashi , Yasuhisa Shimazaki , Kenichi Osada , Kunio Uchiyama
发明人： Shuji Ikeda , Yasuko Yoshida , Masayuki Kojima , Kenji Shiozawa , Mitsuyuki Kimura , Norio Nakagawa , Koichiro Ishibashi , Yasuhisa Shimazaki , Kenichi Osada , Kunio Uchiyama
IPC分类号： H01L218244
CPC分类号： H01L27/105 , H01L27/1052
摘要： An operational margin of a memory of a semiconductor integrated circuit device including an SRAM is improved. In order to set the Vth of driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance QL forming memory cells of an SRAM, relatively and intentionally higher than the Vth of predetermined MISFETs of SRAM peripheral circuits and logic circuits, such as a microprocessor, an impurity introduction step is introduced to set the Vth of the driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance, separately from an impurity introduction step for setting the Vth of the predetermined MISFETs.
摘要翻译：提高了包括SRAM的半导体集成电路器件的存储器的操作裕度。为了设置驱动MISFET Qd的Vth，对于形成SRAM的存储单元的负载电阻QL的转移MISFET Qt和MISFET相对有意地高于诸如微处理器的SRAM外围电路和逻辑电路的预定MISFET的Vth，引入杂质引入步骤，用于设置用于设置预定MISFET的Vth的杂质引入步骤的驱动MISFET Qd，负载电阻的转移MISFET Qt和MISFET的Vth。

3. 发明授权

US06753231B2 Semiconductor integrated circuit and method for manufacturing the same 有权
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US06753231B2
公开(公告)日：2004-06-22
申请号：US10379543
申请日：2003-03-06
申请人： Shuji Ikeda , Yasuko Yoshida , Masayuki Kojima , Kenji Shiozawa , Mitsuyuki Kimura , Norio Nakagawa , Koichiro Ishibashi , Yasuhisa Shimazaki , Kenichi Osada , Kunio Uchiyama
发明人： Shuji Ikeda , Yasuko Yoshida , Masayuki Kojima , Kenji Shiozawa , Mitsuyuki Kimura , Norio Nakagawa , Koichiro Ishibashi , Yasuhisa Shimazaki , Kenichi Osada , Kunio Uchiyama
IPC分类号： H01L21336
CPC分类号： H01L27/105 , H01L27/1052
摘要： An operational margin of a memory of a semiconductor integrated circuit device including an SRAM is improved. In order to set the Vth of driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance QL forming memory cells of an SRAM, relatively and intentionally higher than the Vth of predetermined MISFETs of SRAM peripheral circuits and logic circuits such as microprocessor, an impurity introduction step is introduced to set the Vth of the driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance, separately from an impurity introduction step for setting the Vth of the predetermined MISFETs.
摘要翻译：提高了包括SRAM的半导体集成电路器件的存储器的操作裕度。为了设置驱动MISFET Qd的Vth，传输用于形成SRAM的存储单元的负载电阻QL的MISFET Qt和MISFET相对有意地高于SRAM外围电路和诸如微处理器的逻辑电路的预定MISFET的Vth，杂质介绍引入步骤，用于设置驱动MISFET Qd的Vth，用于负载电阻的传输MISFET Qt和MISFET，与用于设置预定MISFET的Vth的杂质引入步骤分开。

4. 发明授权

US06772327B2 Floating point unit pipeline synchronized with processor pipeline 失效
公开(公告)号：US06772327B2
公开(公告)日：2004-08-03
申请号：US10143230
申请日：2002-05-09
申请人： Prasenjit Biswas , Gautam Dewan , Kevin Iadonato , Norio Nakagawa , Kunio Uchiyama
发明人： Prasenjit Biswas , Gautam Dewan , Kevin Iadonato , Norio Nakagawa , Kunio Uchiyama
IPC分类号： G06F938
CPC分类号： G06F9/3885 , G06F9/30149 , G06F9/3861
摘要： An FPU pipeline is synchronized with a CPU pipeline. Synchronization is achieved by having stalls and freezes in any one pipeline cause stalls and freezes in the other pipeline as well. Exceptions are kept precise even for long floating point operations. Precise exceptions are achieved by having a first execution stage of the FPU pipeline generate a busy signal, when a first floating point instruction enters a first execution stage of the FPU pipeline. When a second floating point instruction is decoded by the FPU pipeline before the first floating point instruction has finished executing in the first stage of the FPU pipeline, then both pipelines are stalled.

5. 发明授权

US06418528B1 Floating point unit pipeline synchronized with processor pipeline 失效
公开(公告)号：US06418528B1
公开(公告)日：2002-07-09
申请号：US09131881
申请日：1998-08-10
申请人： Prasenjit Biswas , Gautam Dewan , Kevin Iadonato , Norio Nakagawa , Kunio Uchiyama
发明人： Prasenjit Biswas , Gautam Dewan , Kevin Iadonato , Norio Nakagawa , Kunio Uchiyama
IPC分类号： G06F9302
CPC分类号： G06F9/3885 , G06F9/30149 , G06F9/3861
摘要： An FPU pipeline is synchronized with a CPU pipeline. Synchronization is achieved by having stalls and freezes in any one pipeline cause stalls and freezes in the other pipeline as well. Exceptions are kept precise even for long floating point operations. Precise exceptions are achieved by having a first execution stage of the FPU pipeline generate a busy signal, when a first floating point instruction enters a first execution stage of the FPU pipeline. When a second floating point instruction is decoded by the FPU pipeline before the first floating point instruction has finished executing in the first stage of the FPU pipeline, then both pipelines are stalled.

6. 发明授权

US5860000A Floating point unit pipeline synchronized with processor pipeline 失效
公开(公告)号：US5860000A
公开(公告)日：1999-01-12
申请号：US594763
申请日：1996-01-31
申请人： Prasenjit Biswas , Gautam Dewan , Kevin Iadonato , Norio Nakagawa , Kunio Uchiyama
发明人： Prasenjit Biswas , Gautam Dewan , Kevin Iadonato , Norio Nakagawa , Kunio Uchiyama
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3885 , G06F9/30149 , G06F9/3861
摘要： An FPU pipeline is synchronized with a CPU pipeline. Synchronization is achieved by having stalls and freezes in any one pipeline cause stalls and freezes in the other pipeline as well. Exceptions are kept precise even for long floating point operations. Precise exceptions are achieved by having a first execution stage of the FPU pipeline generate a busy signal, when a first floating point instruction enters a first execution stage of the FPU pipeline. When a second floating point instruction is decoded by the FPU pipeline before the first floating point instruction has finished executing in the first stage of the FPU pipeline, then both pipelines are stalled.

7. 发明授权

US07162616B2 Floating point unit pipeline synchronized with processor pipeline 有权
标题翻译：浮点单元管线与处理器管线同步
公开(公告)号：US07162616B2
公开(公告)日：2007-01-09
申请号：US10796552
申请日：2004-03-08
申请人： Prasenjit Biswas , Gautam Dewan , Kevin Iadonato , Norio Nakagawa , Kunio Uchiyama
发明人： Prasenjit Biswas , Gautam Dewan , Kevin Iadonato , Norio Nakagawa , Kunio Uchiyama
IPC分类号： G06F9/312
CPC分类号： G06F9/3885 , G06F9/30149 , G06F9/3861
摘要： An FPU pipeline is synchronized with a CPU pipeline. Synchronization is achieved by having stalls and freezes in any one pipeline cause stalls and freezes in the other pipeline as well. Exceptions are kept precise even for long floating point operations. Precise exceptions are achieved by having a first execution stage of the FPU pipeline generate a busy signal, when a first floating point instruction enters a first execution stage of the FPU pipeline. When a second floating point instruction is decoded by the FPU pipeline before the first floating point instruction has finished executing in the first stage of the FPU pipeline, then both pipelines are stalled.
摘要翻译： FPU流水线与CPU流水线同步。通过在任何一个管道中进行停顿和冻结来实现同步，从而在另一个管道中停顿并冻结。即使长时间浮点运算，异常也保持精确。当第一个浮点指令进入FPU流水线的第一个执行阶段时，通过使FPU流水线的第一个执行阶段产生一个忙信号来实现精确的例外。当第一个浮点指令在FPU流水线的第一阶段完成执行之前，FPU流水线进行第二个浮点指令解码时，两条流水线停顿。

8. 发明授权

US6012139A Microprocessor including floating point unit with 16-bit fixed length instruction set 失效
标题翻译：微处理器包括具有16位固定长度指令集的浮点单元
公开(公告)号：US6012139A
公开(公告)日：2000-01-04
申请号：US594750
申请日：1996-01-31
申请人： Prasenjit Biswas , Shumpei Kawasaki , Norio Nakagawa , Osamu Nishii , Kunio Uchiyama
发明人： Prasenjit Biswas , Shumpei Kawasaki , Norio Nakagawa , Osamu Nishii , Kunio Uchiyama
IPC分类号： G06F7/00 , G06F7/487 , G06F7/76 , G06F9/30 , G06F9/302 , G06F9/38
CPC分类号： G06F9/30014 , G06F9/30167 , G06F9/3867 , G06F9/3877
摘要： A Floating Point Unit (FPU) with a sixteen-bit fixed length instruction set for thirty-two bit data. The FPU operates as part of RISC microprocessor. The CPU does all memory addressing. Furthermore, data between the CPU and the FPU is transferred via a communication register. An FPU pipeline is synchronized with a CPU pipeline. The sixteen-bit fixed length instruction group has special instructions for immediate loading of a floating point zero and/or a floating point one. Two instructions are dedicated for this purpose. Furthermore, the 16-bit fixed length instruction group of the FPU flushes denormalized numbers to zero. The instruction set also rounds floating point numbers to zero. An FMAC instruction of the instruction set has the capability to accumulate into a different register for consecutive FMAC operations.
摘要翻译：具有16位固定长度指令集的浮点单元（FPU），用于32位数据。 FPU作为RISC微处理器的一部分运行。 CPU执行所有内存寻址。此外，通过通信寄存器传送CPU和FPU之间的数据。 FPU流水线与CPU流水线同步。 16位固定长度指令组具有用于立即加载浮点零点和/或浮点数指令的特殊指令。为此目的有两个指示。此外，FPU的16位固定长度指令组将非规格化数字刷新为零。指令集也将浮点数转换为零。指令集的FMAC指令具有累积到不同寄存器中以进行连续FMAC操作的能力。

9. 发明授权

US08038298B2 Projector device 有权
标题翻译：投影机设备
公开(公告)号：US08038298B2
公开(公告)日：2011-10-18
申请号：US11488132
申请日：2006-07-18
申请人： Norio Nakagawa , Toshihiro Saruwatari
发明人： Norio Nakagawa , Toshihiro Saruwatari
IPC分类号： G02B21/14 , G02F1/1335
CPC分类号： G03B21/16 , G03B21/14 , G03B21/2073 , H04N9/3105 , H04N9/3167
摘要： A liquid crystal projector device of the present invention includes an optical system for receiving light from a lamp unit. The optical system is provided with a polarization beam splitter for extracting only an S wave out of P and S waves of the light emitted from the lamp unit, and also provided with a latter stage slit plate in contact with a light incidence surface of the polarization beam splitter. The latter stage slit plate is provided with a plurality of slits for allowing light incidence on the polarization beam splitter. A former stage slit plate is arranged in a position spaced apart from the latter stage slit plate along the optical axis toward the lamp unit. The former stage slit plate is provided with a plurality of slits overlapping in the optical axis direction with the respective slits of the latter stage slit plate.
摘要翻译：本发明的液晶投影仪装置包括用于接收来自灯单元的光的光学系统。光学系统设置有偏振分束器，用于从灯单元发射的光中仅提取P波和S波中的S波，并且还设置有与偏振的光入射表面接触的后级狭缝板分束器。后段狭缝板设置有多个狭缝，用于允许光入射到偏振分束器上。前级狭缝板沿着光轴朝向灯单元布置在与后级狭缝板间隔开的位置。前一级狭缝板具有在光轴方向上与后级狭缝板的各狭缝重叠的多个狭缝。

10. 发明授权

US07795863B2 Method and apparatus for forming coil for use in eddy current sensing probe 有权
标题翻译：用于形成用于涡流感应探头的线圈的方法和装置
公开(公告)号：US07795863B2
公开(公告)日：2010-09-14
申请号：US11064325
申请日：2005-02-23
申请人： Marcus James Johnson , Norio Nakagawa
发明人： Marcus James Johnson , Norio Nakagawa
IPC分类号： G01N27/90
CPC分类号： G01N27/9006
摘要： A coil for use in an eddy current sensing probe is formed through depositing film traces. The film traces can be directly deposited. The film traces can be deposited on the outer surface of a core or on ends of the core. The film traces can be deposited onto non-planar surfaces other than cores for the inspection of parts having complex geometries. The coil can be used in a single coil probe or in a probe having a sensor array.
摘要翻译：通过沉积薄膜迹线形成用于涡流感测探针的线圈。胶片痕迹可以直接沉积。薄膜迹线可以沉积在芯的外表面或芯的端部上。膜迹线可以沉积到除芯之外的非平面表面上，以检查具有复杂几何形状的部件。线圈可用于单个线圈探头或具有传感器阵列的探头中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式