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41. 发明授权

US07540935B2 Plasma oxidation and removal of oxidized material 失效
标题翻译：氧化物质的等离子体氧化和去除
公开(公告)号：US07540935B2
公开(公告)日：2009-06-02
申请号：US11076725
申请日：2005-03-09
申请人： Yunsang Kim , Andrew D. Bailey, III , Hyungsuk Alexander Yoon , Arthur M. Howald
发明人： Yunsang Kim , Andrew D. Bailey, III , Hyungsuk Alexander Yoon , Arthur M. Howald
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/32136 , H01L21/31683 , H01L21/321 , H01L21/32115 , H01L21/32135 , H01L21/32138 , H01L21/32139 , H01L21/7684 , H01L21/76865 , H01L21/76885
摘要： A method of etching a conductive layer includes converting at least a portion of the conductive layer and etching the conductive layer to substantially remove the converted portion of the conductive layer and thereby expose a remaining surface. The remaining surface has an average surface roughness of less than about 10 nm. A system for etching a conductive layer is also disclosed.
摘要翻译：蚀刻导电层的方法包括转换导电层的至少一部分并蚀刻导电层，以基本上去除导电层的转换部分，从而暴露出剩余的表面。剩余的表面具有小于约10nm的平均表面粗糙度。还公开了用于蚀刻导电层的系统。

42. 发明申请

US20080145998A1 METHOD OF FORMING A LOW-K DUAL DAMASCENE INTERCONNECT STRUCTURE 失效
标题翻译：形成低K双重DAMASCENE互连结构的方法
公开(公告)号：US20080145998A1
公开(公告)日：2008-06-19
申请号：US11531493
申请日：2006-09-13
申请人： GERARDO A. DELGADINO , Yan Ye , Neungho Shin , Yunsang Kim , Li-Qun Xia , Tzu-Fang Huang , Lihua Li Huang , Joey Chiu , Xiaoye Zhao , Fang Tian , Wen Zhu , Ellie Yieh
发明人： GERARDO A. DELGADINO , Yan Ye , Neungho Shin , Yunsang Kim , Li-Qun Xia , Tzu-Fang Huang , Lihua Li Huang , Joey Chiu , Xiaoye Zhao , Fang Tian , Wen Zhu , Ellie Yieh
IPC分类号： H01L21/76
CPC分类号： H01L21/76826 , H01L21/76811 , H01L21/76813
摘要： A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.
摘要翻译：一种制造互连结构的方法，包括将通孔蚀刻到上部低K电介质层中并进入下部低K电介质层的硬化部分。通孔由形成在光致抗蚀剂层中的图案限定。然后剥离光致抗蚀剂层，并且将由硬掩模限定的通孔的沟槽蚀刻到上部低K电介质层中，并且同时蚀刻到下部低K电介质层的硬化部分中的通孔是进一步蚀刻到下部低K介电层中。结果是低K电介质双镶嵌结构。

43. 发明授权

US07132369B2 Method of forming a low-K dual damascene interconnect structure 失效
标题翻译：形成低K双镶嵌互连结构的方法
公开(公告)号：US07132369B2
公开(公告)日：2006-11-07
申请号：US10745344
申请日：2003-12-22
申请人： Gerardo A. Delgadino , Yan Ye , Neungho Shin , Yunsang Kim , Li-Qun Xia , Tzu-Fang Huang , Lihua Li , Joey Chiu , Xiaoye Zhao , Fang Tian , Wen Zhu , Ellie Yieh
发明人： Gerardo A. Delgadino , Yan Ye , Neungho Shin , Yunsang Kim , Li-Qun Xia , Tzu-Fang Huang , Lihua Li , Joey Chiu , Xiaoye Zhao , Fang Tian , Wen Zhu , Ellie Yieh
IPC分类号： H01L21/302
CPC分类号： H01L21/76826 , H01L21/76811 , H01L21/76813
摘要： A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.
摘要翻译：一种制造互连结构的方法，包括将通孔蚀刻到上部低K电介质层中并进入下部低K电介质层的硬化部分。通孔由形成在光致抗蚀剂层中的图案限定。然后剥离光致抗蚀剂层，并且将由硬掩模限定的通孔的沟槽蚀刻到上部低K电介质层中，并且同时蚀刻到下部低K电介质层的硬化部分中的通孔为进一步蚀刻到下部低K介电层中。结果是低K电介质双镶嵌结构。

44. 发明授权

US09184043B2 Edge electrodes with dielectric covers 有权
标题翻译：带电介质盖的边缘电极
公开(公告)号：US09184043B2
公开(公告)日：2015-11-10
申请号：US11758584
申请日：2007-06-05
申请人： Gregory S. Sexton , Andrew D. Bailey, III , Andras Kuthi , Yunsang Kim
发明人： Gregory S. Sexton , Andrew D. Bailey, III , Andras Kuthi , Yunsang Kim
IPC分类号： H01J37/32 , H01L21/00 , H01L21/311 , H01L21/3213 , H01L21/02
CPC分类号： H01L21/02087 , H01J37/32009 , H01J37/32082 , H01J37/32559 , H01J37/32642 , H01J37/32862 , H01L21/02057 , H01L21/31116 , H01L21/31138 , H01L21/32136
摘要： The embodiments provide apparatus and methods for removal of etch byproducts, dielectric films and metal films near the substrate bevel edge, and chamber interior to avoid the accumulation of polymer byproduct and deposited films and to improve process yield. In an exemplary embodiment, a plasma processing chamber configured to clean a bevel edge of a substrate is provided. The plasma processing chamber includes a substrate support configured to receive the substrate. The plasma processing chamber also includes a bottom edge electrode surrounding the substrate support. The bottom edge electrode and the substrate support are electrically isolated from one another by a bottom dielectric ring. A surface of the bottom edge electrode facing the substrate is covered by a bottom thin dielectric layer. The plasma processing chamber further includes a top edge electrode surrounding a top insulator plate opposing the substrate support. The top edge electrode is electrically grounded. A surface of the top edge electrode facing the substrate is covered by a top thin dielectric layer. The top edge electrode and the bottom edge electrode oppose one another and are configured to generate a cleaning plasma to clean the bevel edge of the substrate.
摘要翻译：这些实施例提供用于去除蚀刻副产物，电介质膜和金属膜附近的衬底斜面边缘的设备和方法，以及室内，以避免聚合物副产物和沉积膜的堆积并提高工艺产率。在示例性实施例中，提供了构造成清洁基板的斜边缘的等离子体处理室。等离子体处理室包括被配置为接收衬底的衬底支撑件。等离子体处理室还包括围绕衬底支撑件的底部边缘电极。底部边缘电极和基底支撑件通过底部介电环彼此电隔离。面向基板的底部边缘电极的表面被底部薄的电介质层覆盖。等离子体处理室还包括围绕与衬底支撑件相对的顶部绝缘体板的顶部边缘电极。顶边电极电接地。面向衬底的顶边电极的表面被顶部薄介电层覆盖。顶边电极和下边缘电极彼此相对并且被配置为产生清洁等离子体以清洁衬底的斜边缘。

45. 发明申请

US20130312913A1 ARRANGEMENT FOR DEPOSITING BEVEL PROTECTIVE FILM 审中-公开
标题翻译：沉积保护膜的安排
公开(公告)号：US20130312913A1
公开(公告)日：2013-11-28
申请号：US13959595
申请日：2013-08-05
申请人： Neungho Shin , Patrick Chung , Yunsang Kim
发明人： Neungho Shin , Patrick Chung , Yunsang Kim
IPC分类号： H01L21/67
CPC分类号： H01L21/67069 , H01J37/32366 , H01J37/32376 , H01J37/32568 , H01L21/2007 , H01L21/30625 , H01L21/3083 , H01L21/67017
摘要： An arrangement for depositing a film at a bevel edge of a substrate in a plasma chamber. The arrangement includes a gas delivery system for supplying gas into the chamber. The arrangement also includes a pair of electrodes including a movable electrode and a stationary electrode, wherein the substrate is disposed on one of the pair of electrodes. The arrangement further includes a gap controller module configured for adjusting an electrode gap between the pair of electrodes to a gap distance configured to prevent plasma formation over a center portion of the substrate. The gap distance is also dimensioned such that a plasma-sustainable condition around the bevel edge of the substrate is formed. The arrangement moreover includes a heater disposed below the substrate and powered by an RE source, wherein the heater is maintained at a chuck temperature conducive for facilitating film deposition on the bevel edge of the substrate.
摘要翻译：一种用于在等离子体室中的衬底的斜边缘处沉积膜的布置。该装置包括用于将气体供应到室中的气体输送系统。该布置还包括一对电极，其包括可动电极和固定电极，其中，所述基板设置在所述一对电极中的一个上。该装置还包括间隙控制器模块，其配置用于将一对电极之间的电极间隙调整到间隔距离，间隙距离被配置为防止等离子体在衬底的中心部分上形成。间隙距离的尺寸也被设计成使得形成在基板的斜边缘周围的等离子体可持续状态。该装置还包括设置在基板下方并由RE源供电的加热器，其中加热器保持在有利于在衬底的斜边缘上的膜沉积的卡盘温度。

46. 发明授权

US08440051B2 Plasma processing chamber for bevel edge processing 有权
标题翻译：等离子处理室用于斜边加工
公开(公告)号：US08440051B2
公开(公告)日：2013-05-14
申请号：US13082393
申请日：2011-04-07
申请人： Andrew D. Bailey, III , Yunsang Kim
发明人： Andrew D. Bailey, III , Yunsang Kim
IPC分类号： C23F1/00 , H01L21/306
CPC分类号： H01J37/32385 , H01J37/321 , H01J37/32366 , H01J37/32706 , H01L21/02087 , H01L21/67069 , H01L21/6715
摘要： Chambers for processing a bevel edge of a substrate are provided. One such chamber includes a bottom electrode defined to support a substrate in the chamber. The bottom electrode has a bottom first level for supporting the substrate and a bottom second level near an outer edge of bottom electrode. The bottom second level is defined at a step below the bottom first level. Further included is a top electrode oriented above the bottom electrode. The top electrode having a top first level and a top second level, where the top first level is opposite the bottom first level and the top second level is opposite the bottom second level. The top second level is defined at a step above the top first level. A bottom ring mount oriented at the bottom second level is included. The bottom ring mount includes a first adjuster for moving a bottom permanent magnet toward and away from the top electrode. Further included is a top ring mount oriented at the top second level. The top ring mount includes a second adjuster for moving a top permanent magnet toward and away from the bottom electrode.
摘要翻译：提供了用于处理基板的斜边缘的室。一个这样的室包括限定为支撑室中的衬底的底部电极。底部电极具有用于支撑衬底的底部第一电平和底部电极的外部边缘附近的底部第二电平。底部第二级别定义在底层第一级以下的一级。还包括位于底部电极上方的顶部电极。顶部电极具有顶部第一电平和顶部第二电平，其中顶部第一电平与底部第一电平相反，而顶部第二电平与底部第二电平相反。顶级的第二级是在顶级第一级以上的一级定义的。包括位于底部第二级的底环安装座。底环安装件包括用于使底部永磁体朝向和远离顶部电极移动的第一调节器。另外还包括一个位于顶部第二层的顶环安装座。顶环安装件包括用于使顶部永磁体朝向和远离底部电极移动的第二调节器。

47. 发明授权

US08398778B2 Control of bevel etch film profile using plasma exclusion zone rings larger than the wafer diameter 有权
标题翻译：使用大于晶片直径的等离子体排除区环来控制斜面蚀刻膜轮廓
公开(公告)号：US08398778B2
公开(公告)日：2013-03-19
申请号：US12076257
申请日：2008-03-14
申请人： Tong Fang , Yunsang Kim , Keechan Kim , George Stojakovic
发明人： Tong Fang , Yunsang Kim , Keechan Kim , George Stojakovic
IPC分类号： B08B6/00 , C25F1/00 , C25F3/30 , C25F5/00
CPC分类号： H01L21/67028 , H01J37/32642 , H01L21/02087 , H01L21/3065
摘要： A method of cleaning a bevel edge of a semiconductor substrate is provided. A semiconductor substrate is placed on a substrate support in a reaction chamber of a plasma processing apparatus. The substrate has a dielectric layer overlying a top surface and a bevel edge of the substrate, the layer extending above and below an apex of the bevel edge. A process gas is introduced into the reaction chamber and energized into a plasma. The bevel edge is cleaned with the plasma so as to remove the layer below the apex without removing all of the layer above the apex.
摘要翻译：提供一种清洁半导体衬底的斜边缘的方法。将半导体衬底放置在等离子体处理设备的反应室中的衬底支撑件上。衬底具有覆盖衬底的顶表面和斜面边缘的介电层，该层在斜面边缘的顶点的上方和下方延伸。将工艺气体引入反应室并通电为等离子体。斜面边缘用等离子体清洁，以便除去顶点以下的层，而不会移除顶点上方的所有层。

48. 发明授权

US08211238B2 System, method and apparatus for self-cleaning dry etch 有权
标题翻译：用于自清洁干蚀刻的系统，方法和设备
公开(公告)号：US08211238B2
公开(公告)日：2012-07-03
申请号：US11444942
申请日：2006-05-31
申请人： Andrew D. Bailey, III , Shrikant P. Lohokare , Arthur M. Howald , Yunsang Kim
发明人： Andrew D. Bailey, III , Shrikant P. Lohokare , Arthur M. Howald , Yunsang Kim
IPC分类号： C25F3/12 , B08B9/027
CPC分类号： B08B7/00 , B08B7/0035 , B08B7/0071 , H01J37/3244 , H01J37/32522 , H01J37/32862 , H01J2237/022 , H01L21/3065 , H01L21/32115 , H01L21/32136 , H01L21/67034 , H01L21/67051 , H01L21/67069 , H01L21/6708 , H01L21/7684 , Y10S438/905
摘要： A method for cleaning a processing chamber that includes heating an inner surface of the processing chamber to a first temperature. The first temperature can be sufficient to cause a first species to become volatile. The first species can be one of several species deposited on the inner surface. A cleaning chemistry is injected into the processing chamber. The cleaning chemistry can be reactive with a second one of the species to convert the second species to the first species. The volatilized first species can also be output from the processing chamber. A system for cleaning the process chamber is also described.
摘要翻译：一种用于清洁处理室的方法，包括将处理室的内表面加热至第一温度。第一个温度足以使第一个物质变得挥发。第一种可以是沉积在内表面上的几种物质之一。将清洁化学品注入到处理室中。清洁化学品可以与第二种物质反应以将第二种类转化为第一种。挥发的第一种也可以从处理室输出。还描述了用于清洁处理室的系统。

49. 发明申请

US20110049101A1 ARRANGEMENTS FOR MANIPULATING PLASMA CONFINEMENT WITHIN A PLASMA PROCESSING SYSTEM AND METHODS THEREOF 有权
标题翻译：用于在等离子体处理系统中操纵等离子体配置的装置及其方法
公开(公告)号：US20110049101A1
公开(公告)日：2011-03-03
申请号：US12552474
申请日：2009-09-02
申请人： Eller Y. Juco , Neungho Shin , Yunsang Kim , Andrew Bailey
发明人： Eller Y. Juco , Neungho Shin , Yunsang Kim , Andrew Bailey
IPC分类号： C23F1/00
CPC分类号： H01J37/32183 , H01J37/32091 , H01J37/32541 , H01J37/32568 , H01J37/32706 , H01J2237/334
摘要： An arrangement for controlling bevel etch rate during plasma processing within a processing chamber. The arrangement includes a power source and a gas distribution system. The arrangement also includes a lower electrode, which is configured at least for supporting a substrate. The arrangement further includes a top ring electrode positioned above the substrate and a bottom ring electrode positioned below the substrate. The arrangement yet also includes a first match arrangement coupled to the top ring electrode and configured at least for controlling current flowing through the top ring electrode to control amount of plasma available for etching at least a part of the substrate top edge. The arrangement yet further includes a second match arrangement configured to control the current flowing through the bottom ring electrode to control amount of plasma available for at least etching at least a part of the substrate bottom edge.
摘要翻译：一种用于在处理室内的等离子体处理期间控制斜面蚀刻速率的装置。该装置包括电源和气体分配系统。该布置还包括下电极，其被配置为至少用于支撑衬底。该布置还包括位于基板上方的顶环电极和位于基板下方的底环电极。该布置还包括耦合到顶环电极并且被配置为至少用于控制流过顶环电极的电流以控制可用于蚀刻衬底顶部边缘的至少一部分的等离子体的第一匹配布置。该装置还包括第二匹配装置，其被配置为控制流过底环电极的电流以控制可用于至少蚀刻至少一部分衬底底边缘的等离子体的量。

50. 发明授权

US07858898B2 Bevel etcher with gap control 有权
标题翻译：斜角蚀刻机具有间隙控制
公开(公告)号：US07858898B2
公开(公告)日：2010-12-28
申请号：US11698191
申请日：2007-01-26
申请人： Andrew D. Bailey, III , Alan M. Schoepp , Gregory Sexton , Andras Kuthi , Yunsang Kim , William S. Kennedy
发明人： Andrew D. Bailey, III , Alan M. Schoepp , Gregory Sexton , Andras Kuthi , Yunsang Kim , William S. Kennedy
IPC分类号： B23K10/00
CPC分类号： H01L21/0209 , H01J37/32366 , H01J37/32568 , H01J2237/335 , H01L21/67069
摘要： A device for cleaning a bevel edge of a semiconductor substrate. The device includes a lower electrode assembly that has a top surface and is adapted to support the substrate and an upper electrode assembly that has a bottom surface opposing the top surface. The lower and upper electrode assemblies generate plasma for cleaning the bevel edge of the substrate disposed between the top and bottom surfaces during operation. The device also includes a mechanism for suspending the upper electrode assembly over the lower support and adjusting the tilt angle and horizontal translation of the bottom surface relative to the top surface.
摘要翻译：一种用于清洁半导体衬底的斜边缘的装置。该装置包括具有顶表面并适于支撑基底的下电极组件和具有与顶表面相对的底表面的上电极组件。下部和上部电极组件在操作期间产生用于清洁设置在顶部和底部表面之间的衬底的斜面边缘的等离子体。该装置还包括用于将上电极组件悬挂在下支撑件上并且调节底表面相对于顶表面的倾斜角度和水平平移的机构。

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