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1. 发明申请

US20080145998A1 METHOD OF FORMING A LOW-K DUAL DAMASCENE INTERCONNECT STRUCTURE 失效
标题翻译：形成低K双重DAMASCENE互连结构的方法
公开(公告)号：US20080145998A1
公开(公告)日：2008-06-19
申请号：US11531493
申请日：2006-09-13
申请人： GERARDO A. DELGADINO , Yan Ye , Neungho Shin , Yunsang Kim , Li-Qun Xia , Tzu-Fang Huang , Lihua Li Huang , Joey Chiu , Xiaoye Zhao , Fang Tian , Wen Zhu , Ellie Yieh
发明人： GERARDO A. DELGADINO , Yan Ye , Neungho Shin , Yunsang Kim , Li-Qun Xia , Tzu-Fang Huang , Lihua Li Huang , Joey Chiu , Xiaoye Zhao , Fang Tian , Wen Zhu , Ellie Yieh
IPC分类号： H01L21/76
CPC分类号： H01L21/76826 , H01L21/76811 , H01L21/76813
摘要： A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.
摘要翻译：一种制造互连结构的方法，包括将通孔蚀刻到上部低K电介质层中并进入下部低K电介质层的硬化部分。通孔由形成在光致抗蚀剂层中的图案限定。然后剥离光致抗蚀剂层，并且将由硬掩模限定的通孔的沟槽蚀刻到上部低K电介质层中，并且同时蚀刻到下部低K电介质层的硬化部分中的通孔是进一步蚀刻到下部低K介电层中。结果是低K电介质双镶嵌结构。

2. 发明授权

US07132369B2 Method of forming a low-K dual damascene interconnect structure 失效
标题翻译：形成低K双镶嵌互连结构的方法
公开(公告)号：US07132369B2
公开(公告)日：2006-11-07
申请号：US10745344
申请日：2003-12-22
申请人： Gerardo A. Delgadino , Yan Ye , Neungho Shin , Yunsang Kim , Li-Qun Xia , Tzu-Fang Huang , Lihua Li , Joey Chiu , Xiaoye Zhao , Fang Tian , Wen Zhu , Ellie Yieh
发明人： Gerardo A. Delgadino , Yan Ye , Neungho Shin , Yunsang Kim , Li-Qun Xia , Tzu-Fang Huang , Lihua Li , Joey Chiu , Xiaoye Zhao , Fang Tian , Wen Zhu , Ellie Yieh
IPC分类号： H01L21/302
CPC分类号： H01L21/76826 , H01L21/76811 , H01L21/76813
摘要： A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.
摘要翻译：一种制造互连结构的方法，包括将通孔蚀刻到上部低K电介质层中并进入下部低K电介质层的硬化部分。通孔由形成在光致抗蚀剂层中的图案限定。然后剥离光致抗蚀剂层，并且将由硬掩模限定的通孔的沟槽蚀刻到上部低K电介质层中，并且同时蚀刻到下部低K电介质层的硬化部分中的通孔为进一步蚀刻到下部低K介电层中。结果是低K电介质双镶嵌结构。

3. 发明授权

US07435685B2 Method of forming a low-K dual damascene interconnect structure 失效
标题翻译：形成低K双镶嵌互连结构的方法
公开(公告)号：US07435685B2
公开(公告)日：2008-10-14
申请号：US11531493
申请日：2006-09-13
申请人： Gerardo A. Delgadino , Yan Ye , Neungho Shin , Yunsang Kim , Li-Qun Xia , Tzu-Fang Huang , Lihua Li Huang , Joey Chiu , Xiaoye Zhao , Fang Tian , Wen Zhu , Ellie Yieh
发明人： Gerardo A. Delgadino , Yan Ye , Neungho Shin , Yunsang Kim , Li-Qun Xia , Tzu-Fang Huang , Lihua Li Huang , Joey Chiu , Xiaoye Zhao , Fang Tian , Wen Zhu , Ellie Yieh
IPC分类号： H01L21/311
CPC分类号： H01L21/76826 , H01L21/76811 , H01L21/76813
摘要： A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.
摘要翻译：一种制造互连结构的方法，包括将通孔蚀刻到上部低K电介质层中并进入下部低K电介质层的硬化部分。通孔由形成在光致抗蚀剂层中的图案限定。然后剥离光致抗蚀剂层，并且将由硬掩模限定的通孔的沟槽蚀刻到上部低K电介质层中，并且同时蚀刻到下部低K电介质层的硬化部分中的通孔为进一步蚀刻到下部低K介电层中。结果是低K电介质双镶嵌结构。

4. 发明申请

US20050026430A1 Selective etching of carbon-doped low-k dielectrics 失效
标题翻译：选择性蚀刻碳掺杂低k电介质
公开(公告)号：US20050026430A1
公开(公告)日：2005-02-03
申请号：US10632873
申请日：2003-08-01
申请人： Yunsang Kim , Neungho Shin , Heeyeop Chae , Joey Chiu , Yan Ye , Fang Tian , Xiaoye Zhao
发明人： Yunsang Kim , Neungho Shin , Heeyeop Chae , Joey Chiu , Yan Ye , Fang Tian , Xiaoye Zhao
IPC分类号： H01L21/3065 , H01L21/311 , H01L21/302 , H01L21/461
CPC分类号： H01L21/31116 , Y10S438/963
摘要： The present invention includes a process for selectively etching a low-k dielectric material formed on a substrate using a plasma of a gas mixture in a plasma etch chamber. The gas mixture comprises a fluorine-rich fluorocarbon or hydrofluorocarbon gas, a nitrogen-containing gas, and one or more additive gases, such as a hydrogen-rich hydrofluorocarbon gas, an inert gas and/or a carbon-oxygen gas. The process provides a low-k dielectric to a photoresist mask etching selectivity ratio greater than about 5:1, a low-k dielectric to a barrier/liner layer etching selectivity ratio greater about 10:1, and a low-k dielectric etch rate higher than about 4000 Å/min.
摘要翻译：本发明包括使用等离子体蚀刻室中的气体混合物的等离子体来选择性地蚀刻在衬底上形成的低k电介质材料的方法。气体混合物包括富氟碳氟化合物或氢氟烃气体，含氮气体和一种或多种添加剂气体，例如富氢氢氟烃气体，惰性气体和/或碳 - 氧气体。该方法提供了大于约5:1的光致抗蚀剂掩模蚀刻选择比的低k电介质，大于10:1的低k电介质到阻挡层/衬层蚀刻选择比，以及低k电介质蚀刻速率高于约4000Å/ min。

5. 发明授权

US07256134B2 Selective etching of carbon-doped low-k dielectrics 失效
标题翻译：选择性蚀刻碳掺杂低k电介质
公开(公告)号：US07256134B2
公开(公告)日：2007-08-14
申请号：US10632873
申请日：2003-08-01
申请人： Yunsang Kim , Neungho Shin , Heeyeop Chae , Joey Chiu , Yan Ye , Fang Tian , Xiaoye Zhao
发明人： Yunsang Kim , Neungho Shin , Heeyeop Chae , Joey Chiu , Yan Ye , Fang Tian , Xiaoye Zhao
IPC分类号： H01L21/302
CPC分类号： H01L21/31116 , Y10S438/963
摘要： The present invention includes a process for selectively etching a low-k dielectric material formed on a substrate using a plasma of a gas mixture in a plasma etch chamber. The gas mixture comprises a fluorine-rich fluorocarbon or hydrofluorocarbon gas, a nitrogen-containing gas, and one or more additive gases, such as a hydrogen-rich hydrofluorocarbon gas, an inert gas and/or a carbon-oxygen gas. The process provides a low-k dielectric to a photoresist mask etching selectivity ratio greater than about 5:1, a low-k dielectric to a barrier/liner layer etching selectivity ratio greater about 10:1, and a low-k dielectric etch rate higher than about 4000 Å/min.
摘要翻译：本发明包括使用等离子体蚀刻室中的气体混合物的等离子体来选择性地蚀刻形成在衬底上的低k电介质材料的方法。气体混合物包括富氟碳氟化合物或氢氟烃气体，含氮气体和一种或多种添加剂气体，例如富氢氢氟烃气体，惰性气体和/或碳 - 氧气体。该方法提供了大于约5:1的光致抗蚀剂掩模蚀刻选择比的低k电介质，大于10:1的低k电介质到阻挡层/衬层蚀刻选择比，以及低k电介质蚀刻速率高于约4000Å/ min。

6. 发明授权

US09275838B2 Arrangements for manipulating plasma confinement within a plasma processing system and methods thereof 有权
标题翻译：在等离子体处理系统中操纵等离子体约束的布置及其方法
公开(公告)号：US09275838B2
公开(公告)日：2016-03-01
申请号：US12552474
申请日：2009-09-02
申请人： Eller Y. Juco , Neungho Shin , Yunsang Kim , Andrew Bailey
发明人： Eller Y. Juco , Neungho Shin , Yunsang Kim , Andrew Bailey
IPC分类号： H01J37/32
CPC分类号： H01J37/32183 , H01J37/32091 , H01J37/32541 , H01J37/32568 , H01J37/32706 , H01J2237/334
摘要： An arrangement for controlling bevel etch rate during plasma processing within a processing chamber. The arrangement includes a power source and a gas distribution system. The arrangement also includes a lower electrode, which is configured at least for supporting a substrate. The arrangement further includes a top ring electrode positioned above the substrate and a bottom ring electrode positioned below the substrate. The arrangement yet also includes a first match arrangement coupled to the top ring electrode and configured at least for controlling current flowing through the top ring electrode to control amount of plasma available for etching at least a part of the substrate top edge. The arrangement yet further includes a second match arrangement configured to control the current flowing through the bottom ring electrode to control amount of plasma available for at least etching at least a part of the substrate bottom edge.
摘要翻译：一种用于在处理室内的等离子体处理期间控制斜面蚀刻速率的装置。该装置包括电源和气体分配系统。该布置还包括下电极，其被配置为至少用于支撑衬底。该布置还包括位于基板上方的顶环电极和位于基板下方的底环电极。该布置还包括耦合到顶环电极并且被配置为至少用于控制流过顶环电极的电流以控制可用于蚀刻衬底顶部边缘的至少一部分的等离子体的第一匹配布置。该装置还包括第二匹配装置，其被配置为控制流过底环电极的电流以控制可用于至少蚀刻至少一部分衬底底边缘的等离子体的量。

7. 发明授权

US08501283B2 Methods for depositing bevel protective film 有权
标题翻译：沉积斜角保护膜的方法
公开(公告)号：US08501283B2
公开(公告)日：2013-08-06
申请号：US12907149
申请日：2010-10-19
申请人： Neungho Shin , Patrick Chung , Yunsang Kim
发明人： Neungho Shin , Patrick Chung , Yunsang Kim
IPC分类号： H05H1/24
CPC分类号： H01L21/67069 , H01J37/32366 , H01J37/32376 , H01J37/32568 , H01L21/2007 , H01L21/30625 , H01L21/3083 , H01L21/67017
摘要： A method of film deposition using localized plasma to protect bevel edge of a wafer in a plasma chamber. The method includes adjusting an electrode gap between a movable electrode and a stationary electrode, the wafer being disposed on one of the movable electrode and the stationary electrode, to a gap distance configured to prevent plasma formation over a center portion of the wafer, the gap distance also dimensioned such that a plasma-sustainable condition around the bevel edge of the wafer is formed after the adjusting. The method also includes flowing deposition gas into the plasma chamber. The method includes maintaining, using a heater, a chuck temperature that is configured to facilitate film deposition on the bevel edge. The method further includes generating the localized plasma from the deposition gas for depositing a film on the bevel edge.
摘要翻译：使用局部等离子体的膜沉积方法来保护等离子体室中的晶片的斜边缘。该方法包括调整可动电极和固定电极之间的电极间隙，将晶片设置在可动电极和固定电极中的一个上，形成为防止等离子体在晶片的中心部分形成的间隙距离，间隙距离也被确定为使得在调整之后形成围绕晶片的斜边缘的等离子体可持续状态。该方法还包括将沉积气体流入等离子体室。该方法包括使用加热器维持配置成有助于膜倾斜边缘上的膜沉积的卡盘温度。该方法还包括从沉积气体产生局部等离子体，以便在斜面边缘上沉积膜。

8. 发明申请

US20120094502A1 METHODS FOR DEPOSITING BEVEL PROTECTIVE FILM 有权
标题翻译：沉积水保护膜的方法
公开(公告)号：US20120094502A1
公开(公告)日：2012-04-19
申请号：US12907149
申请日：2010-10-19
申请人： Neungho Shin , Patrick Chung , Yunsang Kim
发明人： Neungho Shin , Patrick Chung , Yunsang Kim
IPC分类号： H01L21/30
CPC分类号： H01L21/67069 , H01J37/32366 , H01J37/32376 , H01J37/32568 , H01L21/2007 , H01L21/30625 , H01L21/3083 , H01L21/67017
摘要： A method of film deposition using localized plasma to protect bevel edge of a wafer in a plasma chamber. The method includes adjusting an electrode gap between a movable electrode and a stationary electrode, the wafer being disposed on one of the movable electrode and the stationary electrode, to a gap distance configured to prevent plasma formation over a center portion of the wafer, the gap distance also dimensioned such that a plasma-sustainable condition around the bevel edge of the wafer is formed after the adjusting. The method also includes flowing deposition gas into the plasma chamber. The method includes maintaining, using a heater, a chuck temperature that is configured to facilitate film deposition on the bevel edge. The method further includes generating the localized plasma from the deposition gas for depositing a film on the bevel edge.
摘要翻译：使用局部等离子体的膜沉积方法来保护等离子体室中的晶片的斜边缘。该方法包括调整可动电极和固定电极之间的电极间隙，将晶片设置在可动电极和固定电极中的一个上，形成为防止等离子体在晶片的中心部分形成的间隙距离，间隙距离也被确定为使得在调整之后形成围绕晶片的斜边缘的等离子体可持续状态。该方法还包括将沉积气体流入等离子体室。该方法包括使用加热器维持配置成有助于膜倾斜边缘上的膜沉积的卡盘温度。该方法还包括从沉积气体产生局部等离子体，以便在斜面边缘上沉积膜。

9. 发明申请

US20130312913A1 ARRANGEMENT FOR DEPOSITING BEVEL PROTECTIVE FILM 审中-公开
标题翻译：沉积保护膜的安排
公开(公告)号：US20130312913A1
公开(公告)日：2013-11-28
申请号：US13959595
申请日：2013-08-05
申请人： Neungho Shin , Patrick Chung , Yunsang Kim
发明人： Neungho Shin , Patrick Chung , Yunsang Kim
IPC分类号： H01L21/67
CPC分类号： H01L21/67069 , H01J37/32366 , H01J37/32376 , H01J37/32568 , H01L21/2007 , H01L21/30625 , H01L21/3083 , H01L21/67017
摘要： An arrangement for depositing a film at a bevel edge of a substrate in a plasma chamber. The arrangement includes a gas delivery system for supplying gas into the chamber. The arrangement also includes a pair of electrodes including a movable electrode and a stationary electrode, wherein the substrate is disposed on one of the pair of electrodes. The arrangement further includes a gap controller module configured for adjusting an electrode gap between the pair of electrodes to a gap distance configured to prevent plasma formation over a center portion of the substrate. The gap distance is also dimensioned such that a plasma-sustainable condition around the bevel edge of the substrate is formed. The arrangement moreover includes a heater disposed below the substrate and powered by an RE source, wherein the heater is maintained at a chuck temperature conducive for facilitating film deposition on the bevel edge of the substrate.
摘要翻译：一种用于在等离子体室中的衬底的斜边缘处沉积膜的布置。该装置包括用于将气体供应到室中的气体输送系统。该布置还包括一对电极，其包括可动电极和固定电极，其中，所述基板设置在所述一对电极中的一个上。该装置还包括间隙控制器模块，其配置用于将一对电极之间的电极间隙调整到间隔距离，间隙距离被配置为防止等离子体在衬底的中心部分上形成。间隙距离的尺寸也被设计成使得形成在基板的斜边缘周围的等离子体可持续状态。该装置还包括设置在基板下方并由RE源供电的加热器，其中加热器保持在有利于在衬底的斜边缘上的膜沉积的卡盘温度。

10. 发明申请

US20110049101A1 ARRANGEMENTS FOR MANIPULATING PLASMA CONFINEMENT WITHIN A PLASMA PROCESSING SYSTEM AND METHODS THEREOF 有权
标题翻译：用于在等离子体处理系统中操纵等离子体配置的装置及其方法
公开(公告)号：US20110049101A1
公开(公告)日：2011-03-03
申请号：US12552474
申请日：2009-09-02
申请人： Eller Y. Juco , Neungho Shin , Yunsang Kim , Andrew Bailey
发明人： Eller Y. Juco , Neungho Shin , Yunsang Kim , Andrew Bailey
IPC分类号： C23F1/00
CPC分类号： H01J37/32183 , H01J37/32091 , H01J37/32541 , H01J37/32568 , H01J37/32706 , H01J2237/334
摘要： An arrangement for controlling bevel etch rate during plasma processing within a processing chamber. The arrangement includes a power source and a gas distribution system. The arrangement also includes a lower electrode, which is configured at least for supporting a substrate. The arrangement further includes a top ring electrode positioned above the substrate and a bottom ring electrode positioned below the substrate. The arrangement yet also includes a first match arrangement coupled to the top ring electrode and configured at least for controlling current flowing through the top ring electrode to control amount of plasma available for etching at least a part of the substrate top edge. The arrangement yet further includes a second match arrangement configured to control the current flowing through the bottom ring electrode to control amount of plasma available for at least etching at least a part of the substrate bottom edge.
摘要翻译：一种用于在处理室内的等离子体处理期间控制斜面蚀刻速率的装置。该装置包括电源和气体分配系统。该布置还包括下电极，其被配置为至少用于支撑衬底。该布置还包括位于基板上方的顶环电极和位于基板下方的底环电极。该布置还包括耦合到顶环电极并且被配置为至少用于控制流过顶环电极的电流以控制可用于蚀刻衬底顶部边缘的至少一部分的等离子体的第一匹配布置。该装置还包括第二匹配装置，其被配置为控制流过底环电极的电流以控制可用于至少蚀刻至少一部分衬底底边缘的等离子体的量。

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