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31. 发明申请

US20070026609A1 NON-VOLATILE MEMORY AND FABRICATING METHOD THEREOF 失效
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US20070026609A1
公开(公告)日：2007-02-01
申请号：US11463250
申请日：2006-08-08
申请人： Jongoh Kim , Yider Wu , Kent-Kuohua Chang
发明人： Jongoh Kim , Yider Wu , Kent-Kuohua Chang
IPC分类号： H01L21/336
CPC分类号： H01L21/28282 , H01L27/115 , H01L27/11568
摘要： A method of fabricating a non-volatile memory is provided. A plurality of columns of isolation structures are formed on a substrate. A plurality of rows of stacked gate structures crossing over the isolation structures are formed on the substrate. A plurality of doping regions are formed in the substrate between two neighboring stacked gate structures. A plurality of stripes of spacers are formed on the sidewalls of stacked gate structures. A plurality of first dielectric layers are formed on a portion of the isolation structures adjacent to two rows of stacked gate structures. Also, one isolation structure is disposed between two neighboring first dielectric layers in the same row, while two neighboring rows comprising the first dielectric layer and the isolation structure are arranged in an interlacing manner. A plurality of first conductive layers are formed between two neighboring first dielectric layers in the same row.
摘要翻译：提供了一种制造非易失性存储器的方法。在衬底上形成多个隔离结构的列。在衬底上形成多个跨越隔离结构的层叠栅极结构的行。在两个相邻的堆叠栅极结构之间的衬底中形成多个掺杂区域。在堆叠栅极结构的侧壁上形成多个隔离条。多个第一电介质层形成在隔离结构的与两排堆叠栅极结构相邻的部分上。此外，一个隔离结构设置在相同行中的两个相邻的第一介电层之间，而包括第一介电层和隔离结构的两个相邻行以隔行方式布置。在同一行中的两个相邻的第一电介质层之间形成多个第一导电层。

32. 发明授权

US07157333B1 Non-volatile memory and fabricating method thereof 有权
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US07157333B1
公开(公告)日：2007-01-02
申请号：US11180117
申请日：2005-07-11
申请人： Jongoh Kim , Yider Wu , Kent-Kuohua Chang
发明人： Jongoh Kim , Yider Wu , Kent-Kuohua Chang
IPC分类号： H01L21/336
CPC分类号： H01L21/28282 , H01L27/115 , H01L27/11568
摘要： A method of fabricating a non-volatile memory is provided. A plurality of columns of isolation structures are formed on a substrate. A plurality of rows of stacked gate structures crossing over the isolation structures are formed on the substrate. A plurality of doping regions are formed in the substrate between two neighboring stacked gate structures. A plurality of stripes of spacers are formed on the sidewalls of stacked gate structures. A plurality of first dielectric layers are formed on a portion of the isolation structures adjacent to two rows of stacked gate structures. Also, one isolation structure is disposed between two neighboring first dielectric layers in the same row, while two neighboring rows comprising the first dielectric layer and the isolation structure are arranged in an interlacing manner. A plurality of first conductive layers are formed between two neighboring first dielectric layers in the same row.
摘要翻译：提供了一种制造非易失性存储器的方法。在衬底上形成多个隔离结构的列。在衬底上形成多个跨越隔离结构的层叠栅极结构的行。在两个相邻的堆叠栅极结构之间的衬底中形成多个掺杂区域。在堆叠栅极结构的侧壁上形成多个隔离条。多个第一电介质层形成在隔离结构的与两排堆叠栅极结构相邻的部分上。此外，一个隔离结构设置在相同行中的两个相邻的第一介电层之间，而包括第一介电层和隔离结构的两个相邻行以隔行方式布置。在同一行中的两个相邻的第一电介质层之间形成多个第一导电层。

33. 发明授权

US07078749B1 Memory structure having tunable interlayer dielectric and method for fabricating same 有权
标题翻译：具有可调谐层间电介质的记忆结构及其制造方法
公开(公告)号：US07078749B1
公开(公告)日：2006-07-18
申请号：US10618156
申请日：2003-07-11
申请人： Jean Yee-Mei Yang , Yider Wu
发明人： Jean Yee-Mei Yang , Yider Wu
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , G02F1/1334 , H01L29/792
摘要： According to one embodiment, a memory structure comprises a substrate having a channel region situated between a source region and a drain region. The memory structure further comprises a gate layer formed over the channel region of the substrate, and a tunable interlayer dielectric formed over the gate layer and the substrate. The tunable interlayer dielectric has a transparent state and an opaque state, and comprises a matrix and electrically or magnetically tunable material situated within the matrix. During the transparent state, UV rays can pass through the tunable interlayer dielectric to the gate layer, e.g., to perform a UV erase operation. During the opaque state, UV rays are prevented from passing through the tunable interlayer dielectric to the gate layer, thereby protecting the gate layer against unwanted charge storage and extrinsic damage that may occur during various processes.
摘要翻译：根据一个实施例，存储器结构包括具有位于源极区域和漏极区域之间的沟道区域的衬底。存储器结构还包括形成在衬底的沟道区上的栅极层和形成在栅极层和衬底上的可调谐层间电介质。可调谐层间电介质具有透明状态和不透明状态，并且包括位于基体内的矩阵和电或磁性可调谐材料。在透明状态期间，紫外线可以通过可调谐层间电介质到达栅极层，例如进行UV擦除操作。在不透明状态期间，防止紫外线通过可调谐层间电介质到栅极层，从而保护栅极层免于不必要的电荷存储和在各种过程中可能发生的外在损伤。

34. 发明授权

US07019366B1 Electrostatic discharge performance of a silicon structure and efficient use of area with electrostatic discharge protective device under the pad approach and adjustment of via configuration thereto to control drain junction resistance 有权
标题翻译：硅结构的静电放电性能，有效利用垫下方的静电放电保护装置的面积，调整通孔配置，以控制漏极结电阻
公开(公告)号：US07019366B1
公开(公告)日：2006-03-28
申请号：US10758173
申请日：2004-01-14
申请人： Nian Yang , Hiroyuki Ogawa , Yider Wu , Kuo-Tung Chang , Yu Sun
发明人： Nian Yang , Hiroyuki Ogawa , Yider Wu , Kuo-Tung Chang , Yu Sun
IPC分类号： H01L23/62
CPC分类号： H01L27/0251
摘要： More efficient use of silicon area is achieved by incorporating an electrostatic discharge protective (ESDP) device beneath a pad area of a semiconductor structure. The pad area includes a substrate having a first metal layer above it. A second metal layer is above the first metal layer. The ESDP device resides in the substrate below the first metal layer. A layer of dielectric separates the first and second metal layers. A via within the dielectric layer electrically couples the first and second metal layers. A via connects to the ESDP component. Subsequent metal layers can be arranged between the first and second metal layers. The Ohmic value of the resistance component of the ESDP device can be set during fabrication by fixing a number of individual via components, arranged electrically in parallel, by fixing the cross sectional area of the via components, and/or by fixing the length of the via components.
摘要翻译：通过在半导体结构的焊盘区域的下方并入静电放电保护（ESDP）器件来实现硅面积的更有效的使用。焊盘区域包括在其上方具有第一金属层的基板。第二金属层位于第一金属层之上。 ESDP设备位于第一金属层下方的基板中。电介质层分离第一和第二金属层。电介质层内的通孔电耦合第一和第二金属层。 A通道连接到ESDP组件。随后的金属层可以布置在第一和第二金属层之间。 ESDP装置的电阻部件的欧姆值可以在制造期间通过固定多个单独的通孔部件，通过固定通孔部件的横截面面积和/或固定长度通过组件。

35. 发明授权

US06897533B1 Multi-bit silicon nitride charge-trapping non-volatile memory cell 有权
标题翻译：多位氮化硅电荷捕获非易失性存储单元
公开(公告)号：US06897533B1
公开(公告)日：2005-05-24
申请号：US10247641
申请日：2002-09-18
申请人： Jean Yee-Mei Yang , Yider Wu
发明人： Jean Yee-Mei Yang , Yider Wu
IPC分类号： G11C16/04 , H01L21/28 , H01L29/423 , H01L29/788 , H01L29/792 , H01L29/02
CPC分类号： H01L29/7923 , G11C16/0475 , H01L21/28282 , H01L29/42332 , H01L29/7887
摘要： A non-volatile multi-bit memory cell is presented which comprises a source, a drain, a channel coupling the source and the drain, and a gate with a plurality of charge trapping regions located so that a trapped charge in each charge trapping region is enabled to affect the influence of the gate voltage on the flow of electrons in the channel. The charge trapping regions are in multiple layers of oxide/nitride/oxide and there can be multiple levels of charge trapping regions. Charges are stored in the nitride layers and isolated by the oxide layers.
摘要翻译：提出了一种非易失性多位存储单元，其包括源极，漏极，耦合源极和漏极的沟道以及具有多个电荷俘获区域的栅极，所述多个电荷俘获区域被定位成使得每个电荷俘获区域中的俘获电荷为能够影响栅极电压对通道中电子流的影响。电荷捕获区域处于多层氧化物/氮化物/氧化物中，并且可以有多个电荷俘获区域。电荷存储在氮化物层中并被氧化层隔离。

36. 发明授权

US06767791B1 Structure and method for suppressing oxide encroachment in a floating gate memory cell 有权
标题翻译：用于抑制浮动栅极存储单元中的氧化物侵蚀的结构和方法
公开(公告)号：US06767791B1
公开(公告)日：2004-07-27
申请号：US10364569
申请日：2003-02-10
申请人： Yider Wu , Harpreet K. Sachar , Jean Yee-Mei Yang
发明人： Yider Wu , Harpreet K. Sachar , Jean Yee-Mei Yang
IPC分类号： H01L21336
CPC分类号： H01L29/511 , H01L21/28273 , H01L29/42324
摘要： According to one exemplary embodiment, a structure comprises a substrate. The structure further comprises a tunnel oxide layer, where the tunnel oxide layer is situated on the substrate. The structure further comprises a floating gate situated on the tunnel oxide layer, where the floating gate comprises nitrogen. The floating gate may further comprise polysilicon and may be situated in a floating gate flash memory cell, for example. The nitrogen may suppress oxide growth at first and second end regions of the tunnel oxide layer, for example. The nitrogen may be implanted in the floating gate, for example, at a concentration of between approximately 1013 atoms per cm2 and approximately 1015 atoms per cm2. According to this exemplary embodiment, the structure further comprises an ONO stack situated over the floating gate. The structure may further comprise a control gate situated over the ONO stack.
摘要翻译：根据一个示例性实施例，一种结构包括基底。该结构还包括隧道氧化物层，其中隧道氧化物层位于衬底上。该结构还包括位于隧道氧化物层上的浮置栅极，其中浮栅包括氮。浮栅可以进一步包括多晶硅，并且例如可以位于浮动栅闪存单元中。例如，氮可以抑制隧道氧化物层的第一和第二端区域的氧化物生长。可以将氮气注入浮栅中，例如以约10 13个原子/ cm 2和约10 15个原子/ cm 2的浓度注入。根据该示例性实施例，该结构还包括位于浮动栅极上方的ONO堆叠。该结构还可以包括位于ONO堆叠上的控制门。

37. 发明授权

US06706595B2 Hard mask process for memory device without bitline shorts 有权
标题翻译：内存设备的硬掩模处理，无位线短路
公开(公告)号：US06706595B2
公开(公告)日：2004-03-16
申请号：US10100485
申请日：2002-03-14
申请人： Jean Y. Yang , Mark T. Ramsbey , Hidehiko Shiraiwa , Yider Wu , Emmanuil Lingunis , Tazrien Kamal
发明人： Jean Y. Yang , Mark T. Ramsbey , Hidehiko Shiraiwa , Yider Wu , Emmanuil Lingunis , Tazrien Kamal
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/115
摘要： A manufacturing method for a MirrorBit® Flash memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric layer. First and second bitlines are implanted and a wordline layer is deposited. A hard mask layer is deposited over the wordline layer. The hard mask is of a material formulated for removal without damaging the charge-trapping dielectric layer. A photoresist is deposited over the wordline layer and used to form a hard mask. The photoresist is removed. The wordline layer is processed using the hard mask to form a wordline and the hard mask is removed. A salicide is grown without short-circuiting the first and second bitlines.
摘要翻译：用于MirrorBit（闪存）闪存的制造方法包括提供半导体衬底和沉积电荷俘获电介质层。植入第一和第二位线，并存放字线层。硬掩模层沉积在字线层上。硬掩模是配制用于去除而不损坏电荷捕获介电层的材料。光刻胶沉积在字线层上并用于形成硬掩模。去除光致抗蚀剂。使用硬掩模处理字线层以形成字线，并且去除硬掩模。生长自杀剂不会使第一和第二位线短路。

38. 发明授权

US06667243B1 Etch damage repair with thermal annealing 有权
标题翻译：蚀刻损伤修复与热退火
公开(公告)号：US06667243B1
公开(公告)日：2003-12-23
申请号：US10222248
申请日：2002-08-16
申请人： Mark T. Ramsbey , Nicholas H. Tripsas , Arvind Halliyal , Jeffrey A. Shields , Yider Wu
发明人： Mark T. Ramsbey , Nicholas H. Tripsas , Arvind Halliyal , Jeffrey A. Shields , Yider Wu
IPC分类号： H01L21302
CPC分类号： H01L21/02071 , H01L21/31138 , H01L21/32137 , H01L21/32139 , H01L29/6659 , Y10S438/906 , Y10S438/94
摘要： A method of manufacturing a semiconductor device etches a feature on a substrate in accordance with a photoresist mask. The photoresist mask is removed by plasma etching. Laser thermal annealing is performed to vaporize polymer residue created during the stripping of the photoresist mask, and to repair damage to the substrate.
摘要翻译：半导体器件的制造方法根据光致抗蚀剂掩模蚀刻衬底上的特征。通过等离子体蚀刻去除光致抗蚀剂掩模。进行激光热退火以蒸发在光刻胶掩模剥离期间产生的聚合物残余物，并修复对基材的损伤。

39. 发明授权

US06465306B1 Simultaneous formation of charge storage and bitline to wordline isolation 有权
标题翻译：同时形成电荷存储和位线到字线隔离
公开(公告)号：US06465306B1
公开(公告)日：2002-10-15
申请号：US09723635
申请日：2000-11-28
申请人： Mark T. Ramsbey , Jean Y. Yang , Hidehiko Shiraiwa , Michael A. Van Buskirk , David M. Rogers , Ravi Sunkavalli , Janet Wang , Narbeh Derhacobian , Yider Wu
发明人： Mark T. Ramsbey , Jean Y. Yang , Hidehiko Shiraiwa , Michael A. Van Buskirk , David M. Rogers , Ravi Sunkavalli , Janet Wang , Narbeh Derhacobian , Yider Wu
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11573 , Y10S438/954 , Y10S438/981
摘要： One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving the sequential or non-sequential steps of forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; forming buried bitlines in the core region; and forming gates in the core region and the periphery region.
摘要翻译：本发明的一个方面涉及一种形成非挥发性半导体存储器件的方法，涉及在衬底上形成电荷俘获电介质的顺序或非顺序步骤，所述衬底具有芯区域和外围区域; 去除外围区域中的电荷捕获电介质的至少一部分; 在周边区域形成栅电介质; 在核心区域形成掩埋位线; 并且在芯区域和周边区域中形成栅极。

40. 发明授权

US06440797B1 Nitride barrier layer for protection of ONO structure from top oxide loss in a fabrication of SONOS flash memory 有权
标题翻译：用于在SONOS闪存的制造中保护ONO结构免受顶部氧化物损失的氮化物阻挡层
公开(公告)号：US06440797B1
公开(公告)日：2002-08-27
申请号：US09966702
申请日：2001-09-28
申请人： Yider Wu , Jean Yee-Mei Yang , Mark Ramsbey , Emmanuel H. Lingunis , Yu Sun
发明人： Yider Wu , Jean Yee-Mei Yang , Mark Ramsbey , Emmanuel H. Lingunis , Yu Sun
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L27/115 , Y10S438/954
摘要： A method for fabricating a SONOS device having a buried bit-line including the steps of: providing a semiconductor substrate having an ONO structure overlying the semiconductor substrate; forming a nitride barrier layer on the ONO structure to form a four-layer stack; forming a patterned photoresist layer on the nitride barrier layer; implanting As or P ions through the four-layer stack to form a bit-line buried under the ONO structure; stripping the photoresist layer and cleaning an upper surface of the four-layer stack; and consolidating the four-layer stack by applying an oxidation cycle. The invention further relates to a SONOS-type device including the nitride barrier layer.
摘要翻译：一种用于制造具有掩埋位线的SONOS器件的方法，包括以下步骤：提供具有覆盖在半导体衬底上的ONO结构的半导体衬底; 在ONO结构上形成氮化物阻挡层以形成四层堆叠; 在所述氮化物阻挡层上形成图案化的光致抗蚀剂层; 将As或P离子注入四层堆叠中以形成埋在ONO结构下的位线; 剥离光致抗蚀剂层并清洁四层堆叠的上表面; 并通过施加氧化循环来合并四层堆叠。本发明还涉及包括氮化物阻挡层的SONOS型器件。

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