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31. 发明授权

US5869889A Thin power tape ball grid array package 失效
标题翻译：薄电动带球栅阵列封装
公开(公告)号：US5869889A
公开(公告)日：1999-02-09
申请号：US840614
申请日：1997-04-21
申请人： Chok J. Chia , Patrick Variot , Maniam Alagaratnam
发明人： Chok J. Chia , Patrick Variot , Maniam Alagaratnam
IPC分类号： H01L23/29 , H01L21/60 , H01L23/12 , H01L23/24 , H01L23/31 , H01L23/36 , H01L23/498 , H01L23/34
CPC分类号： H01L23/36 , H01L23/24 , H01L23/4985 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L24/48 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/1532 , H01L2924/181
摘要： An integrated circuit package includes a heatspreader which is formed to have a centrally disposed recessed portion between planar surfaces, and flex tape extending from the planar surfaces into the centrally disposed surface. A semiconductor chip is mounted on the centrally disposed surface between the flex tape, and wire bonds interconnect bonding pads on the chip to the metal interconnect patterns on the flex tape. Plastic molding or epoxy is then applied to encapsulate the chip and wire bonding in the centrally disposed planar surface of the heat spreader. The package is then readily mounted on a motherboard using solder balls.
摘要翻译：集成电路封装包括散热器，其形成为在平面之间具有居中设置的凹部，以及从平面延伸到中心设置表面的柔性带。半导体芯片安装在柔性带之间的中央布置的表面上，并且引线将芯片上的接合焊盘互连到柔性带上的金属互连图案。然后施加塑料模制或环氧树脂以将芯片和引线接合封装在散热器的中心设置的平坦表面中。然后使用焊球将封装容易地安装在母板上。

32. 发明授权

US5789811A Surface mount peripheral leaded and ball grid array package 失效
公开(公告)号：US5789811A
公开(公告)日：1998-08-04
申请号：US725735
申请日：1996-10-04
申请人： Chok J. Chia , Patrick Variot
发明人： Chok J. Chia , Patrick Variot
IPC分类号： H01L23/12 , H01L23/24 , H01L23/31 , H01L23/495 , H01L23/498 , H05K3/34 , H01L23/02
CPC分类号： H01L23/24 , H01L23/3128 , H01L23/49531 , H01L23/49811 , H01L23/49816 , H05K3/341 , H01L2224/05554 , H01L2224/16 , H01L2224/48091 , H01L24/48 , H01L2924/00014 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/16195 , H01L2924/181 , H05K2201/10659 , H05K2201/10681 , H05K2201/10689 , H05K2201/10734 , Y02P70/613
摘要： A surface mounted integrated circuit die package includes a group of peripheral leads extending laterally outwardly from the perimeter of the package and also includes an array of solder balls on the bottom of the package. The arrangement provides for a greater number of input/output connections to a die package by utilizing both peripheral leads and a ball grid array without requiring increases in package size or a reduction in the width of electrically conductive interconnections.

33. 发明授权

US5557150A Overmolded semiconductor package 失效
标题翻译：包覆半导体封装
公开(公告)号：US5557150A
公开(公告)日：1996-09-17
申请号：US429605
申请日：1995-04-27
申请人： Patrick Variot , Chok J. Chia
发明人： Patrick Variot , Chok J. Chia
IPC分类号： G03F7/20 , H01L23/31 , H01L23/495 , H01L23/498 , H01L23/544 , H01L29/06 , H01L23/28
CPC分类号： G03F7/70433 , H01L23/3121 , H01L23/49517 , H01L23/49541 , H01L23/49838 , H01L23/49861 , H01L23/544 , H01L2223/54473 , H01L2224/48091 , H01L2224/48227 , H01L2224/49109 , H01L2224/73265 , H01L24/48 , H01L24/49 , H01L29/0657 , H01L2924/00014 , H01L2924/01078 , H01L2924/14 , H01L2924/15151 , H01L2924/15162 , H01L2924/15311 , H01L2924/15312 , H01L2924/181 , H01L2924/1815 , H01L2924/18301
摘要： A technique for providing partially and fully overmolded semiconductor packages is described which prevents delamination (detachment) of the molding compound from the substrate by allowing the molding compound to flow through holes in the substrate and forming it into rivet-like anchors on the opposite side of the substrate. Various shapes of rivet-like anchors are described. Different embodiments provide for the formation of molded standoffs and locating pins integral to the anchor structures.
摘要翻译：描述了一种用于提供部分和完全包覆模制的半导体封装的技术，其通过允许模塑料流过衬底中的孔并将其形成铆钉状锚固体，从而防止模塑料从衬底的分层（脱离）底物。描述了各种形状的铆钉状锚固件。不同的实施例提供模制支座的形成和与锚结构一体的定位销。

34. 发明授权

US5521427A Printed wiring board mounted semiconductor device having leadframe with alignment feature 失效
标题翻译：印刷线路板安装的半导体器件具有引导框架，具有对准特征
公开(公告)号：US5521427A
公开(公告)日：1996-05-28
申请号：US340807
申请日：1994-11-17
申请人： Chok J. Chia , Seng-Sooi Lim
发明人： Chok J. Chia , Seng-Sooi Lim
IPC分类号： H01L23/495 , H05K3/30 , H05K3/34 , H01L23/544
CPC分类号： H05K3/303 , H01L23/49541 , H01L2224/48091 , H01L2224/48247 , H05K2201/10303 , H05K2201/10659 , H05K2201/10689 , H05K2201/10962 , H05K2203/167 , H05K3/3421 , Y02P70/613 , Y10S438/975 , Y10T29/49121 , Y10T29/49133
摘要： A packaged semiconductor device, leadframe for making same, and method of mounting same to a printed circuit board are described. The device has a body, and a plurality of leads extending from the body. One or more alignment features are formed on the exterior of the package body, for maintaining precise alignment of the device with respect to a printed wiring board. The alignment feature is a tab formed as part of portion of the leadframe external to the package body. The tab may have various shapes, and may be provided with a hole for registering with a pin on an underlying substrate, such as a printed wiring board. The pin and the tab may be electrically connected.
摘要翻译：描述了一种封装的半导体器件，用于制造其的引线框，以及将其安装到印刷电路板的方法。该装置具有主体和从主体延伸的多个引线。一个或多个对准特征形成在包装体的外部上，以保持装置相对于印刷线路板的精确对准。对准特征是形成为包装体外部的引线框架的一部分的突片。突片可以具有各种形状，并且可以设置有用于与诸如印刷线路板的下面的基板上的销对准的孔。引脚和突片可以电连接。

35. 发明授权

US5463529A High power dissipating packages with matched heatspreader heatsink assemblies 失效
标题翻译：具有匹配散热器散热器组件的大功率消散封装
公开(公告)号：US5463529A
公开(公告)日：1995-10-31
申请号：US317968
申请日：1994-10-04
申请人： Chok J. Chia , Manian Alagaratnam , Qwai H. Low , Seng-Sooi Lim
发明人： Chok J. Chia , Manian Alagaratnam , Qwai H. Low , Seng-Sooi Lim
IPC分类号： F02F7/00 , H01L23/367 , H01L23/40 , H05K7/20
CPC分类号： H01L23/40 , F02F7/00 , H01L23/3675 , H01L2924/0002 , Y10T29/4913
摘要： A removable heatsink assembly comprised of a heatsink unit and a heatspreader is provided. The heatsink unit has at least one fin and a coupling collar for radiating heat away from a packaged electronic device. The heatspreader includes a platform attached to an inner collar in thermal contact with the packaged electronic device. The platform has one or more tabs suitable for mating with one or more flanges located on the coupling collar of the heatsink unit. Coupling grooves within the flanges engage the platform of the heatspreader when the flanges are mated with the heatspreader tabs and the heatsink is turned. The heatsink can therefore be quickly and conveniently attached to or removed from the heatspreader. The present invention thus permits a wide variety of different heatsinks to be interchangeably used with a single heatspreader attached to an electronic device package.
摘要翻译：提供了由散热器单元和散热器组成的可拆卸的散热器组件。散热器单元具有至少一个翅片和用于从封装的电子设备辐射热量的联接套环。散热器包括附接到与封装的电子设备热接触的内部套环的平台。该平台具有一个或多个适合于与位于散热器单元的联接环上的一个或多个凸缘相配合的凸片。当凸缘与散热片接头配合并且散热片转动时，凸缘内的耦合凹槽接合散热器的平台。因此，散热器可以快速方便地附接到散热器或从散热器移除。因此，本发明允许各种不同的散热器与附接到电子设备封装的单个散热器可互换地使用。

36. 发明授权

US5262927A Partially-molded, PCB chip carrier package 失效
标题翻译：部分成型，PCB芯片载体封装
公开(公告)号：US5262927A
公开(公告)日：1993-11-16
申请号：US834182
申请日：1992-02-07
申请人： Chok J. Chia , Seng-Sooi Lim
发明人： Chok J. Chia , Seng-Sooi Lim
IPC分类号： H01L23/12 , G03F7/20 , H01L23/31 , H01L23/495 , H01L23/498 , H01L23/50 , H01L29/06 , H05K1/11
CPC分类号： G03F7/70433 , H01L23/3121 , H01L23/49517 , H01L23/49541 , H01L23/49861 , H01L2224/48091 , H01L2224/48247 , H01L2224/49109 , H01L24/48 , H01L24/49 , H01L29/0657 , H01L2924/00014 , H01L2924/01014 , H01L2924/01078 , H01L2924/14 , H01L2924/15151 , H01L2924/15153 , H01L2924/1517 , H01L2924/1532 , H01L2924/181 , H01L2924/18301
摘要： A dambar-less leadframe is sandwiched between two printed circuit boards (PCBs). The PCBs form a major portion of the package body, and isolate the leadframe leads from plastic molding compound. In one embodiment, an upper PCB (substrate) is formed as a square ring, having an opening containing a heat sink element. A lower PCB is also formed as a square ring, and has a smaller opening for receiving a die. The back face of the die is mounted to the heat sink. The exposed front face of the die is wire bonded to inner ends of conductive traces on the exposed face of the lower PCB. The outer ends of the traces are electrically connected to the leadframe leads by plated-through vias extending through the two PCBs. The plated-through vias additionally secure the sandwich structure together. Plastic molding compound is injection/transfer molded over the front face of the die and the bond wires, forming a partially-molded package. In another embodiment, the upper PCB is a solid planar element, and is not provided with an opening for a heat sink. The back face of the die is mounted to the inside surface of the upper PCB.

37. 发明授权

US5197183A Modified lead frame for reducing wire wash in transfer molding of IC packages 失效
标题翻译：改进的引线框架，用于减少IC封装的传输成型中的电线清洗
公开(公告)号：US5197183A
公开(公告)日：1993-03-30
申请号：US787848
申请日：1991-11-05
申请人： Chok J. Chia , Seng-Sooi Lim
发明人： Chok J. Chia , Seng-Sooi Lim
IPC分类号： B29C45/14 , H01L21/56 , H01L23/495
CPC分类号： B29C45/14655 , H01L21/565 , H01L23/49551 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/181 , H01L2924/3025 , Y10T29/49121
摘要： In a leadframe supporting a semiconductor device, the tiebar adjacent the mold gate is kinked, or cut and bent, to form a baffle shielding bond wires connecting the semiconductor device to the leadframe from damage by a jet of incoming molding compound. Whether kinked or cut/bent, the baffle extends out of the plane of the leadframe so as to be disposed more-or-less directly in front of the gate.
摘要翻译：在支撑半导体器件的引线框架中，与模具门相邻的连接杆被扭结或切割和弯曲，以形成将半导体器件与引线框架连接的挡板屏蔽接合线，以免由入射的模塑料的射流造成损坏。无论是弯曲还是切割/弯曲，挡板延伸出引线框架的平面，以便直接在门的前方多或少地设置。

38. 发明授权

US06861343B2 Buffer metal layer 失效
标题翻译：缓冲金属层
公开(公告)号：US06861343B2
公开(公告)日：2005-03-01
申请号：US10267410
申请日：2002-10-09
申请人： Chok J. Chia , Qwai H. Low , Ramaswamy Ranganathan
发明人： Chok J. Chia , Qwai H. Low , Ramaswamy Ranganathan
IPC分类号： H01L23/367 , H01L23/373 , H01L23/522 , H01L23/552 , H01L21/44
CPC分类号： H01L23/552 , H01L23/367 , H01L23/3735 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit having a top passivation layer and bonding pads, where the improvement is a metal layer overlying all of the integrated circuit. The metal layer overlies the top passivation layer and is not in electrical contact with any of the bonding pads. In this manner, there is a structure that is added to the integrated circuit which has a relatively high thermal conductivity, and which also has a relatively high structural strength. With these two added properties, the occurrence of stress cracks, such as those induced by plastic molded packages, is reduced, and hot spots tend to be dissipated. Thus, the overlying metal layer tends to improve the reliability of the integrated circuit.
摘要翻译：具有顶部钝化层和接合焊盘的集成电路，其中改进是覆盖所有集成电路的金属层。金属层覆盖在顶部钝化层上，并且不与任何焊盘焊接。以这种方式，具有添加到具有相对较高导热性并且还具有相对较高的结构强度的集成电路的结构。通过这两个添加的性质，减少了由塑料模制包装引起的应力裂纹的发生，并且热点趋于消散。因此，上覆金属层倾向于提高集成电路的可靠性。

39. 发明授权

US06519844B1 Overmold integrated circuit package 有权
标题翻译：封装集成电路封装
公开(公告)号：US06519844B1
公开(公告)日：2003-02-18
申请号：US09940130
申请日：2001-08-27
申请人： Kumar Nagarajan , Seng Sooi Lim , Chok J. Chia
发明人： Kumar Nagarajan , Seng Sooi Lim , Chok J. Chia
IPC分类号： H05K330
CPC分类号： H01L24/32 , H01L23/13 , H01L23/3128 , H01L2224/16225 , H01L2224/27013 , H01L2224/32225 , H01L2224/73204 , H01L2224/83051 , H01L2224/83385 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/14 , H01L2924/15151 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , Y10T29/49144 , Y10T29/49146 , H01L2924/00
摘要： An integrated circuit package manufacturing process is described which reduces or eliminates the formation of voids in a molding compound between a die and an underlying substrate. The process includes providing the substrate, which has an upper surface and an air space above the upper surface. Electrically conductive vias are formed through the upper surface of the substrate which extend at least partially through the substrate, and fluid communication is provided between the vias and the overlying air space. The process includes attaching the integrated circuit die to the upper surface of the substrate over at least a portion of the vias, while leaving a gap between the die and the upper surface of the substrate. The process further includes flowing the molding compound into the gap between the die and the upper surface of the substrate while maintaining fluid communication between the vias and the air space. In this manner, air trapped between the molding compound and the upper surface of the substrate is urged to flow into the vias rather than forming a void in the molding compound. Fluid communication between the plurality of vias and the air space may be provided by not tenting the vias with a solder mask layer, or by removing any solder mask or other material which may have filled or tented over the vias during processing of the substrate.
摘要翻译：描述了一种集成电路封装制造工艺，其减少或消除了在管芯和下层衬底之间的模塑料中形成空隙。该方法包括提供在上表面上方具有上表面和空气空间的基底。导电孔通过衬底的上表面形成，其至少部分延伸通过衬底，并且在通孔和上覆空气空间之间提供流体连通。该过程包括在集成电路管芯的至少一部分通孔之上附接集成电路管芯到衬底的上表面，同时在管芯和衬底的上表面之间留下间隙。该方法还包括使模塑料流动到模具和衬底的上表面之间的间隙中，同时保持通孔和空气空间之间的流体连通。以这种方式，被迫在模塑料和衬底的上表面之间被捕获的空气被迫流入通孔，而不是在模塑料中形成空隙。多个通孔和空气空间之间的流体连通可以通过不用通孔焊接掩模层来提供，或者通过在衬底的处理期间移除可能已经填充或覆盖过孔的任何焊接掩模或其他材料来提供。

40. 发明授权

US06492253B1 Method for programming a substrate for array-type packages 有权
标题翻译：用于对阵列型封装的衬底进行编程的方法
公开(公告)号：US06492253B1
公开(公告)日：2002-12-10
申请号：US09477306
申请日：2000-01-04
申请人： Chok J. Chia , Seng-Sooi Lim , Patrick Variot
发明人： Chok J. Chia , Seng-Sooi Lim , Patrick Variot
IPC分类号： H01L2348
CPC分类号： H01L23/5382 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H05K1/029 , H05K2201/0949 , H05K2203/049 , H05K2203/173 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A programmable substrate and a method of making a programmable substrate for use with array-type packages, including Ball Grid Arrays(BGA), Pin Grid Arrays (PGA) and Column Grid Arrays (CGA) includes a nonconductive programmable substrate with a cavity in the top of the substrate. The cavity is sized to receive an integrated circuit (IC) die. An array of electrically conductive vias pass through the substrate. A plurality of electrical traces are formed on the top of the substrate. The traces extend radially from an edge of the die cavity to the periphery of the substrate so as to pass between and near the vias. Each trace is electrically connected to a pad of the IC die by a wire bond. Each via is connected on a bottom surface of the substrate to a solder ball, pin, or other means for electrically and mechanically attaching the substrate to a printed circuit board. The traces are programmably connected to a selected via, e.g., using wire bonds between the trace and a nearby selected via, thereby allowing each pad of the IC die to be selectively connected to a desired via, and hence to a selected solder ball or pin.
摘要翻译：一种可编程衬底和一种用于阵列型封装的可编程衬底的方法，包括球栅阵列（BGA），引脚栅格阵列（PGA）和柱栅阵列（CGA），包括一个非导电可编程衬底，衬底顶部。空腔的大小适于接收集成电路（IC）模具。一组导电通孔穿过基板。多个电迹线形成在基板的顶部。迹线从模腔的边缘径向延伸到衬底的周边，以便在通孔之间和附近通过。每个迹线通过引线键与IC芯片的焊盘电连接。每个通孔在基板的底表面上连接到焊球，销或用于将基板电气和机械地附接到印刷电路板的其它装置。迹线可编程地连接到所选择的通孔，例如，使用迹线和附近选定的通孔之间的引线键合，从而允许IC管芯的每个焊盘选择性地连接到期望的通孔，并且因此被选择性地连接到所选择的焊球或引脚。

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