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1. 发明授权

US5981311A Process for using a removeable plating bus layer for high density substrates 失效
标题翻译：使用可移除电镀总线层用于高密度基板的工艺
公开(公告)号：US5981311A
公开(公告)日：1999-11-09
申请号：US104838
申请日：1998-06-25
申请人： Chok J. Chia , Seng Sooi Lim , Patrick Variot
发明人： Chok J. Chia , Seng Sooi Lim , Patrick Variot
IPC分类号： H01L21/48 , H05K3/24 , H05K3/42 , H01L21/58 , H01L21/28 , H01L21/304
CPC分类号： H05K3/242 , H01L21/4846 , H05K3/428 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H05K2203/0191 , H05K2203/0361 , H05K2203/1572
摘要： A method of electroplating a high density integrated circuit (IC) substrate using a removable plating bus including the steps of providing an IC substrate made of nonconductive material having a plurality of conductive traces formed on its surface. Attaching a removable plating bus to the IC substrate, covering the plurality of conductive traces. Forming through holes (or vias) in predetermined locations. The holes going through the removable plating bus and IC substrate, exposing edges of selected conductive traces in the holes. Plating the through holes with a conductive material (such as copper) that electrically connects the removable plating bus to the exposed edges of the traces in the holes. Coating the IC substrate (including the removable plating bus) with plating resist and selectively removing portions of the removable plating bus, along with the plating resist, to expose selected areas of traces on the IC substrate that require plating. Electroplating the exposed trace areas on the IC substrate with conductive material (such as gold or nickel) by using the removable plating bus as the electrical connection to the exposed metal traces and removing the removable plating bus after electroplating is finished.
摘要翻译：一种使用可移除电镀母线电镀高密度集成电路（IC）衬底的方法，包括以下步骤：提供由其表面上形成有多个导电迹线的非导电材料制成的IC衬底。将可移除的电镀母线安装到IC基板上，覆盖多个导电迹线。在预定位置形成通孔（或通孔）。穿过可移除电镀总线和IC基板的孔，暴露孔中选定导电迹线的边缘。用诸如铜的导电材料（例如铜）电镀通孔，其将可移除的电镀总线电连接到孔中的迹线的暴露边缘。用电镀抗蚀剂涂覆IC基板（包括可移除电镀总线），并与电镀抗蚀剂一起选择性地去除可移除电镀母线的部分，以暴露需要电镀的IC基板上的选定区域的痕迹。通过使用可移除的电镀母线作为与暴露的金属迹线的电气连接，并且在电镀完成之后移除可移除的电镀母线，用导电材料（例如金或镍）电镀IC衬底上的暴露痕迹区域。

2. 发明授权

US06492253B1 Method for programming a substrate for array-type packages 有权
标题翻译：用于对阵列型封装的衬底进行编程的方法
公开(公告)号：US06492253B1
公开(公告)日：2002-12-10
申请号：US09477306
申请日：2000-01-04
申请人： Chok J. Chia , Seng-Sooi Lim , Patrick Variot
发明人： Chok J. Chia , Seng-Sooi Lim , Patrick Variot
IPC分类号： H01L2348
CPC分类号： H01L23/5382 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H05K1/029 , H05K2201/0949 , H05K2203/049 , H05K2203/173 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A programmable substrate and a method of making a programmable substrate for use with array-type packages, including Ball Grid Arrays(BGA), Pin Grid Arrays (PGA) and Column Grid Arrays (CGA) includes a nonconductive programmable substrate with a cavity in the top of the substrate. The cavity is sized to receive an integrated circuit (IC) die. An array of electrically conductive vias pass through the substrate. A plurality of electrical traces are formed on the top of the substrate. The traces extend radially from an edge of the die cavity to the periphery of the substrate so as to pass between and near the vias. Each trace is electrically connected to a pad of the IC die by a wire bond. Each via is connected on a bottom surface of the substrate to a solder ball, pin, or other means for electrically and mechanically attaching the substrate to a printed circuit board. The traces are programmably connected to a selected via, e.g., using wire bonds between the trace and a nearby selected via, thereby allowing each pad of the IC die to be selectively connected to a desired via, and hence to a selected solder ball or pin.
摘要翻译：一种可编程衬底和一种用于阵列型封装的可编程衬底的方法，包括球栅阵列（BGA），引脚栅格阵列（PGA）和柱栅阵列（CGA），包括一个非导电可编程衬底，衬底顶部。空腔的大小适于接收集成电路（IC）模具。一组导电通孔穿过基板。多个电迹线形成在基板的顶部。迹线从模腔的边缘径向延伸到衬底的周边，以便在通孔之间和附近通过。每个迹线通过引线键与IC芯片的焊盘电连接。每个通孔在基板的底表面上连接到焊球，销或用于将基板电气和机械地附接到印刷电路板的其它装置。迹线可编程地连接到所选择的通孔，例如，使用迹线和附近选定的通孔之间的引线键合，从而允许IC管芯的每个焊盘选择性地连接到期望的通孔，并且因此被选择性地连接到所选择的焊球或引脚。

3. 发明授权

US6054767A Programmable substrate for array-type packages 失效
标题翻译：用于阵列型封装的可编程衬底
公开(公告)号：US6054767A
公开(公告)日：2000-04-25
申请号：US6584
申请日：1998-01-13
申请人： Chok J. Chia , Seng-Sooi Lim , Patrick Variot
发明人： Chok J. Chia , Seng-Sooi Lim , Patrick Variot
IPC分类号： H01L23/538 , H05K1/00 , H01L23/48
CPC分类号： H01L23/5382 , H05K1/029 , H01L2224/05554 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L24/48 , H01L24/49 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H05K2201/0949 , H05K2203/049 , H05K2203/173
摘要： A programmable substrate and a method of making a programmable substrate for use with array-type packages, including Ball Grid Arrays(BGA), Pin Grid Arrays (PGA) and Column Grid Arrays (CGA) includes a nonconductive programmable substrate with a cavity in the top of the substrate. The cavity is sized to receive an integrated circuit (IC) die. An array of electrically conductive vias pass through the substrate. A plurality of electrical traces are formed on the top of the substrate. The traces extend radially from an edge of the die cavity to the periphery of the substrate so as to pass between and near the vias. Each trace is electrically connected to a pad of the IC die by a wire bond. Each via is connected on a bottom surface of the substrate to a solder ball, pin, or other means for electrically and mechanically attaching the substrate to a printed circuit board. The traces are programmably connected to a selected via, e.g., using wire bonds between the trace and a nearby selected via, thereby allowing each pad of the IC die to be selectively connected to a desired via, and hence to a selected solder ball or pin.
摘要翻译：一种可编程衬底和一种用于阵列型封装的可编程衬底的方法，包括球栅阵列（BGA），引脚栅格阵列（PGA）和柱栅阵列（CGA），包括一个非导电可编程衬底，衬底顶部。空腔的大小适于接收集成电路（IC）裸片。一组导电通孔穿过基板。多个电迹线形成在基板的顶部。迹线从模腔的边缘径向延伸到衬底的周边，以便在通孔之间和附近通过。每个迹线通过引线键与IC芯片的焊盘电连接。每个通孔在基板的底表面上连接到焊球，销或用于将基板电气和机械地附接到印刷电路板的其它装置。迹线可编程地连接到所选择的通孔，例如，使用迹线和附近选定的通孔之间的引线键合，从而允许IC管芯的每个焊盘选择性地连接到期望的通孔，并且因此被选择性地连接到所选择的焊球或引脚。

4. 发明授权

US06512293B1 Mechanically interlocking ball grid array packages and method of making 失效
标题翻译：机械联锁球栅阵列封装及制作方法
公开(公告)号：US06512293B1
公开(公告)日：2003-01-28
申请号：US09875055
申请日：2001-06-05
申请人： Chok J. Chia , Seng Sooi Lim , Wee K. Liew
发明人： Chok J. Chia , Seng Sooi Lim , Wee K. Liew
IPC分类号： H01L2304
CPC分类号： H01L23/544 , H01L23/49816 , H01L25/105 , H01L2223/54473 , H01L2223/54486 , H01L2225/1005 , H01L2924/15162 , H05K1/181 , H05K2201/10537 , H05K2201/10734 , Y02P70/611
摘要： A method and apparatus for providing a ball grid array assembly formed from interlocking ball grid array packages is disclosed. Each of the ball grid array packages has interlocking edge features for mechanical connection, whereby joining the plurality of ball grid array packages via the interlocking edge features forms the interlocking ball grid array assembly. The interlocking ball grid array assembly may then be mounted on a PC board as a single unit.
摘要翻译：公开了一种用于提供由联锁球栅阵列封装形成的球栅阵列组件的方法和装置。每个球栅阵列封装具有用于机械连接的互锁边缘特征，由此通过互锁边缘特征连接多个球栅阵列封装形成互锁球栅阵列组件。联锁球栅阵列组件然后可以作为单个单元安装在PC板上。

5. 发明授权

US6040632A Multiple sized die 失效
标题翻译：多尺寸模具
公开(公告)号：US6040632A
公开(公告)日：2000-03-21
申请号：US6784
申请日：1998-01-14
申请人： Qwai H. Low , Chok J. Chia , Seng-Sooi Lim
发明人： Qwai H. Low , Chok J. Chia , Seng-Sooi Lim
IPC分类号： H01L23/485 , H01L27/10
CPC分类号： H01L24/02 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/14 , H01L2924/19043
摘要： A multiple-sized integrated circuit (IC) die and a method of making a multiple-sized IC die includes forming a plurality of IC dies on a semiconductor wafer. Each IC die has multiple rows of bonding pads around its periphery. Adjacent bonding pads on separate rows of each IC die are electrically connected together so that attachment to any one of the connected bond pads yields the same result. A plurality of scribe streets separate each IC die on the wafer, with the scribe street defining the width between each IC die. Rows of bonding pads reside in the scribe street area. Different rows of bonding pads may be selectively removed from the IC die by scribing the wafer so as to include one or more of the rows of bonding pads, thereby allowing one IC die design to have multiple sizes. An IC die separated from the wafer may still be sized smaller as long as there remain at least two rows of bonding pads around the periphery.
摘要翻译：多尺寸集成电路（IC）管芯和制造多尺寸IC管芯的方法包括在半导体晶片上形成多个IC管芯。每个IC芯片周围都有多排接合焊盘。每个IC管芯的独立行上的相邻接合焊盘电连接在一起，使得连接到任何一个连接的接合焊盘产生相同的结果。多个划线区将晶片上的每个IC芯片分开，划线条限定每个IC芯片之间的宽度。焊盘行位于划痕街区域。可以通过划片晶片来选择性地从IC芯片去除不同行的焊盘，以便包括一行或多行接合焊盘，从而允许一个IC管芯设计具有多个尺寸。只要在周围保持至少两排接合焊盘，则与晶片分离的IC裸片仍可具有更小的尺寸。

6. 发明授权

US5927505A Overmolded package body on a substrate 失效
标题翻译：包覆成型的包装体在基材上
公开(公告)号：US5927505A
公开(公告)日：1999-07-27
申请号：US920430
申请日：1997-08-29
申请人： Chok J. Chia , Seng-Sooi Lim , Maniam Alagaratnam
发明人： Chok J. Chia , Seng-Sooi Lim , Maniam Alagaratnam
IPC分类号： B29C45/14 , H01L21/56 , H01L23/31 , B65D73/02 , H01L23/04
CPC分类号： B29C45/14418 , B29C45/14655 , H01L21/565 , H01L23/3121 , B29C2045/14934 , B29C70/72 , B29C70/78 , H01L2924/0002
摘要： Substrates having a wide range of thickness, and intended to be overmolded with a plastic package body, are accommodated in a common mold. The top surface of the substrate is provided with a dam structure, which may be formed as an additional layer on the substrate, and which is preferably in the form of a square ring. A groove (channel) is machined (e.g., by routing) into the surface of the dam structure. The top mold half, having a cavity for forming the package body, is provided with a sealing structure at the periphery of the cavity. The sealing structure has a ridge fitting into the channel of the dam structure. The depth of the groove in the dam structure is readily adjusted to ensure uniform clamping pressure of the top mold half on the substrate, so that liquid molding compound is contained within the cavity and so that undue pressure is not exerted on the substrate.
摘要翻译：具有宽范围厚度并且旨在用塑料封装体包覆成型的基板容纳在共同的模具中。衬底的顶表面设置有坝结构，其可以在衬底上形成为附加层，并且其优选地为正方形环的形式。槽（通道）被加工（例如通过路由）到坝结构的表面中。具有用于形成封装主体的空腔的顶部模具半部在空腔的周边处设置有密封结构。密封结构具有嵌入坝结构通道的脊。容易调节坝结构中槽的深度，以确保上模半部在基板上的均匀夹紧压力，使得液体模塑料被包含在空腔内，从而不会对衬底施加过大的压力。

7. 发明授权

US5568683A Method of cooling a packaged electronic device 失效
标题翻译：冷却电子装置的方法
公开(公告)号：US5568683A
公开(公告)日：1996-10-29
申请号：US472320
申请日：1995-06-07
申请人： Chok J. Chia , Manian Alagaratnam , Qwai H. Low , Seng-Sooi Lim
发明人： Chok J. Chia , Manian Alagaratnam , Qwai H. Low , Seng-Sooi Lim
IPC分类号： F02F7/00 , H01L23/367 , H01L23/40 , H05K3/30
CPC分类号： H01L23/40 , F02F7/00 , H01L23/3675 , H01L2924/0002 , Y10T29/4913
摘要： A removable heatsink assembly comprised of a heatsink unit and a heatspreader is provided. The heatsink unit has at least one fin and a coupling collar for radiating heat away from a packaged electronic device. The heatspreader includes a platform attached to an inner collar in thermal contact with the packaged electronic device. The platform has one or more tabs suitable for mating with one or more flanges located on the coupling collar of the heatsink unit. Coupling grooves within the flanges engage the platform of the heatspreader when the flanges are mated with the heatspreader tabs and the heatsink is turned. The heatsink can therefore be quickly and conveniently attached to or removed from the heatspreader. The present invention thus permits a wide variety of different heatsinks to be interchangeably used with a single heatspreader attached to an electronic device package.
摘要翻译：提供了由散热器单元和散热器组成的可拆卸的散热器组件。散热器单元具有至少一个翅片和用于从封装的电子设备辐射热量的联接套环。散热器包括附接到与封装的电子设备热接触的内部套环的平台。该平台具有一个或多个适合于与位于散热器单元的联接环上的一个或多个凸缘相配合的凸片。当凸缘与散热片接头配合并且散热片转动时，凸缘内的耦合凹槽接合散热器的平台。因此，散热器可以快速方便地附接到散热器或从散热器移除。因此，本发明允许各种不同的散热器与附接到电子设备封装的单个散热器可互换地使用。

8. 发明授权

US5521427A Printed wiring board mounted semiconductor device having leadframe with alignment feature 失效
标题翻译：印刷线路板安装的半导体器件具有引导框架，具有对准特征
公开(公告)号：US5521427A
公开(公告)日：1996-05-28
申请号：US340807
申请日：1994-11-17
申请人： Chok J. Chia , Seng-Sooi Lim
发明人： Chok J. Chia , Seng-Sooi Lim
IPC分类号： H01L23/495 , H05K3/30 , H05K3/34 , H01L23/544
CPC分类号： H05K3/303 , H01L23/49541 , H01L2224/48091 , H01L2224/48247 , H05K2201/10303 , H05K2201/10659 , H05K2201/10689 , H05K2201/10962 , H05K2203/167 , H05K3/3421 , Y02P70/613 , Y10S438/975 , Y10T29/49121 , Y10T29/49133
摘要： A packaged semiconductor device, leadframe for making same, and method of mounting same to a printed circuit board are described. The device has a body, and a plurality of leads extending from the body. One or more alignment features are formed on the exterior of the package body, for maintaining precise alignment of the device with respect to a printed wiring board. The alignment feature is a tab formed as part of portion of the leadframe external to the package body. The tab may have various shapes, and may be provided with a hole for registering with a pin on an underlying substrate, such as a printed wiring board. The pin and the tab may be electrically connected.
摘要翻译：描述了一种封装的半导体器件，用于制造其的引线框，以及将其安装到印刷电路板的方法。该装置具有主体和从主体延伸的多个引线。一个或多个对准特征形成在包装体的外部上，以保持装置相对于印刷线路板的精确对准。对准特征是形成为包装体外部的引线框架的一部分的突片。突片可以具有各种形状，并且可以设置有用于与诸如印刷线路板的下面的基板上的销对准的孔。引脚和突片可以电连接。

9. 发明授权

US5463529A High power dissipating packages with matched heatspreader heatsink assemblies 失效
标题翻译：具有匹配散热器散热器组件的大功率消散封装
公开(公告)号：US5463529A
公开(公告)日：1995-10-31
申请号：US317968
申请日：1994-10-04
申请人： Chok J. Chia , Manian Alagaratnam , Qwai H. Low , Seng-Sooi Lim
发明人： Chok J. Chia , Manian Alagaratnam , Qwai H. Low , Seng-Sooi Lim
IPC分类号： F02F7/00 , H01L23/367 , H01L23/40 , H05K7/20
CPC分类号： H01L23/40 , F02F7/00 , H01L23/3675 , H01L2924/0002 , Y10T29/4913
摘要： A removable heatsink assembly comprised of a heatsink unit and a heatspreader is provided. The heatsink unit has at least one fin and a coupling collar for radiating heat away from a packaged electronic device. The heatspreader includes a platform attached to an inner collar in thermal contact with the packaged electronic device. The platform has one or more tabs suitable for mating with one or more flanges located on the coupling collar of the heatsink unit. Coupling grooves within the flanges engage the platform of the heatspreader when the flanges are mated with the heatspreader tabs and the heatsink is turned. The heatsink can therefore be quickly and conveniently attached to or removed from the heatspreader. The present invention thus permits a wide variety of different heatsinks to be interchangeably used with a single heatspreader attached to an electronic device package.
摘要翻译：提供了由散热器单元和散热器组成的可拆卸的散热器组件。散热器单元具有至少一个翅片和用于从封装的电子设备辐射热量的联接套环。散热器包括附接到与封装的电子设备热接触的内部套环的平台。该平台具有一个或多个适合于与位于散热器单元的联接环上的一个或多个凸缘相配合的凸片。当凸缘与散热片接头配合并且散热片转动时，凸缘内的耦合凹槽接合散热器的平台。因此，散热器可以快速方便地附接到散热器或从散热器移除。因此，本发明允许各种不同的散热器与附接到电子设备封装的单个散热器可互换地使用。

10. 发明授权

US5262927A Partially-molded, PCB chip carrier package 失效
标题翻译：部分成型，PCB芯片载体封装
公开(公告)号：US5262927A
公开(公告)日：1993-11-16
申请号：US834182
申请日：1992-02-07
申请人： Chok J. Chia , Seng-Sooi Lim
发明人： Chok J. Chia , Seng-Sooi Lim
IPC分类号： H01L23/12 , G03F7/20 , H01L23/31 , H01L23/495 , H01L23/498 , H01L23/50 , H01L29/06 , H05K1/11
CPC分类号： G03F7/70433 , H01L23/3121 , H01L23/49517 , H01L23/49541 , H01L23/49861 , H01L2224/48091 , H01L2224/48247 , H01L2224/49109 , H01L24/48 , H01L24/49 , H01L29/0657 , H01L2924/00014 , H01L2924/01014 , H01L2924/01078 , H01L2924/14 , H01L2924/15151 , H01L2924/15153 , H01L2924/1517 , H01L2924/1532 , H01L2924/181 , H01L2924/18301
摘要： A dambar-less leadframe is sandwiched between two printed circuit boards (PCBs). The PCBs form a major portion of the package body, and isolate the leadframe leads from plastic molding compound. In one embodiment, an upper PCB (substrate) is formed as a square ring, having an opening containing a heat sink element. A lower PCB is also formed as a square ring, and has a smaller opening for receiving a die. The back face of the die is mounted to the heat sink. The exposed front face of the die is wire bonded to inner ends of conductive traces on the exposed face of the lower PCB. The outer ends of the traces are electrically connected to the leadframe leads by plated-through vias extending through the two PCBs. The plated-through vias additionally secure the sandwich structure together. Plastic molding compound is injection/transfer molded over the front face of the die and the bond wires, forming a partially-molded package. In another embodiment, the upper PCB is a solid planar element, and is not provided with an opening for a heat sink. The back face of the die is mounted to the inside surface of the upper PCB.

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