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1. 发明授权

US06963138B2 Dielectric stack 有权
标题翻译：电介质堆
公开(公告)号：US06963138B2
公开(公告)日：2005-11-08
申请号：US10357142
申请日：2003-02-03
申请人： Qwai H. Low , Chok J. Chia , Ramaswamy Ranganathan , Tauman T. Lau
发明人： Qwai H. Low , Chok J. Chia , Ramaswamy Ranganathan , Tauman T. Lau
IPC分类号： H01L23/485 , H01L23/532 , H01L23/48
CPC分类号： H01L24/05 , H01L23/53295 , H01L2224/05093 , H01L2224/05556 , H01L2224/05624 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/04953 , H01L2924/14 , H01L2924/181 , H01L2924/30105 , H01L2924/00
摘要： An integrated circuit with a pressure resistant current carrying structure having electrically conductive layers for carrying current. A first electrically nonconductive material at least partially surrounds the electrically conductive layers, and provides electrical insulation between the electrically conductive layers. The first electrically nonconductive material has a first degree of fragility and a first dielectric constant. A second electrically nonconductive material is disposed in a pattern within the first electrically nonconductive material and between the electrically conductive layers, and provides structural support for the first electrically nonconductive material between the electrically conductive layers. The second electrically nonconductive material has a second degree of fragility that is less than the first degree of fragility and a second dielectric constant that is greater than the first dielectric constant.
摘要翻译：一种具有耐压载流结构的集成电路，其具有用于承载电流的导电层。第一非导电材料至少部分地围绕导电层，并且在导电层之间提供电绝缘。第一非导电材料具有第一程度的脆性和第一介电常数。第二非导电材料以第一非导电材料内部和导电层之间的图案设置，并为导电层之间的第一非导电材料提供结构支撑。第二非导电材料具有小于第一脆性程度的第二脆性程度和大于第一介电常数的第二介电常数。

2. 发明授权

US06743979B1 Bonding pad isolation 有权
标题翻译：粘接垫隔离
公开(公告)号：US06743979B1
公开(公告)日：2004-06-01
申请号：US10652453
申请日：2003-08-29
申请人： Michael J. Berman , Aftab Ahmad , Qwai H. Low , Chok J. Chia , Ramaswamy Ranganathan
发明人： Michael J. Berman , Aftab Ahmad , Qwai H. Low , Chok J. Chia , Ramaswamy Ranganathan
IPC分类号： H05K506
CPC分类号： H01L24/06 , H01L24/05 , H01L2224/04042 , H01L2224/05554 , H01L2224/05556 , H01L2224/05599 , H01L2224/48091 , H01L2224/48227 , H01L2224/48463 , H01L2224/49431 , H01L2224/85399 , H01L2924/00014 , H01L2924/01033 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2224/45099 , H01L2924/00012
摘要： An integrated circuit, including a substrate with circuitry formed therein, where the substrate has a peripheral edge. Also included are a top most electrically conductive layer and an underlying electrically conductive layer. Outer bonding pads are disposed in an outer ring, and are formed within the top most layer. Inner bonding pads are disposed in an inner ring, and are formed within the top most layer. Inner connectors electrically connect the inner bonding pads to the circuitry. The inner connectors are formed within the underlying layer, and have a width that is less than the width of the inner bonding pads, thereby defining a gap between the inner connectors. Outer connectors electrically connect the outer bonding pads to the circuitry. The outer connectors are formed within the underlying layer, and have a width that is less than the width of the gap between the inner connectors.
摘要翻译：一种集成电路，包括其中形成有电路的衬底，其中衬底具有外围边缘。还包括最顶层的导电层和底层导电层。外部接合焊盘设置在外圈中，并形成在最上层。内部接合焊盘设置在内圈中，并且形成在最顶层内。内部连接器将内部接合焊盘电连接到电路。内部连接器形成在下面的层中，并且具有小于内部焊盘的宽度的宽度，由此限定内部连接器之间的间隙。外部连接器将外部接合焊盘电连接到电路。外部连接器形成在下面的层中，并且具有小于内部连接器之间的间隙的宽度的宽度。

3. 发明授权

US06861343B2 Buffer metal layer 失效
标题翻译：缓冲金属层
公开(公告)号：US06861343B2
公开(公告)日：2005-03-01
申请号：US10267410
申请日：2002-10-09
申请人： Chok J. Chia , Qwai H. Low , Ramaswamy Ranganathan
发明人： Chok J. Chia , Qwai H. Low , Ramaswamy Ranganathan
IPC分类号： H01L23/367 , H01L23/373 , H01L23/522 , H01L23/552 , H01L21/44
CPC分类号： H01L23/552 , H01L23/367 , H01L23/3735 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit having a top passivation layer and bonding pads, where the improvement is a metal layer overlying all of the integrated circuit. The metal layer overlies the top passivation layer and is not in electrical contact with any of the bonding pads. In this manner, there is a structure that is added to the integrated circuit which has a relatively high thermal conductivity, and which also has a relatively high structural strength. With these two added properties, the occurrence of stress cracks, such as those induced by plastic molded packages, is reduced, and hot spots tend to be dissipated. Thus, the overlying metal layer tends to improve the reliability of the integrated circuit.
摘要翻译：具有顶部钝化层和接合焊盘的集成电路，其中改进是覆盖所有集成电路的金属层。金属层覆盖在顶部钝化层上，并且不与任何焊盘焊接。以这种方式，具有添加到具有相对较高导热性并且还具有相对较高的结构强度的集成电路的结构。通过这两个添加的性质，减少了由塑料模制包装引起的应力裂纹的发生，并且热点趋于消散。因此，上覆金属层倾向于提高集成电路的可靠性。

4. 发明授权

US06425179B1 Method for assembling tape ball grid arrays 有权
标题翻译：胶带球栅阵列组装方法
公开(公告)号：US06425179B1
公开(公告)日：2002-07-30
申请号：US09417255
申请日：1999-10-12
申请人： Qwai H. Low , Chok J. Chia , Ramaswamy Ranganathan
发明人： Qwai H. Low , Chok J. Chia , Ramaswamy Ranganathan
IPC分类号： H01L21/60 , H01L23/00 , H05K3/34
CPC分类号： H01L24/86 , H01L23/562 , H01L2924/01029 , H01L2924/01033 , H01L2924/014 , H01L2924/14 , H01L2924/181 , Y10T29/49144 , Y10T29/49146 , Y10T29/49147 , Y10T29/49155 , H01L2924/00
摘要： According to the present invention, a method for creating a package for a semiconductor die, the package comprising a flexible tape, comprises the following steps. A support with an opening has a plurality of arms extending through at a portion of the opening. For example, for a square opening, there may be eight arms, two extending from each side of the opening. The arms preferably form a “z” shape or some other shape with a transverse component. The flexible tape is then attached to the ends of the arms within the opening such that the flexible tape is supported by the arms. A die is attached to the flexible tape, the die is preferably covered with a molding compound, and the die/flexible tape assembly is scribed from the support, thereby creating an individual package.
摘要翻译：根据本发明，一种用于制造用于半导体管芯的封装的方法，包括柔性带的封装包括以下步骤。具有开口的支撑件具有在开口的一部分延伸穿过的多个臂。例如，对于方形开口，可以有八个臂，两个从开口的每一侧延伸。臂优选地形成具有横向分量的“z”形或一些其它形状。然后将柔性带附接到开口内的臂的端部，使得柔性带由臂支撑。将模具附接到柔性带上，模具优选用模制化合物覆盖，并且模具/柔性带组件从支撑件划刻，从而形成单独的包装。

5. 发明授权

US5463529A High power dissipating packages with matched heatspreader heatsink assemblies 失效
标题翻译：具有匹配散热器散热器组件的大功率消散封装
公开(公告)号：US5463529A
公开(公告)日：1995-10-31
申请号：US317968
申请日：1994-10-04
申请人： Chok J. Chia , Manian Alagaratnam , Qwai H. Low , Seng-Sooi Lim
发明人： Chok J. Chia , Manian Alagaratnam , Qwai H. Low , Seng-Sooi Lim
IPC分类号： F02F7/00 , H01L23/367 , H01L23/40 , H05K7/20
CPC分类号： H01L23/40 , F02F7/00 , H01L23/3675 , H01L2924/0002 , Y10T29/4913
摘要： A removable heatsink assembly comprised of a heatsink unit and a heatspreader is provided. The heatsink unit has at least one fin and a coupling collar for radiating heat away from a packaged electronic device. The heatspreader includes a platform attached to an inner collar in thermal contact with the packaged electronic device. The platform has one or more tabs suitable for mating with one or more flanges located on the coupling collar of the heatsink unit. Coupling grooves within the flanges engage the platform of the heatspreader when the flanges are mated with the heatspreader tabs and the heatsink is turned. The heatsink can therefore be quickly and conveniently attached to or removed from the heatspreader. The present invention thus permits a wide variety of different heatsinks to be interchangeably used with a single heatspreader attached to an electronic device package.
摘要翻译：提供了由散热器单元和散热器组成的可拆卸的散热器组件。散热器单元具有至少一个翅片和用于从封装的电子设备辐射热量的联接套环。散热器包括附接到与封装的电子设备热接触的内部套环的平台。该平台具有一个或多个适合于与位于散热器单元的联接环上的一个或多个凸缘相配合的凸片。当凸缘与散热片接头配合并且散热片转动时，凸缘内的耦合凹槽接合散热器的平台。因此，散热器可以快速方便地附接到散热器或从散热器移除。因此，本发明允许各种不同的散热器与附接到电子设备封装的单个散热器可互换地使用。

6. 发明授权

US6040632A Multiple sized die 失效
标题翻译：多尺寸模具
公开(公告)号：US6040632A
公开(公告)日：2000-03-21
申请号：US6784
申请日：1998-01-14
申请人： Qwai H. Low , Chok J. Chia , Seng-Sooi Lim
发明人： Qwai H. Low , Chok J. Chia , Seng-Sooi Lim
IPC分类号： H01L23/485 , H01L27/10
CPC分类号： H01L24/02 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/14 , H01L2924/19043
摘要： A multiple-sized integrated circuit (IC) die and a method of making a multiple-sized IC die includes forming a plurality of IC dies on a semiconductor wafer. Each IC die has multiple rows of bonding pads around its periphery. Adjacent bonding pads on separate rows of each IC die are electrically connected together so that attachment to any one of the connected bond pads yields the same result. A plurality of scribe streets separate each IC die on the wafer, with the scribe street defining the width between each IC die. Rows of bonding pads reside in the scribe street area. Different rows of bonding pads may be selectively removed from the IC die by scribing the wafer so as to include one or more of the rows of bonding pads, thereby allowing one IC die design to have multiple sizes. An IC die separated from the wafer may still be sized smaller as long as there remain at least two rows of bonding pads around the periphery.
摘要翻译：多尺寸集成电路（IC）管芯和制造多尺寸IC管芯的方法包括在半导体晶片上形成多个IC管芯。每个IC芯片周围都有多排接合焊盘。每个IC管芯的独立行上的相邻接合焊盘电连接在一起，使得连接到任何一个连接的接合焊盘产生相同的结果。多个划线区将晶片上的每个IC芯片分开，划线条限定每个IC芯片之间的宽度。焊盘行位于划痕街区域。可以通过划片晶片来选择性地从IC芯片去除不同行的焊盘，以便包括一行或多行接合焊盘，从而允许一个IC管芯设计具有多个尺寸。只要在周围保持至少两排接合焊盘，则与晶片分离的IC裸片仍可具有更小的尺寸。

7. 发明授权

US5568683A Method of cooling a packaged electronic device 失效
标题翻译：冷却电子装置的方法
公开(公告)号：US5568683A
公开(公告)日：1996-10-29
申请号：US472320
申请日：1995-06-07
申请人： Chok J. Chia , Manian Alagaratnam , Qwai H. Low , Seng-Sooi Lim
发明人： Chok J. Chia , Manian Alagaratnam , Qwai H. Low , Seng-Sooi Lim
IPC分类号： F02F7/00 , H01L23/367 , H01L23/40 , H05K3/30
CPC分类号： H01L23/40 , F02F7/00 , H01L23/3675 , H01L2924/0002 , Y10T29/4913
摘要： A removable heatsink assembly comprised of a heatsink unit and a heatspreader is provided. The heatsink unit has at least one fin and a coupling collar for radiating heat away from a packaged electronic device. The heatspreader includes a platform attached to an inner collar in thermal contact with the packaged electronic device. The platform has one or more tabs suitable for mating with one or more flanges located on the coupling collar of the heatsink unit. Coupling grooves within the flanges engage the platform of the heatspreader when the flanges are mated with the heatspreader tabs and the heatsink is turned. The heatsink can therefore be quickly and conveniently attached to or removed from the heatspreader. The present invention thus permits a wide variety of different heatsinks to be interchangeably used with a single heatspreader attached to an electronic device package.
摘要翻译：提供了由散热器单元和散热器组成的可拆卸的散热器组件。散热器单元具有至少一个翅片和用于从封装的电子设备辐射热量的联接套环。散热器包括附接到与封装的电子设备热接触的内部套环的平台。该平台具有一个或多个适合于与位于散热器单元的联接环上的一个或多个凸缘相配合的凸片。当凸缘与散热片接头配合并且散热片转动时，凸缘内的耦合凹槽接合散热器的平台。因此，散热器可以快速方便地附接到散热器或从散热器移除。因此，本发明允许各种不同的散热器与附接到电子设备封装的单个散热器可互换地使用。

8. 发明授权

US08525312B2 Area array quad flat no-lead (QFN) package 有权
标题翻译：区域阵列四边形无引线（QFN）封装
公开(公告)号：US08525312B2
公开(公告)日：2013-09-03
申请号：US13208822
申请日：2011-08-12
申请人： Qwai H. Low , Chok J. Chia , Kishor Desai , Charles G. Woychik , Huailiang Wei
发明人： Qwai H. Low , Chok J. Chia , Kishor Desai , Charles G. Woychik , Huailiang Wei
IPC分类号： H01L23/495 , H01L21/50 , H01L21/60
CPC分类号： H01L23/49537 , H01L21/4821 , H01L23/3121 , H01L23/49575 , H01L23/49861 , H01L24/73 , H01L24/97 , H01L2224/0401 , H01L2224/04042 , H01L2224/16245 , H01L2224/32145 , H01L2224/32245 , H01L2224/45014 , H01L2224/48247 , H01L2224/48465 , H01L2224/48471 , H01L2224/49171 , H01L2224/73265 , H01L2224/97 , H01L2924/01322 , H01L2924/01327 , H01L2924/07811 , H01L2924/12042 , H01L2924/1434 , H01L2924/1436 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/85 , H01L2224/81 , H01L2224/83
摘要： A microelectronic assembly can include a microelectronic element and a lead frame having a first unit and a second unit overlying the first unit and assembled therewith. The first unit can have a first metal layer comprising a portion of the thickness of the lead frame and including terminals and first conductive elements extending away therefrom. The second unit can have a second metal layer comprising a portion of the thickness of the lead frame and including bond pads and second conductive elements extending away therefrom. The first and second units each can have an encapsulation supporting at least portions of the respective first and second conductive elements. At least some of the second conductive elements can overlie portions of corresponding ones of the first conductive elements and can be joined thereto. The microelectronic element can have contacts electrically connected with the bond pads of the lead frame.
摘要翻译：微电子组件可以包括微电子元件和引线框架，引线框架具有覆盖第一单元并与其组装的第一单元和第二单元。第一单元可以具有包括引线框架的厚度的一部分的第一金属层，并且包括端子和从其延伸的第一导电元件。第二单元可以具有包括引线框架的厚度的一部分的第二金属层，并且包括接合焊盘和从其延伸的第二导电元件。第一和第二单元各自可以具有支撑相应的第一和第二导电元件的至少一部分的封装。至少一些第二导电元件可以覆盖相应的第一导电元件的部分并且可以与其连接。微电子元件可以具有与引线框架的接合焊盘电连接的触点。

9. 发明申请

US20130037925A1 AREA ARRAY QFN 有权
标题翻译：区域阵列QFN
公开(公告)号：US20130037925A1
公开(公告)日：2013-02-14
申请号：US13208822
申请日：2011-08-12
申请人： Qwai H. Low , Chok J. Chia , Kishor Desai , Charles G. Woychik , Huailiang Wei
发明人： Qwai H. Low , Chok J. Chia , Kishor Desai , Charles G. Woychik , Huailiang Wei
IPC分类号： H01L23/495 , H01L21/50 , H01L21/60
CPC分类号： H01L23/49537 , H01L21/4821 , H01L23/3121 , H01L23/49575 , H01L23/49861 , H01L24/73 , H01L24/97 , H01L2224/0401 , H01L2224/04042 , H01L2224/16245 , H01L2224/32145 , H01L2224/32245 , H01L2224/45014 , H01L2224/48247 , H01L2224/48465 , H01L2224/48471 , H01L2224/49171 , H01L2224/73265 , H01L2224/97 , H01L2924/01322 , H01L2924/01327 , H01L2924/07811 , H01L2924/12042 , H01L2924/1434 , H01L2924/1436 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/85 , H01L2224/81 , H01L2224/83
摘要： A microelectronic assembly can include a microelectronic element and a lead frame having a first unit and a second unit overlying the first unit and assembled therewith. The first unit can have a first metal layer comprising a portion of the thickness of the lead frame and including terminals and first conductive elements extending away therefrom. The second unit can have a second metal layer comprising a portion of the thickness of the lead frame and including bond pads and second conductive elements extending away therefrom. The first and second units each can have an encapsulation supporting at least portions of the respective first and second conductive elements. At least some of the second conductive elements can overlie portions of corresponding ones of the first conductive elements and can be joined thereto. The microelectronic element can have contacts electrically connected with the bond pads of the lead frame.
摘要翻译：微电子组件可以包括微电子元件和引线框架，引线框架具有覆盖第一单元并与其组装的第一单元和第二单元。第一单元可以具有包括引线框架的厚度的一部分的第一金属层，并且包括端子和从其延伸的第一导电元件。第二单元可以具有包括引线框架的厚度的一部分的第二金属层，并且包括接合焊盘和从其延伸的第二导电元件。第一和第二单元各自可以具有支撑相应的第一和第二导电元件的至少一部分的封装。至少一些第二导电元件可以覆盖相应的第一导电元件的部分并且可以与其连接。微电子元件可以具有与引线框架的接合焊盘电连接的触点。

10. 发明授权

US06603200B1 Integrated circuit package 失效
标题翻译：集成电路封装
公开(公告)号：US06603200B1
公开(公告)日：2003-08-05
申请号：US08928826
申请日：1997-09-12
申请人： Qwai H. Low , Chok J. Chia , Seng-Sooi (Allen) Lim
发明人： Qwai H. Low , Chok J. Chia , Seng-Sooi (Allen) Lim
IPC分类号： H01L23053
CPC分类号： H01L24/06 , H01L23/49838 , H01L24/48 , H01L24/49 , H01L2224/0401 , H01L2224/05554 , H01L2224/48227 , H01L2224/48233 , H01L2224/4911 , H01L2224/4912 , H01L2224/49171 , H01L2224/49431 , H01L2924/00014 , H01L2924/014 , H01L2924/14 , H01L2924/19107 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： An integrated circuit package includes a connector board and plural levels of individual conductors and conductive vias disposed through the connector board to form electrical connections between external connection pads on an undersurface of the connector board and finger connections on the upper surface of the connector board. An integrated circuit die is mounted in a central region of the connector board within confines of the individual conductors that are arranged about the die, and wire bond connections are formed between selected ones of the finger connections, the individual conductors, and the connection pads on the integrated circuit die to provide distributed connections for ground and power at one or more operating voltage levels on the individual conductors.
摘要翻译：集成电路封装包括连接器板和多层单独的导体以及通过连接器板设置的导电通路，以在连接器板的下表面上的外部连接焊盘和连接器板的上表面上的指状连接之间形成电连接。集成电路管芯安装在连接器板的中心区域，在围绕管芯布置的各个导体的限制范围内，并且引线接合连接形成在指状连接，各个导体和连接焊盘上的选定的导体之间集成电路管芯，以在单个导体上的一个或多个工作电压电平上提供用于接地和电力的分布式连接。

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