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31. 发明申请

US20100003813A1 Semiconductor device and method of fabricating the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20100003813A1
公开(公告)日：2010-01-07
申请号：US12585334
申请日：2009-09-11
申请人： Katsuyuki Sekine , Akio Kaneko , Motoyuki Sato , Seiji Inumiya , Kazuhiro Eguchi
发明人： Katsuyuki Sekine , Akio Kaneko , Motoyuki Sato , Seiji Inumiya , Kazuhiro Eguchi
IPC分类号： H01L21/28
CPC分类号： C23C16/401 , C23C16/56 , H01L21/02329 , H01L21/3145
摘要： According to the present invention, there is provided a semiconductor device comprising: a gate insulating film selectively formed on a predetermined region of a semiconductor substrate; a gate electrode formed on said gate insulating film; and a source region and drain region formed, in a surface portion of said semiconductor substrate, on two sides of a channel region positioned below said gate electrode, wherein a carbon concentration in an interface where said gate insulating film is in contact with said gate electrode is not more than 5×1022 atoms/cm3.
摘要翻译：根据本发明，提供了一种半导体器件，包括：选择性地形成在半导体衬底的预定区域上的栅极绝缘膜; 形成在所述栅极绝缘膜上的栅电极; 以及在所述半导体衬底的表面部分中形成在位于所述栅极电极下方的沟道区域的两侧上的源极区和漏极区，其中所述栅极绝缘膜与所述栅电极接触的界面中的碳浓度不大于5×1022原子/ cm3。

32. 发明授权

US07629243B2 Method for manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07629243B2
公开(公告)日：2009-12-08
申请号：US11487994
申请日：2006-07-18
申请人： Tsunehiro Ino , Akio Kaneko , Nobutoshi Aoki
发明人： Tsunehiro Ino , Akio Kaneko , Nobutoshi Aoki
IPC分类号： H01L21/4763
CPC分类号： H01L21/28202 , H01L21/268 , H01L21/2686 , H01L21/28035 , H01L21/2807 , H01L21/28176 , H01L21/28185 , H01L21/28194 , H01L29/511 , H01L29/517
摘要： A method for manufacturing a semiconductor device is provided, which includes forming a gate insulating film on a semiconductor substrate, forming a first layer on the gate insulating film, the first layer containing a first p-type impurity and, an amorphous or polycrystalline formed of Si1-xGex (0≦x
摘要翻译：提供一种制造半导体器件的方法，其包括在半导体衬底上形成栅极绝缘膜，在栅极绝缘膜上形成第一层，第一层包含第一p型杂质，以及由 Si1-xGex（0 <= x <0.25），对第一层进行第一热处理，其中第一层在高于1100℃的温度下加热1毫秒以下，在第一层上形成第二层所述第二层包含第二p型杂质并由非晶硅或多晶硅形成，所述第二p型杂质的共价键半径小于所述第一p型杂质的半值，并且使所述第二层经受第二层热处理以在800℃至1100℃的温度下加热第二层。

33. 发明授权

US07521309B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07521309B2
公开(公告)日：2009-04-21
申请号：US11948344
申请日：2007-11-30
申请人： Akio Kaneko , Motoyuki Sato , Katsuyuki Sekine , Tomohiro Saito , Kazuaki Nakajima , Tomonori Aoyama
发明人： Akio Kaneko , Motoyuki Sato , Katsuyuki Sekine , Tomohiro Saito , Kazuaki Nakajima , Tomonori Aoyama
IPC分类号： H01L21/336
CPC分类号： H01L29/517 , H01L21/28097 , H01L21/3215 , H01L21/823814 , H01L21/823835 , H01L21/823842 , H01L29/66507
摘要： A method of manufacturing a semiconductor device having a MOSFET of a first conductivity type and a MOSFET of a second conductivity type different from the first conductivity type formed on a semiconductor substrate, the method has: forming a gate insulating film; forming a first gate electrode layer, and forming a second gate electrode layer; forming a first metal containing layer on said first gate electrode layer and said second gate electrode layer; forming a second metal containing layer for preventing diffusion of a metal on said first metal containing layer; forming a third metal containing layer on said second gate electrode layer from which said first metal containing layer and said second metal containing layer are selectively removed, the third metal containing layer having a thickness different from the thickness of said first metal containing layer in a case where the third metal containing layer contains the same metal or alloy as the metal or alloy contained in said first metal containing layer; and performing a thermal processing, thereby causing reaction between the metal contained in said first metal containing layer and said first gate electrode layer to convert said first gate electrode layer into an alloy and causing reaction between the metal contained in said third metal containing layer and said second gate electrode layer to convert said second gate electrode layer into an alloy, thereby forming gate electrodes of different compositions.
摘要翻译：一种制造具有第一导电类型的MOSFET的半导体器件的方法和形成在半导体衬底上的与第一导电类型不同的第二导电类型的MOSFET，该方法具有：形成栅极绝缘膜; 形成第一栅电极层，形成第二栅电极层; 在所述第一栅电极层和所述第二栅电极层上形成第一含金属层; 形成用于防止金属在所述第一金属含有层上的扩散的第二含金属层; 在所述第二栅电极层上形成第三金属含有层，从所述第二金属含有层和所述第二金属含有层被选择性地除去，所述第三金属含有层的厚度与所述第一金属含有层的厚度不同其中所述第三含金属层包含与所述第一含金属层中所含的金属或合金相同的金属或合金; 并进行热处理，从而使包含在所述第一金属含有层中的金属与所述第一栅极电极层之间产生反应，将所述第一栅电极层转换成合金，并引起所述第三金属含有层中含有的金属与所述第二栅极电极层，以将所述第二栅电极层转换成合金，从而形成不同组成的栅电极。

34. 发明授权

US4629561A Liquid chromatograph with flow controller 失效
标题翻译：带流量控制器的液相色谱仪
公开(公告)号：US4629561A
公开(公告)日：1986-12-16
申请号：US703398
申请日：1985-02-20
申请人： Kozo Shirato , Kazuo Hiraizumi , Akio Kaneko , Akihiko Nagai
发明人： Kozo Shirato , Kazuo Hiraizumi , Akio Kaneko , Akihiko Nagai
IPC分类号： B01D15/08 , G01N30/32
CPC分类号： G01N30/32 , G01N2030/322 , G01N2030/324 , Y10T137/7788
摘要： A liquid chromatograph includes a solvent tank, a pump, a sample injection element, a column, a detector, conduits for successively interconnecting these elements, and a flow controller which is connected between the pump and the detector and in parallel with the column.
摘要翻译：液相色谱仪包括溶剂罐，泵，样品注射元件，色谱柱，检测器，用于连续地互连这些元件的管道，以及连接在泵和检测器之间并与塔并联的流量控制器。

35. 发明授权

US08039333B2 Semiconductor device and method of fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US08039333B2
公开(公告)日：2011-10-18
申请号：US12359974
申请日：2009-01-26
申请人： Akio Kaneko , Seiji Inumiya , Tomonori Aoyama , Takuya Kobayashi
发明人： Akio Kaneko , Seiji Inumiya , Tomonori Aoyama , Takuya Kobayashi
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/823807 , H01L21/0245 , H01L21/02532 , H01L21/02667 , H01L21/823431 , H01L21/82385 , H01L21/823857 , H01L27/0886 , H01L27/0922 , H01L29/1037 , H01L29/1054 , H01L29/665 , H01L29/6659 , H01L29/66651 , H01L29/66795 , H01L29/7834 , H01L29/7851 , H01L29/7853
摘要： A method of fabricating a semiconductor device according to one embodiment includes: forming a SiGe crystal layer on a semiconductor substrate, the SiGe crystal layer having a first plane and a second plane inclined with respect to the first plane; forming an amorphous Si film on the SiGe crystal layer; crystallizing a portion located adjacent to the first and second planes of the amorphous Si film by applying heat treatment using the first and second planes of the SiGe crystal layer as a seed, thereby forming a Si crystal layer; selectively removing or thinning a portion of the amorphous Si film that is not crystallized by the heat treatment; applying oxidation treatment to a surface of the Si crystal layer, thereby forming a gate insulating film on the surface of the Si crystal layer; and forming a gate electrode on the gate insulating film.
摘要翻译：根据一个实施例的制造半导体器件的方法包括：在半导体衬底上形成SiGe晶体层，所述SiGe晶体层具有第一平面和相对于第一平面倾斜的第二平面; 在SiGe晶体层上形成非晶Si膜; 通过使用SiGe晶体层的第一和第二平面作为种子进行热处理，使位于非晶Si膜的第一和第二平面附近的部分结晶，从而形成Si晶体层; 通过热处理选择性去除或稀薄未结晶的非晶Si膜的一部分; 对Si晶体层的表面进行氧化处理，从而在Si晶体层的表面上形成栅极绝缘膜; 以及在所述栅极绝缘膜上形成栅电极。

36. 发明授权

US07687869B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07687869B2
公开(公告)日：2010-03-30
申请号：US12081824
申请日：2008-04-22
申请人： Akio Kaneko , Seiji Inumiya , Katsuyuki Sekine , Kazuhiro Eguchi , Motoyuki Sato
发明人： Akio Kaneko , Seiji Inumiya , Katsuyuki Sekine , Kazuhiro Eguchi , Motoyuki Sato
IPC分类号： H01L29/78 , H01L21/8238
CPC分类号： H01L21/28194 , H01L21/28079 , H01L21/823842 , H01L21/823857 , H01L29/495 , H01L29/513 , H01L29/517 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device according to the present invention comprises a semiconductor substrate, a gate insulating film which is composed of a material whose main component is a tetravalent metal oxide, a mixture of a tetravalent metal oxide and SiO2, or a mixture of a tetravalent metal oxide and SiON and which containing B when it is in an nMOS structure on the semiconductor substrate or containing at least one of P and As when it is in a pMOS structure on the semiconductor substrate, and a gate electrode made of a metal having a work function of 4 eV to 5.5 eV.
摘要翻译：根据本发明的半导体器件包括半导体衬底，由主要成分为四价金属氧化物的材料，四价金属氧化物和SiO 2的混合物或四价金属氧化物的混合物构成的栅极绝缘膜和SiON，并且当其在半导体衬底上处于pMOS结构中时在半导体衬底上为nMOS结构或含有P和As中的至少一种时含有B，并且由具有功函数的金属制成的栅电极 4 eV至5.5 eV。

37. 发明申请

US20080191271A1 SEMICONDUCTOR DEVICE HAVING FINS FET AND MANUFACTURING METHOD THEREOF 有权
标题翻译：具有FINS FET的半导体器件及其制造方法
公开(公告)号：US20080191271A1
公开(公告)日：2008-08-14
申请号：US11972097
申请日：2008-01-10
申请人： Atsushi YAGISHITA , Akio KANEKO
发明人： Atsushi YAGISHITA , Akio KANEKO
IPC分类号： H01L29/00 , H01L21/3205
CPC分类号： H01L29/785 , H01L29/0673 , H01L29/42392 , H01L29/66795 , H01L29/7854 , H01L29/78639
摘要： A line-form insulator is formed on a substrate and then the substrate is etched with the insulator used as a mask to form first trenches on both sides of the insulator. Side wall insulators are formed on the side walls of the first trenches, the substrate is etched with the insulator and side wall insulators used as a mask to form second trenches in the bottom of the first trenches. After, the substrate is oxidized with the insulator and side wall insulators used as an anti-oxidation mask to cause oxide regions formed on the adjacent side walls of the second trenches lying on both sides of the substrate to make contact with each other and the insulator and side wall insulators are removed. Then, a fin FET having a semiconductor region as a line-form fin is formed in the substrate.
摘要翻译：在衬底上形成线形绝缘体，然后用用作掩模的绝缘体蚀刻衬底，以在绝缘体的两侧形成第一沟槽。侧壁绝缘体形成在第一沟槽的侧壁上，用绝缘体和侧壁绝缘体作为掩模蚀刻衬底，以在第一沟槽的底部形成第二沟槽。之后，用作为抗氧化掩模的绝缘体和侧壁绝缘体氧化衬底，使得形成在位于衬底两侧的第二沟槽的相邻侧壁上形成的氧化物区域相互接触，并且绝缘体和侧壁绝缘子被去除。然后，在衬底中形成具有半导体区域作为线状翅片的翅片FET。

38. 发明申请

US20080138969A1 Method of Manufacturing Semiconductor Device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20080138969A1
公开(公告)日：2008-06-12
申请号：US11948344
申请日：2007-11-30
申请人： Akio Kaneko , Motoyuki Sato , Katsuyuki Sekine , Tomohiro Saito , Kazuaki Nakajima , Tomonori Aoyama
发明人： Akio Kaneko , Motoyuki Sato , Katsuyuki Sekine , Tomohiro Saito , Kazuaki Nakajima , Tomonori Aoyama
IPC分类号： H01L21/28
CPC分类号： H01L29/517 , H01L21/28097 , H01L21/3215 , H01L21/823814 , H01L21/823835 , H01L21/823842 , H01L29/66507
摘要： A method of manufacturing a semiconductor device having a MOSFET of a first conductivity type and a MOSFET of a second conductivity type different from the first conductivity type formed on a semiconductor substrate, the method has: forming a gate insulating film; forming a first gate electrode layer, and forming a second gate electrode layer; forming a first metal containing layer on said first gate electrode layer and said second gate electrode layer; forming a second metal containing layer for preventing diffusion of a metal on said first metal containing layer; forming a third metal containing layer on said second gate electrode layer from which said first metal containing layer and said second metal containing layer are selectively removed, the third metal containing layer having a thickness different from the thickness of said first metal containing layer in a case where the third metal containing layer contains the same metal or alloy as the metal or alloy contained in said first metal containing layer; and performing a thermal processing, thereby causing reaction between the metal contained in said first metal containing layer and said first gate electrode layer to convert said first gate electrode layer into an alloy and causing reaction between the metal contained in said third metal containing layer and said second gate electrode layer to convert said second gate electrode layer into an alloy, thereby forming gate electrodes of different compositions.
摘要翻译：一种制造具有第一导电类型的MOSFET的半导体器件的方法和形成在半导体衬底上的与第一导电类型不同的第二导电类型的MOSFET，该方法具有：形成栅极绝缘膜; 形成第一栅电极层，形成第二栅电极层; 在所述第一栅电极层和所述第二栅电极层上形成第一含金属层; 形成用于防止金属在所述第一金属含有层上的扩散的第二含金属层; 在所述第二栅电极层上形成第三金属含有层，从所述第二金属含有层和所述第二金属含有层选择性地除去所述第三金属含有层，所述第三金属含有层的厚度与所述第一金属含有层的厚度不同其中所述第三含金属层包含与所述第一含金属层中所含的金属或合金相同的金属或合金; 并进行热处理，从而使包含在所述第一金属含有层中的金属与所述第一栅极电极层之间产生反应，将所述第一栅电极层转换成合金，并引起所述第三金属含有层中含有的金属与所述第二栅极电极层，以将所述第二栅电极层转换成合金，从而形成不同组成的栅极。

39. 发明授权

US07371644B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07371644B2
公开(公告)日：2008-05-13
申请号：US11404772
申请日：2006-04-17
申请人： Atsushi Yagishita , Akio Kaneko , Kazunari Ishimaru
发明人： Atsushi Yagishita , Akio Kaneko , Kazunari Ishimaru
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L21/28097 , H01L21/823431 , H01L27/0886 , H01L29/66795 , H01L29/6681 , H01L29/7851
摘要： According to the present invention, there is provided a semiconductor device fabrication method, comprising: depositing a mask material on a semiconductor substrate; patterning the mask material and forming a trench in a surface portion of the semiconductor substrate by etching, thereby forming a first projection in a first region, and a second projection wider than the first projection in a second region; burying a device isolation insulating film in the trench; etching away a predetermined amount of the device isolation insulating film formed in the first region; etching away the mask material formed in the second region; forming a first gate insulating film on a pair of opposing side surfaces of the first projection, and a second gate insulating film on an upper surface of the second projection; depositing a first gate electrode material on the device isolation insulating film, mask material, and second gate insulating film; planarizing the first gate electrode material by using as stoppers the mask material formed in the first region and the device isolation insulating film formed in the second region; depositing a second gate electrode material on the mask material, first gate electrode material, and device isolation insulating film; and patterning the first and second gate electrode materials, thereby forming a first gate electrode in the first region, and a second gate electrode in the second region.
摘要翻译：根据本发明，提供了一种半导体器件制造方法，包括：在半导体衬底上沉积掩模材料; 图案化掩模材料并通过蚀刻在半导体衬底的表面部分中形成沟槽，从而在第一区域中形成第一突起，在第二区域形成比第一突起宽的第二突起; 在沟槽中埋设器件隔离绝缘膜; 蚀刻形成在第一区域中的预定量的器件隔离绝缘膜; 蚀刻形成在第二区域中的掩模材料; 在所述第一突起的一对相对的侧面上形成第一栅极绝缘膜，在所述第二突起的上表面上形成第二栅极绝缘膜; 在器件隔离绝缘膜，掩模材料和第二栅极绝缘膜上沉积第一栅电极材料; 通过使用形成在第一区域中的掩模材料和形成在第二区域中的器件隔离绝缘膜作为阻挡层来平坦化第一栅电极材料; 在掩模材料上沉积第二栅电极材料，第一栅电极材料和器件隔离绝缘膜; 以及对第一和第二栅电极材料进行构图，从而在第一区域形成第一栅电极，在第二区域形成第二栅电极。

40. 发明申请

US20050110101A1 Semiconductor apparatus and method of manufacturing the semiconductor apparatus 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050110101A1
公开(公告)日：2005-05-26
申请号：US10927115
申请日：2004-08-27
申请人： Akio Kaneko , Kazuhiro Eguchi , Seiji Inumiya , Katsuyuki Sekine , Motoyuki Sato
发明人： Akio Kaneko , Kazuhiro Eguchi , Seiji Inumiya , Katsuyuki Sekine , Motoyuki Sato
IPC分类号： C23C14/10 , C23C16/42 , H01L21/28 , H01L21/316 , H01L21/336 , H01L21/822 , H01L21/8234 , H01L21/8238 , H01L27/04 , H01L27/08 , H01L27/088 , H01L27/092 , H01L27/115 , H01L27/12 , H01L29/423 , H01L29/49 , H01L29/51 , H01L29/78 , H01L29/786 , H01L29/76
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28211 , H01L27/115 , H01L27/1203 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/66825 , H01L29/78
摘要： A semiconductor apparatus wherein a device formed on a semiconductor substrate comprises a gate insulating film including a high dielectric constant film formed on the substrate and an anti-reaction film formed on the high dielectric constant film, and a gate electrode formed on the anti-reaction film, the high dielectric constant film comprises a film containing at least one of Hf and Zr, and Si and O, or a film containing at least one of Hf and Zr, and Si, O and N, the anti-reaction film comprises an SiO2 film, a film containing SiO2 as a main component and at least one of Hf and Zr, a film containing SiO2 as a main component and N, a film containing SiO2 as a main component, Hf and N, a film containing SiO2 as a main component, Zr and N, or a film containing SiO2 as a main component, Hf, Zr and N.
摘要翻译：一种半导体装置，其中形成在半导体衬底上的器件包括栅极绝缘膜，该栅极绝缘膜包括形成在基底上的高介电常数膜和形成在高介电常数膜上的抗反应膜，以及形成在抗反应上的栅电极高介电常数膜包括含有Hf和Zr中的至少一种以及Si和O的膜，或包含Hf和Zr中的至少一种以及Si，O和N的膜，所述抗反应膜包括 SiO 2膜，含有SiO 2作为主要成分的膜和Hf和Zr中的至少一种的膜，含有SiO 2的膜作为主要成分为N，以SiO 2为主要成分的膜，Hf和N，以SiO 2为主要成分的膜，Zr和N，或膜含有SiO 2作为主要成分的Hf，Zr和N.

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