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1. 发明申请

US20080138969A1 Method of Manufacturing Semiconductor Device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20080138969A1
公开(公告)日：2008-06-12
申请号：US11948344
申请日：2007-11-30
申请人： Akio Kaneko , Motoyuki Sato , Katsuyuki Sekine , Tomohiro Saito , Kazuaki Nakajima , Tomonori Aoyama
发明人： Akio Kaneko , Motoyuki Sato , Katsuyuki Sekine , Tomohiro Saito , Kazuaki Nakajima , Tomonori Aoyama
IPC分类号： H01L21/28
CPC分类号： H01L29/517 , H01L21/28097 , H01L21/3215 , H01L21/823814 , H01L21/823835 , H01L21/823842 , H01L29/66507
摘要： A method of manufacturing a semiconductor device having a MOSFET of a first conductivity type and a MOSFET of a second conductivity type different from the first conductivity type formed on a semiconductor substrate, the method has: forming a gate insulating film; forming a first gate electrode layer, and forming a second gate electrode layer; forming a first metal containing layer on said first gate electrode layer and said second gate electrode layer; forming a second metal containing layer for preventing diffusion of a metal on said first metal containing layer; forming a third metal containing layer on said second gate electrode layer from which said first metal containing layer and said second metal containing layer are selectively removed, the third metal containing layer having a thickness different from the thickness of said first metal containing layer in a case where the third metal containing layer contains the same metal or alloy as the metal or alloy contained in said first metal containing layer; and performing a thermal processing, thereby causing reaction between the metal contained in said first metal containing layer and said first gate electrode layer to convert said first gate electrode layer into an alloy and causing reaction between the metal contained in said third metal containing layer and said second gate electrode layer to convert said second gate electrode layer into an alloy, thereby forming gate electrodes of different compositions.
摘要翻译：一种制造具有第一导电类型的MOSFET的半导体器件的方法和形成在半导体衬底上的与第一导电类型不同的第二导电类型的MOSFET，该方法具有：形成栅极绝缘膜; 形成第一栅电极层，形成第二栅电极层; 在所述第一栅电极层和所述第二栅电极层上形成第一含金属层; 形成用于防止金属在所述第一金属含有层上的扩散的第二含金属层; 在所述第二栅电极层上形成第三金属含有层，从所述第二金属含有层和所述第二金属含有层选择性地除去所述第三金属含有层，所述第三金属含有层的厚度与所述第一金属含有层的厚度不同其中所述第三含金属层包含与所述第一含金属层中所含的金属或合金相同的金属或合金; 并进行热处理，从而使包含在所述第一金属含有层中的金属与所述第一栅极电极层之间产生反应，将所述第一栅电极层转换成合金，并引起所述第三金属含有层中含有的金属与所述第二栅极电极层，以将所述第二栅电极层转换成合金，从而形成不同组成的栅极。

2. 发明授权

US07521309B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07521309B2
公开(公告)日：2009-04-21
申请号：US11948344
申请日：2007-11-30
申请人： Akio Kaneko , Motoyuki Sato , Katsuyuki Sekine , Tomohiro Saito , Kazuaki Nakajima , Tomonori Aoyama
发明人： Akio Kaneko , Motoyuki Sato , Katsuyuki Sekine , Tomohiro Saito , Kazuaki Nakajima , Tomonori Aoyama
IPC分类号： H01L21/336
CPC分类号： H01L29/517 , H01L21/28097 , H01L21/3215 , H01L21/823814 , H01L21/823835 , H01L21/823842 , H01L29/66507
摘要： A method of manufacturing a semiconductor device having a MOSFET of a first conductivity type and a MOSFET of a second conductivity type different from the first conductivity type formed on a semiconductor substrate, the method has: forming a gate insulating film; forming a first gate electrode layer, and forming a second gate electrode layer; forming a first metal containing layer on said first gate electrode layer and said second gate electrode layer; forming a second metal containing layer for preventing diffusion of a metal on said first metal containing layer; forming a third metal containing layer on said second gate electrode layer from which said first metal containing layer and said second metal containing layer are selectively removed, the third metal containing layer having a thickness different from the thickness of said first metal containing layer in a case where the third metal containing layer contains the same metal or alloy as the metal or alloy contained in said first metal containing layer; and performing a thermal processing, thereby causing reaction between the metal contained in said first metal containing layer and said first gate electrode layer to convert said first gate electrode layer into an alloy and causing reaction between the metal contained in said third metal containing layer and said second gate electrode layer to convert said second gate electrode layer into an alloy, thereby forming gate electrodes of different compositions.
摘要翻译：一种制造具有第一导电类型的MOSFET的半导体器件的方法和形成在半导体衬底上的与第一导电类型不同的第二导电类型的MOSFET，该方法具有：形成栅极绝缘膜; 形成第一栅电极层，形成第二栅电极层; 在所述第一栅电极层和所述第二栅电极层上形成第一含金属层; 形成用于防止金属在所述第一金属含有层上的扩散的第二含金属层; 在所述第二栅电极层上形成第三金属含有层，从所述第二金属含有层和所述第二金属含有层被选择性地除去，所述第三金属含有层的厚度与所述第一金属含有层的厚度不同其中所述第三含金属层包含与所述第一含金属层中所含的金属或合金相同的金属或合金; 并进行热处理，从而使包含在所述第一金属含有层中的金属与所述第一栅极电极层之间产生反应，将所述第一栅电极层转换成合金，并引起所述第三金属含有层中含有的金属与所述第二栅极电极层，以将所述第二栅电极层转换成合金，从而形成不同组成的栅电极。

3. 发明申请

US20070278587A1 Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070278587A1
公开(公告)日：2007-12-06
申请号：US11798068
申请日：2007-05-10
申请人： Tomonori Aoyama , Tomohiro Saito , Katsuyuki Sekine , Kazuaki Nakajima , Motoyuki Sato , Takuya Kobayashi
发明人： Tomonori Aoyama , Tomohiro Saito , Katsuyuki Sekine , Kazuaki Nakajima , Motoyuki Sato , Takuya Kobayashi
IPC分类号： H01L29/94
CPC分类号： H01L21/26513 , H01L21/26506 , H01L21/28079 , H01L21/28097 , H01L21/28202 , H01L21/2822 , H01L21/823842 , H01L21/823857 , H01L29/513 , H01L29/518 , H01L29/6656 , H01L29/6659 , H01L29/785
摘要： This disclosure concerns a semiconductor device comprising a semiconductor substrate; a gate dielectric film provided on the semiconductor substrate and containing Hf, Si, and O or containing Zr, Si and O; a gate electrode of an n-channel FET provided on the gate dielectric film, the gate electrode being made of nickel silicide containing nickel at a higher content than silicon; an aluminum layer provided at a bottom portion of the gate electrode of the n-channel FET; and a gate electrode of a p-channel FET provided on the gate dielectric film, the gate electrode being made of nickel silicide containing nickel at a higher content than silicon.
摘要翻译：本公开涉及包括半导体衬底的半导体器件; 设置在半导体衬底上并含有Hf，Si和O或含有Zr，Si和O的栅极电介质膜; 设置在所述栅极电介质膜上的n沟道FET的栅电极，所述栅电极由含有比所述硅含量高的镍的镍硅化物制成; 设置在n沟道FET的栅电极的底部的铝层; 以及设置在所述栅极电介质膜上的p沟道FET的栅电极，所述栅电极由镍含量高于硅的镍的硅化镍制成。

4. 发明申请

US20060273413A1 Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060273413A1
公开(公告)日：2006-12-07
申请号：US11185678
申请日：2005-07-21
申请人： Motoyuki Sato , Katsuyuki Sekine , Kazuaki Nakajima , Tomohiro Saito , Kazuhiro Eguchi , Atsushi Yagishita
发明人： Motoyuki Sato , Katsuyuki Sekine , Kazuaki Nakajima , Tomohiro Saito , Kazuhiro Eguchi , Atsushi Yagishita
IPC分类号： H01L29/94
CPC分类号： H01L21/823462 , H01L21/82345 , H01L29/518 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： There are provided: a semiconductor substrate including first and second device regions isolated by device isolation regions; a first gate insulating film of a high-k material formed in the first device region; a first gate electrode formed on the first gate insulating film; first source and drain regions formed at both sides of the first gate electrode in the first device region; a second gate insulating film of a high-k material which is different from the high-k material of the first gate insulating film, the second gate insulating film being formed in the second device region; a second gate electrode formed on the second gate insulating film; and second source and drain regions formed at both sides of the second gate electrode in the second device region.
摘要翻译：提供：包括由器件隔离区域隔离的第一和第二器件区域的半导体衬底; 形成在所述第一器件区域中的高k材料的第一栅极绝缘膜; 形成在第一栅极绝缘膜上的第一栅电极; 形成在第一器件区域中的第一栅电极的两侧的第一源极和漏极区; 与所述第一栅极绝缘膜的高k材料不同的高k材料的第二栅极绝缘膜，所述第二栅极绝缘膜形成在所述第二器件区域中; 形成在所述第二栅极绝缘膜上的第二栅电极; 以及形成在第二器件区域中的第二栅电极的两侧的第二源极和漏极区。

5. 发明申请

US20070099370A1 Method for manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20070099370A1
公开(公告)日：2007-05-03
申请号：US11524237
申请日：2006-09-21
申请人： Kazuaki Nakajima , Tomohiro Saito
发明人： Kazuaki Nakajima , Tomohiro Saito
IPC分类号： H01L21/8238
CPC分类号： H01L21/823828 , H01L21/28052 , H01L21/28097 , H01L29/6659 , H01L29/7833
摘要： A method for manufacturing a semiconductor device includes forming a gate insulating film on a semiconductor substrate, and forming a gate electrode comprising a metal semiconductor compound layer and having a predetermined gate length on the gate insulating film, the forming the gate electrode including forming a polycrystalline semiconductor film having an average grain diameter below a specific size depending on the predetermined gate length and including at least one of silicon and germanium, the average grain diameter of the semiconductor film being 5 nm or more and 90 nm or less, forming a metal film on the semiconductor film, and converting whole of the semiconductor film into the metal semiconductor compound layer by reacting the semiconductor film and the metal film by heat treatment.
摘要翻译：一种半导体器件的制造方法包括：在半导体衬底上形成栅极绝缘膜，在所述栅极绝缘膜上形成包含金属半导体化合物层并具有规定的栅极长度的栅电极，形成所述栅电极，形成多晶半导体膜的平均粒径小于规定的栅极长度的特定尺寸，并且包括硅和锗中的至少一种，半导体膜的平均粒径为5nm以上且90nm以下，形成金属膜并且通过热处理使半导体膜和金属膜反应而将整个半导体膜转换成金属半导体化合物层。

6. 发明申请

US20080197429A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080197429A1
公开(公告)日：2008-08-21
申请号：US12033566
申请日：2008-02-19
申请人： Motoyuki Sato , Tomohiro Saito
发明人： Motoyuki Sato , Tomohiro Saito
IPC分类号： H01L29/78 , H01L21/4763
CPC分类号： H01L29/518 , H01L21/28052 , H01L21/28097 , H01L21/28202 , H01L21/823857 , H01L29/7833
摘要： A semiconductor device includes: a silicon oxide film; a metal silicate insulating film provided on the silicon oxide film and having a higher dielectric constant than the silicon oxide film; and a gate electrode provided on the metal silicate insulating film. A composition ratio of a metal element in the metal silicate insulating film on a side closer to the gate electrode is lower than a composition ratio of the metal element in the metal silicate insulating film on a side closer to the silicon oxide film.
摘要翻译：半导体器件包括：氧化硅膜; 设置在所述氧化硅膜上并且具有比所述氧化硅膜更高的介电常数的金属硅酸盐绝缘膜; 以及设置在金属硅酸盐绝缘膜上的栅电极。金属硅酸盐绝缘膜中靠近栅电极的金属元素的组成比低于金属硅酸盐绝缘膜中更靠近氧化硅膜的金属元素的组成比。

7. 发明授权

US07915130B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07915130B2
公开(公告)日：2011-03-29
申请号：US12588336
申请日：2009-10-13
申请人： Tomohiro Saito , Akio Kaneko , Atsushi Yagishita
发明人： Tomohiro Saito , Akio Kaneko , Atsushi Yagishita
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L29/4908 , H01L29/785
摘要： This disclosure concerns a manufacturing method of a semiconductor device includes forming a Fin-type body on an insulation layer, the Fin-type body being made of a semiconductor material and having an upper surface covered with a protective film; forming a gate insulation film on side surfaces of the Fin-type body; depositing a gate electrode material so as to cover the Fin-type body; planarizing the gate electrode material; forming a gate electrode by processing the gate electrode material; depositing an interlayer insulation film so as to cover the gate electrode; exposing the upper surface of the gate electrode; depositing a metal layer on the upper surface of the gate electrode; siliciding the gate electrode by reacting the gate electrode with the metal layer; forming a trench on the upper surface of the protective film by removing an unreacted metal in the metal layer; and filling the trench with a conductor.
摘要翻译：本公开涉及半导体器件的制造方法，包括在绝缘层上形成鳍状体，所述鳍状体由半导体材料制成，并且具有被保护膜覆盖的上表面; 在鳍型体的侧表面上形成栅极绝缘膜; 沉积栅电极材料以覆盖鳍型体; 平面化栅电极材料; 通过处理栅电极材料形成栅电极; 沉积层间绝缘膜以覆盖栅电极; 露出栅电极的上表面; 在栅电极的上表面上沉积金属层; 通过使栅电极与金属层反应来硅化栅电极; 通过去除金属层中的未反应金属在保护膜的上表面上形成沟槽; 并用导体填充沟槽。

8. 发明申请

US20070148843A1 Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070148843A1
公开(公告)日：2007-06-28
申请号：US11635039
申请日：2006-12-07
申请人： Tomohiro Saito , Akio Kaneko , Atsushi Yagishita
发明人： Tomohiro Saito , Akio Kaneko , Atsushi Yagishita
IPC分类号： H01L21/8242 , H01L21/8234 , H01L21/336
CPC分类号： H01L29/66795 , H01L29/4908 , H01L29/785
摘要： This disclosure concerns a manufacturing method of a semiconductor device includes forming a Fin-type body on an insulation layer, the Fin-type body being made of a semiconductor material and having an upper surface covered with a protective film; forming a gate insulation film on side surfaces of the Fin-type body; depositing a gate electrode material so as to cover the Fin-type body; planarizing the gate electrode material; forming a gate electrode by processing the gate electrode material; depositing an interlayer insulation film so as to cover the gate electrode; exposing the upper surface of the gate electrode; depositing a metal layer on the upper surface of the gate electrode; siliciding the gate electrode by reacting the gate electrode with the metal layer; forming a trench on the upper surface of the protective film by removing an unreacted metal in the metal layer; and filling the trench with a conductor.
摘要翻译：本公开涉及半导体器件的制造方法，包括在绝缘层上形成鳍状体，所述鳍状体由半导体材料制成，并且具有被保护膜覆盖的上表面; 在鳍型体的侧表面上形成栅极绝缘膜; 沉积栅电极材料以覆盖鳍型体; 平面化栅电极材料; 通过处理栅电极材料形成栅电极; 沉积层间绝缘膜以覆盖栅电极; 露出栅电极的上表面; 在栅电极的上表面上沉积金属层; 通过使栅电极与金属层反应来硅化栅电极; 通过去除金属层中的未反应金属在保护膜的上表面上形成沟槽; 并用导体填充沟槽。

9. 发明申请

US20100035396A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20100035396A1
公开(公告)日：2010-02-11
申请号：US12588336
申请日：2009-10-13
申请人： Tomohiro Saito , Akio Kaneko , Atsushi Yagishita
发明人： Tomohiro Saito , Akio Kaneko , Atsushi Yagishita
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L29/4908 , H01L29/785
摘要： This disclosure concerns a manufacturing method of a semiconductor device includes forming a Fin-type body on an insulation layer, the Fin-type body being made of a semiconductor material and having an upper surface covered with a protective film; forming a gate insulation film on side surfaces of the Fin-type body; depositing a gate electrode material so as to cover the Fin-type body; planarizing the gate electrode material; forming a gate electrode by processing the gate electrode material; depositing an interlayer insulation film so as to cover the gate electrode; exposing the upper surface of the gate electrode; depositing a metal layer on the upper surface of the gate electrode; siliciding the gate electrode by reacting the gate electrode with the metal layer; forming a trench on the upper surface of the protective film by removing an unreacted metal in the metal layer; and filling the trench with a conductor.
摘要翻译：本公开涉及半导体器件的制造方法，包括在绝缘层上形成鳍状体，所述鳍状体由半导体材料制成，并且具有被保护膜覆盖的上表面; 在鳍型体的侧表面上形成栅极绝缘膜; 沉积栅电极材料以覆盖鳍型体; 平面化栅电极材料; 通过处理栅电极材料形成栅电极; 沉积层间绝缘膜以覆盖栅电极; 露出栅电极的上表面; 在栅电极的上表面上沉积金属层; 通过使栅电极与金属层反应来硅化栅电极; 通过去除金属层中的未反应金属在保护膜的上表面上形成沟槽; 并用导体填充沟槽。

10. 发明授权

US09287050B2 MEMS and method of manufacturing the same 有权
标题翻译： MEMS及其制造方法
公开(公告)号：US09287050B2
公开(公告)日：2016-03-15
申请号：US13413889
申请日：2012-03-07
申请人： Tomohiro Saito
发明人： Tomohiro Saito
IPC分类号： H01L29/84 , H01G5/18 , B81C1/00
CPC分类号： H01G5/18 , B81B2201/018 , B81B2201/0221 , B81B2203/0109 , B81C1/00611 , B81C2201/0126
摘要： According to one embodiment, a MEMS includes a first electrode, a first auxiliary structure and a second electrode. The first electrode is provided on a substrate. The first auxiliary structure is provided on the substrate and adjacent to the first electrode. The first auxiliary structure is in an electrically floating state. The second electrode is provided above the first electrode and the first auxiliary structure, and is driven in a direction of the first electrode.
摘要翻译：根据一个实施例，MEMS包括第一电极，第一辅助结构和第二电极。第一电极设置在基板上。第一辅助结构设置在基板上并与第一电极相邻。第一辅助结构处于电浮动状态。第二电极设置在第一电极和第一辅助结构之上，并且沿第一电极的方向被驱动。

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