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1. 发明授权

US08338889B2 Semiconductor device and method of manufacturing semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08338889B2
公开(公告)日：2012-12-25
申请号：US13137920
申请日：2011-09-21
申请人： Akio Kaneko , Atsushi Yagishita , Satoshi Inaba
发明人： Akio Kaneko , Atsushi Yagishita , Satoshi Inaba
IPC分类号： H01L27/12
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/045 , H01L29/6681 , H01L29/7843
摘要： The disclosure concerns a method of manufacturing a semiconductor device including forming a plurality of fins made of a semiconductor material on an insulating layer; forming a gate insulating film on side surfaces of the plurality of fins; and forming a gate electrode on the gate insulating film in such a manner that a compressive stress is applied to a side surface of a first fin which is used in an NMOSFET among the plurality of fins in a direction perpendicular to the side surface and a tensile stress is applied to a side surface of a second fin which is used in a PMOSFET among the plurality of fins in a direction perpendicular to the side surface.
摘要翻译：本公开涉及一种制造半导体器件的方法，包括在绝缘层上形成由半导体材料制成的多个鳍片; 在所述多个翅片的侧面上形成栅极绝缘膜; 以及在所述栅极绝缘膜上形成栅电极，使得在与所述侧面垂直的方向上在所述多个翅片中的NMOSFET中使用的第一鳍片的侧面施加压缩应力，在垂直于侧面的方向上，在多个翅片中的PMOSFET中使用的第二鳍片的侧面施加应力。

2. 发明申请

US20120012935A1 Semiconductor device and method of manufacturing semiconductor device 有权
公开(公告)号：US20120012935A1
公开(公告)日：2012-01-19
申请号：US13137920
申请日：2011-09-21
申请人： Akio Kaneko , Atsushi Yagishita , Satoshi Inaba
发明人： Akio Kaneko , Atsushi Yagishita , Satoshi Inaba
IPC分类号： H01L27/12 , H01L27/092
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/045 , H01L29/6681 , H01L29/7843
摘要： The disclosure concerns a method of manufacturing a semiconductor device including forming a plurality of fins made of a semiconductor material on an insulating layer; forming a gate insulating film on side surfaces of the plurality of fins; and forming a gate electrode on the gate insulating film in such a manner that a compressive stress is applied to a side surface of a first fin which is used in an NMOSFET among the plurality of fins in a direction perpendicular to the side surface and a tensile stress is applied to a side surface of a second fin which is used in a PMOSFET among the plurality of fins in a direction perpendicular to the side surface.

3. 发明授权

US07968397B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07968397B2
公开(公告)日：2011-06-28
申请号：US12659250
申请日：2010-03-02
申请人： Akio Kaneko , Seiji Inumiya , Katsuyuki Sekine , Kazuhiro Eguchi , Motoyuki Sato
发明人： Akio Kaneko , Seiji Inumiya , Katsuyuki Sekine , Kazuhiro Eguchi , Motoyuki Sato
IPC分类号： H01L21/38
CPC分类号： H01L21/28194 , H01L21/28079 , H01L21/823842 , H01L21/823857 , H01L29/495 , H01L29/513 , H01L29/517 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device according to the present invention comprises a semiconductor substrate, a gate insulating film which is composed of a material whose main component is a tetravalent metal oxide, a mixture of a tetravalent metal oxide and SiO2, or a mixture of a tetravalent metal oxide and SiON and which containing B when it is in an nMOS structure on the semiconductor substrate or containing at least one of P and As when it is in a pMOS structure on the semiconductor substrate, and a gate electrode made of a metal having a work function of 4 eV to 5.5 eV.
摘要翻译：根据本发明的半导体器件包括半导体衬底，由主要成分为四价金属氧化物的材料，四价金属氧化物和SiO 2的混合物或四价金属氧化物的混合物构成的栅极绝缘膜和SiON，并且当其在半导体衬底上处于pMOS结构中时在半导体衬底上为nMOS结构或含有P和As中的至少一种时含有B，并且由具有功函数的金属制成的栅电极 4 eV至5.5 eV。

4. 发明申请

US20100304555A1 Semiconductor device and method of manufacturing semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20100304555A1
公开(公告)日：2010-12-02
申请号：US12805533
申请日：2010-08-04
申请人： Akio Kaneko , Atsushi Yagishita , Satoshi Inaba
发明人： Akio Kaneko , Atsushi Yagishita , Satoshi Inaba
IPC分类号： H01L21/84
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/045 , H01L29/6681 , H01L29/7843
摘要： The disclosure concerns a method of manufacturing a semiconductor device including forming a plurality of fins made of a semiconductor material on an insulating layer; forming a gate insulating film on side surfaces of the plurality of fins; and forming a gate electrode on the gate insulating film in such a manner that a compressive stress is applied to a side surface of a first fin which is used in an NMOSFET among the plurality of fins in a direction perpendicular to the side surface and a tensile stress is applied to a side surface of a second fin which is used in a PMOSFET among the plurality of fins in a direction perpendicular to the side surface.
摘要翻译：本公开涉及一种制造半导体器件的方法，包括在绝缘层上形成由半导体材料制成的多个鳍片; 在所述多个翅片的侧面上形成栅极绝缘膜; 以及在所述栅极绝缘膜上形成栅电极，使得在与所述侧面垂直的方向上在所述多个翅片中的NMOSFET中使用的第一鳍片的侧面施加压缩应力，在垂直于侧面的方向上，在多个翅片中的PMOSFET中使用的第二鳍片的侧面施加应力。

5. 发明申请

US20090194821A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090194821A1
公开(公告)日：2009-08-06
申请号：US12359974
申请日：2009-01-26
申请人： Akio KANEKO , Seiji Inumiya , Tomonori Aoyama , Takuya Kobayashi
发明人： Akio KANEKO , Seiji Inumiya , Tomonori Aoyama , Takuya Kobayashi
IPC分类号： H01L29/68 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/0245 , H01L21/02532 , H01L21/02667 , H01L21/823431 , H01L21/82385 , H01L21/823857 , H01L27/0886 , H01L27/0922 , H01L29/1037 , H01L29/1054 , H01L29/665 , H01L29/6659 , H01L29/66651 , H01L29/66795 , H01L29/7834 , H01L29/7851 , H01L29/7853
摘要： A method of fabricating a semiconductor device according to one embodiment includes: forming a SiGe crystal layer on a semiconductor substrate, the SiGe crystal layer having a first plane and a second plane inclined with respect to the first plane; forming an amorphous Si film on the SiGe crystal layer; crystallizing a portion located adjacent to the first and second planes of the amorphous Si film by applying heat treatment using the first and second planes of the SiGe crystal layer as a seed, thereby forming a Si crystal layer; selectively removing or thinning a portion of the amorphous Si film that is not crystallized by the heat treatment; applying oxidation treatment to a surface of the Si crystal layer, thereby forming a gate insulating film on the surface of the Si crystal layer; and forming a gate electrode on the gate insulating film.
摘要翻译：根据一个实施例的制造半导体器件的方法包括：在半导体衬底上形成SiGe晶体层，所述SiGe晶体层具有第一平面和相对于第一平面倾斜的第二平面; 在SiGe晶体层上形成非晶Si膜; 通过使用SiGe晶体层的第一和第二平面作为种子进行热处理，使位于非晶Si膜的第一和第二平面附近的部分结晶，从而形成Si晶体层; 通过热处理选择性去除或稀薄未结晶的非晶Si膜的一部分; 对Si晶体层的表面进行氧化处理，从而在Si晶体层的表面上形成栅极绝缘膜; 以及在所述栅极绝缘膜上形成栅电极。

6. 发明授权

US07375403B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07375403B2
公开(公告)日：2008-05-20
申请号：US10738049
申请日：2003-12-18
申请人： Akio Kaneko , Seiji Inumiya , Katsuyuki Sekine , Kazuhiro Eguchi , Motoyuki Sato
发明人： Akio Kaneko , Seiji Inumiya , Katsuyuki Sekine , Kazuhiro Eguchi , Motoyuki Sato
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/28194 , H01L21/28079 , H01L21/823842 , H01L21/823857 , H01L29/495 , H01L29/513 , H01L29/517 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device according to the present invention comprises a semiconductor substrate, a gate insulating film which is composed of a material whose main component is a tetravalent metal oxide, a mixture of a tetravalent metal oxide and SiO2, or a mixture of a tetravalent metal oxide and SiON and which containing B when it is in an nMOS structure on the semiconductor substrate or containing at least one of P and As when it is in a pMOS structure on the semiconductor substrate, and a gate electrode made of a metal having a work function of 4 eV to 5.5 eV.
摘要翻译：根据本发明的半导体器件包括半导体衬底，由主要成分为四价金属氧化物的材料，四价金属氧化物和SiO 2的混合物构成的栅极绝缘膜，或四价金属氧化物和SiON的混合物，并且当其在半导体衬底上处于pMOS结构中时在半导体衬底上为nMOS结构或含有P和As中的至少一种时含有B，并且栅电极由功能为4eV至5.5eV的金属制成。

7. 发明申请

US20080054378A1 Semiconductor apparatus and method of manufacturing the semiconductor apparatus 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080054378A1
公开(公告)日：2008-03-06
申请号：US11889278
申请日：2007-08-10
申请人： Akio Kaneko , Kazuhiro Eguchi , Seiji Inumiya , Katsuyuki Sekine , Motoyuki Sato
发明人： Akio Kaneko , Kazuhiro Eguchi , Seiji Inumiya , Katsuyuki Sekine , Motoyuki Sato
IPC分类号： H01L29/76
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28211 , H01L27/115 , H01L27/1203 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/66825 , H01L29/78
摘要： A semiconductor apparatus wherein a device formed on a semiconductor substrate comprises a gate insulating film including a high dielectric constant film formed on the substrate and an anti-reaction film formed on the high dielectric constant film, and a gate electrode formed on the anti-reaction film, the high dielectric constant film comprises a film containing at least one of Hf and Zr, and Si and O, or a film containing at least one of Hf and Zr, and Si, O and N, the anti-reaction film comprises an SiO2 film, a film containing SiO2 as a main component and at least one of Hf and Zr, a film containing SiO2 as a main component and N, a film containing SiO2 as a main component, Hf and N, a film containing SiO2 as a main component, Zr and N, or a film containing SiO2 as a main component, Hf, Zr and N.
摘要翻译：一种半导体装置，其中形成在半导体衬底上的器件包括栅极绝缘膜，该栅极绝缘膜包括形成在基底上的高介电常数膜和形成在高介电常数膜上的抗反应膜，以及形成在抗反应上的栅电极高介电常数膜包括含有Hf和Zr中的至少一种以及Si和O的膜，或包含Hf和Zr中的至少一种以及Si，O和N的膜，所述抗反应膜包括 SiO 2膜，含有SiO 2作为主要成分的膜和Hf和Zr中的至少一种的膜，含有SiO 2的膜作为主要成分为N，以SiO 2为主要成分的膜，Hf和N，以SiO 2为主要成分的膜，Zr和N，或膜含有SiO 2作为主要成分的Hf，Zr和N.

8. 发明申请

US20070190708A1 Semiconductor device and method manufacturing semiconductor device 有权
标题翻译：半导体器件和方法制造半导体器件
公开(公告)号：US20070190708A1
公开(公告)日：2007-08-16
申请号：US11700147
申请日：2007-01-31
申请人： Akio Kaneko , Atsushi Yagishita , Satoshi Inaba
发明人： Akio Kaneko , Atsushi Yagishita , Satoshi Inaba
IPC分类号： H01L21/84
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/045 , H01L29/6681 , H01L29/7843
摘要： The disclosure concerns a method of manufacturing a semiconductor device including forming a plurality of fins made of a semiconductor material on an insulating layer; forming a gate insulating film on side surfaces of the plurality of fins; and forming a gate electrode on the gate insulating film in such a manner that a compressive stress is applied to a side surface of a first fin which is used in an NMOSFET among the plurality of fins in a direction perpendicular to the side surface and a tensile stress is applied to a side surface of a second fin which is used in a PMOSFET among the plurality of fins in a direction perpendicular to the side surface.
摘要翻译：本公开涉及一种制造半导体器件的方法，包括在绝缘层上形成由半导体材料制成的多个鳍片; 在所述多个翅片的侧面上形成栅极绝缘膜; 以及在所述栅极绝缘膜上形成栅电极，使得在与所述侧面垂直的方向上在所述多个翅片中的NMOSFET中使用的第一鳍片的侧面施加压缩应力，在垂直于侧面的方向上，在多个翅片中的PMOSFET中使用的第二鳍片的侧面施加应力。

9. 发明申请

US20060275988A1 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060275988A1
公开(公告)日：2006-12-07
申请号：US11404772
申请日：2006-04-17
申请人： Atsushi Yagishita , Akio Kaneko , Kazunari Ishimaru
发明人： Atsushi Yagishita , Akio Kaneko , Kazunari Ishimaru
IPC分类号： H01L21/8234 , H01L29/76
CPC分类号： H01L29/785 , H01L21/28097 , H01L21/823431 , H01L27/0886 , H01L29/66795 , H01L29/6681 , H01L29/7851
摘要： According to the present invention, there is provided a semiconductor device fabrication method, comprising: depositing a mask material on a semiconductor substrate; patterning the mask material and forming a trench in a surface portion of the semiconductor substrate by etching, thereby forming a first projection in a first region, and a second projection wider than the first projection in a second region; burying a device isolation insulating film in the trench; etching away a predetermined amount of the device isolation insulating film formed in the first region; etching away the mask material formed in the second region; forming a first gate insulating film on a pair of opposing side surfaces of the first projection, and a second gate insulating film on an upper surface of the second projection; depositing a first gate electrode material on the device isolation insulating film, mask material, and second gate insulating film; planarizing the first gate electrode material by using as stoppers the mask material formed in the first region and the device isolation insulating film formed in the second region; depositing a second gate electrode material on the mask material, first gate electrode material, and device isolation insulating film; and patterning the first and second gate electrode materials, thereby forming a first gate electrode in the first region, and a second gate electrode in the second region.
摘要翻译：根据本发明，提供了一种半导体器件制造方法，包括：在半导体衬底上沉积掩模材料; 图案化掩模材料并通过蚀刻在半导体衬底的表面部分中形成沟槽，从而在第一区域中形成第一突起，在第二区域形成比第一突起宽的第二突起; 在沟槽中埋设器件隔离绝缘膜; 蚀刻形成在第一区域中的预定量的器件隔离绝缘膜; 蚀刻形成在第二区域中的掩模材料; 在所述第一突起的一对相对的侧面上形成第一栅极绝缘膜，在所述第二突起的上表面上形成第二栅极绝缘膜; 在器件隔离绝缘膜，掩模材料和第二栅极绝缘膜上沉积第一栅电极材料; 通过使用形成在第一区域中的掩模材料和形成在第二区域中的器件隔离绝缘膜作为阻挡层来平坦化第一栅电极材料; 在掩模材料上沉积第二栅电极材料，第一栅电极材料和器件隔离绝缘膜; 以及对第一和第二栅电极材料进行构图，从而在第一区域形成第一栅电极，在第二区域形成第二栅电极。

10. 发明授权

US07141466B2 Method of fabricating semiconductor device having gate insulating film comprising a silicate nitride film with interface insulating film 有权
标题翻译：具有栅极绝缘膜的半导体器件的制造方法包括具有界面绝缘膜的硅酸盐氮化物膜
公开(公告)号：US07141466B2
公开(公告)日：2006-11-28
申请号：US10962673
申请日：2004-10-13
申请人： Motoyuki Sato , Kazuhiro Eguchi , Seiji Inumiya , Katsuyuki Sekine , Akio Kaneko
发明人： Motoyuki Sato , Kazuhiro Eguchi , Seiji Inumiya , Katsuyuki Sekine , Akio Kaneko
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/518 , H01L21/2807 , H01L21/28194 , H01L21/28202 , H01L29/513 , H01L29/78
摘要： According to the present invention, there is provided a semiconductor device comprising:an interface insulating film selectively formed on a predetermined region of a semiconductor substrate, and having a film thickness of substantially one atomic layer;a gate insulating film formed on said interface insulating film, and having a dielectric constant higher than that of said interface insulating film;a gate electrode formed on said gate insulating film; andsource and drain regions formed in a surface region of said semiconductor substrate on two sides of a channel region positioned below said gate electrode.
摘要翻译：根据本发明，提供了一种半导体器件，包括：界面绝缘膜，其选择性地形成在半导体衬底的预定区域上，并且具有基本上一个原子层的膜厚度; 形成在所述界面绝缘膜上并具有高于所述界面绝缘膜的介电常数的介电常数的栅极绝缘膜; 形成在所述栅极绝缘膜上的栅电极; 以及源极和漏极区，形成在位于所述栅电极下方的沟道区的两侧的所述半导体衬底的表面区域中。

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