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21. 发明授权

US07074677B1 Memory with improved charge-trapping dielectric layer 有权
标题翻译：具有改进的电荷俘获介电层的存储器
公开(公告)号：US07074677B1
公开(公告)日：2006-07-11
申请号：US10307189
申请日：2002-11-29
申请人： Arvind Halliyal , Minh Van Ngo , Hidehiko Shiraiwa , Rinji Sugino
发明人： Arvind Halliyal , Minh Van Ngo , Hidehiko Shiraiwa , Rinji Sugino
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11568 , Y10S438/954
摘要： A manufacturing method for a Flash memory includes depositing a first dielectric layer on a semiconductor substrate. A low hydrogen charge-trapping dielectric layer is deposited followed by a second dielectric layer. First and second bitlines are implanted and a wordline layer is deposited.
摘要翻译：一种闪速存储器的制造方法，包括在半导体衬底上沉积第一介电层。沉积低氢电荷捕获电介质层，然后沉积第二介电层。植入第一和第二位线，并存放字线层。

22. 发明授权

US07023046B2 Undoped oxide liner/BPSG for improved data retention 有权
标题翻译：未掺杂氧化物衬垫/ BPSG，以改善数据保留
公开(公告)号：US07023046B2
公开(公告)日：2006-04-04
申请号：US10617450
申请日：2003-07-11
申请人： Minh Van Ngo , Angela Hui , Ning Cheng , Jeyong Park , Jean Yee-Mei Yang , Robert A. Huertas , Tazrien Kamal , Pei-Yuan Gao , Tyagamohan Gottipati
发明人： Minh Van Ngo , Angela Hui , Ning Cheng , Jeyong Park , Jean Yee-Mei Yang , Robert A. Huertas , Tazrien Kamal , Pei-Yuan Gao , Tyagamohan Gottipati
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L21/02129 , H01L21/02164 , H01L21/022 , H01L21/02271 , H01L21/31612 , H01L21/31625 , H01L27/115 , H01L29/511
摘要： Semiconductor devices with improved data retention are formed by depositing an undoped oxide liner on spaced apart transistors followed by in situ deposition of a BPSG layer. Embodiments include depositing an undoped silicon oxide liner derived from TEOS, as at a thickness of 400 Å to 600 Å, on transistors of a non-volatile semiconductor device, as by sub-atmospheric chemical vapor deposition, followed by depositing the BPSG layer in the same deposition chamber.
摘要翻译：具有改进的数据保留的半导体器件通过将未掺杂的氧化物衬底沉积在间隔开的晶体管上，然后原位沉积BPSG层来形成。实施例包括在非易失性半导体器件的晶体管上沉积衍生自TEOS的未掺杂的氧化硅衬垫，如非易失性半导体器件的晶体管，如通过亚大气压化学气相沉积，然后将BPSG层沉积在相同的沉积室。

23. 发明授权

US07005357B2 Low stress sidewall spacer in integrated circuit technology 有权
标题翻译：集成电路技术中的低应力侧壁间隔
公开(公告)号：US07005357B2
公开(公告)日：2006-02-28
申请号：US10756023
申请日：2004-01-12
申请人： Minh Van Ngo , Simon Siu-Sing Chan , Paul R. Besser , Paul L. King , Errol Todd Ryan , Robert J. Chiu
发明人： Minh Van Ngo , Simon Siu-Sing Chan , Paul R. Besser , Paul L. King , Errol Todd Ryan , Robert J. Chiu
IPC分类号： H01L21/336 , H01L21/441
CPC分类号： H01L29/6659 , H01L29/665
摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A sidewall spacer is formed around the gate using a low power plasma enhanced chemical vapor deposition process A silicide is formed on the source/drain junctions and on the gate, and an interlayer dielectric is deposited above the semiconductor substrate. Contacts are then formed in the interlayer dielectric to the silicide.
摘要翻译：提供一种形成具有半导体衬底的集成电路的方法。在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。在半导体衬底中形成源极/漏极结。使用低功率等离子体增强化学气相沉积工艺在栅极周围形成侧壁间隔物。在源极/漏极结和栅极上形成硅化物，并且在半导体衬底上沉积层间电介质。然后在层间电介质中形成与硅化物的接触。

24. 发明授权

US06861350B1 Method of manufacturing semiconductor device comprising silicon-rich tasin metal gate electrode 有权
标题翻译：一种制造半导体器件的方法，所述半导体器件包括富含硅的金属栅电极
公开(公告)号：US06861350B1
公开(公告)日：2005-03-01
申请号：US10464508
申请日：2003-06-19
申请人： Minh Van Ngo , Christy Mei-Chu Woo , Jinsong Yin , James Pan , Paul R. Besser
发明人： Minh Van Ngo , Christy Mei-Chu Woo , Jinsong Yin , James Pan , Paul R. Besser
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H10L21/4763 , H10L21/44
CPC分类号： H01L29/66606 , H01L21/28088 , H01L29/4966 , H01L29/66545
摘要： Micro-miniaturized semiconductor devices are fabricated with silicon-rich tantalum silicon nitride replacement metal gate electrodes. Embodiments include removing a removable gate, depositing a layer of tantalum nitride, as by PVD at a thickness of 25 Å to 75 Å, and then introducing silicon into the deposited tantalum nitride layer by thermal soaking in silane or silane plasma treatment to form a layer of silicon-rich tantalum silicon nitride. In another embodiment, the intermediate structure is subjected to thermal soaking in silane or silane plasma treatment before and after depositing the tantalum nitride layer. Embodiments further include pretreating the intermediate structure with silane prior to depositing the tantalum nitride layer, treating the deposited tantalum nitride layer with silane, and repeating these steps a number of times to form a plurality of sub-layers of silicon-rich tantalum silicon nitride.
摘要翻译：微型半导体器件由富含硅的钽氮化硅替代金属栅电极制成。实施例包括去除可移除栅极，通过PVD沉积氮化钽层，厚度为25埃，然后通过在硅烷或硅烷等离子体处理中热浸泡形成层，将硅引入沉积的氮化钽层中的富硅钽硅氮化物。在另一个实施方案中，在沉积氮化钽层之前和之后，使中间体在硅烷或硅烷等离子体处理中进行热浸。实施例还包括在沉积氮化钽层之前用硅烷预处理中间结构，用硅烷处理沉积的氮化钽层，并重复这些步骤多次以形成多个富硅钽硅氮化物的子层。

25. 发明授权

US06809043B1 Multi-stage, low deposition rate PECVD oxide 有权
标题翻译：多级，低沉积速率PECVD氧化物
公开(公告)号：US06809043B1
公开(公告)日：2004-10-26
申请号：US10173611
申请日：2002-06-19
申请人： Minh Van Ngo , Robert A. Huertas , Hieu Pham
发明人： Minh Van Ngo , Robert A. Huertas , Hieu Pham
IPC分类号： H01L2131
CPC分类号： H01L21/02164 , H01L21/02211 , H01L21/02274 , H01L21/0228 , H01L21/28247 , H01L21/3144 , H01L21/3145 , H01L21/31612
摘要： A silicon oxide layer is deposited at a thickness of about 50 Å or less by a multi-stage method comprising depositing a sub-layer of silicon oxide in each stage by PECVD at a low deposition rate. Embodiments include depositing a silicon dioxide liner over a gate electrode in at least four stages, each stage comprising depositing a sub-layer at a thickness of 10 Å or less.
摘要翻译：氧化硅层通过多级方法沉积在大约等于或小于50埃的厚度，包括通过PECVD以低沉积速率在每个阶段沉积氧化硅的子层。实施例包括在至少四个阶段中在栅电极上沉积二氧化硅衬垫，每个阶段包括沉积厚度为或更小的子层。

26. 发明授权

US06770905B1 Implantation for the formation of CuX layer in an organic memory device 失效
标题翻译：用于在有机存储器件中形成CuX层的植入
公开(公告)号：US06770905B1
公开(公告)日：2004-08-03
申请号：US10314054
申请日：2002-12-05
申请人： Matthew S. Buynoski , Suzette K. Pangrle , Sergey D. Lopatin , Minh Van Ngo
发明人： Matthew S. Buynoski , Suzette K. Pangrle , Sergey D. Lopatin , Minh Van Ngo
IPC分类号： H01L2940
CPC分类号： H01L51/0037 , B82Y10/00 , G11C13/0014 , G11C13/0016 , H01L27/28 , H01L51/0035 , H01L51/0036 , H01L51/0043 , H01L51/0046 , H01L51/0048 , H01L51/0052 , H01L51/0053 , H01L51/0059 , H01L51/0062 , H01L51/0077 , H01L51/0078 , H01L51/0081 , H01L51/0085
摘要： An organic memory cell having a CuX layer made by implantation is disclosed. The organic memory cell is made of two electrodes, at least one containing copper, with a controllably conductive media between the two electrodes. The controllably conductive media contains an organic semiconductor layer and CuX layer made by implantation of a Group VIB element.
摘要翻译：公开了一种具有通过注入制造的CuX层的有机存储单元。有机存储单元由两个电极组成，至少一个电极含有铜，两个电极之间具有可控导电介质。可控导电介质包含通过注入VIB族元素制成的有机半导体层和CuX层。

27. 发明授权

US06770523B1 Method for semiconductor wafer planarization by CMP stop layer formation 失效
标题翻译：通过CMP停止层形成的半导体晶片平面化方法
公开(公告)号：US06770523B1
公开(公告)日：2004-08-03
申请号：US10190397
申请日：2002-07-02
申请人： Kashmir S. Sahota , Jeffrey P. Erhardt , Arvind Halliyal , Minh Van Ngo , Krishnashree Achuthan
发明人： Kashmir S. Sahota , Jeffrey P. Erhardt , Arvind Halliyal , Minh Van Ngo , Krishnashree Achuthan
IPC分类号： H01L218238
CPC分类号： H01L21/76229 , H01L21/31053
摘要： A method of manufacturing an integrated circuit is provided having a semiconductor wafer. A chemical-mechanical polishing stop layer is deposited on the semiconductor wafer and a first photoresist layer is processed over the chemical-mechanical polishing stop layer. The chemical-mechanical polishing stop layer and the semiconductor wafer are patterned to form a shallow trench and a shallow trench isolation material is deposited on the chemical-mechanical polishing stop layer and in the shallow trench. A second photoresist layer is processed over the shallow trench isolation material leaving the shallow trench uncovered. The uncovered shallow trench is then treated to become a chemical-mechanical polishing stop area. The shallow trench isolation material is then chemical-mechanical polished to be co-planar with the chemical-mechanical stop layer and the chemical-mechanical polishing stop treated area.
摘要翻译：提供了具有半导体晶片的集成电路的制造方法。化学机械抛光停止层沉积在半导体晶片上，并且在化学机械抛光停止层上处理第一光致抗蚀剂层。化学机械抛光停止层和半导体晶片被图案化以形成浅沟槽，浅沟槽隔离材料沉积在化学机械抛光停止层和浅沟槽中。在浅沟槽隔离材料上处理第二光致抗蚀剂层，留下未覆盖的浅沟槽。然后将未覆盖的浅沟槽处理成为化学机械抛光停止区域。然后将浅沟槽隔离材料进行化学机械抛光以与化学 - 机械停止层和化学 - 机械抛光停止处理区共面。

28. 发明授权

US06764966B1 Spacers with a graded dielectric constant for semiconductor devices having a high-K dielectric 有权
标题翻译：具有高K电介质的半导体器件具有渐变介电常数的间隔物
公开(公告)号：US06764966B1
公开(公告)日：2004-07-20
申请号：US10085278
申请日：2002-02-27
申请人： William George En , Arvind Halliyal , Ming-Ren Lin , Minh Van Ngo , Chih-Yuh Yang
发明人： William George En , Arvind Halliyal , Ming-Ren Lin , Minh Van Ngo , Chih-Yuh Yang
IPC分类号： H01L2128
CPC分类号： H01L29/6656 , H01L29/66833 , H01L29/78
摘要： A semiconductor device formed on a semiconductor substrate having an active region and a method of making the same is disclosed. The semiconductor device includes a dielectric layer interposed between a gate electrode and the semiconductor substrate. Further, the semiconductor device includes graded dielectric constant spacers formed on sidewalls of the dielectric layer, sidewalls of the gate electrode and portions of an upper surface of the semiconductor substrate. The dielectric constant of the graded dielectric constant spacers decreases in a direction away from the sidewalls of the dielectric layer.
摘要翻译：公开了一种形成在具有有源区的半导体衬底上的半导体器件及其制造方法。半导体器件包括插入在栅电极和半导体衬底之间的电介质层。此外，半导体器件包括形成在电介质层的侧壁，栅电极的侧壁和半导体衬底的上表面的部分上的渐变介电常数间隔物。梯度介电常数间隔物的介电常数在远离介电层的侧壁的方向上减小。

29. 发明授权

US06731006B1 Doped copper interconnects using laser thermal annealing 失效
标题翻译：使用激光热退火的掺杂铜互连
公开(公告)号：US06731006B1
公开(公告)日：2004-05-04
申请号：US10323941
申请日：2002-12-20
申请人： Arvind Halliyal , Minh Van Ngo
发明人： Arvind Halliyal , Minh Van Ngo
IPC分类号： H01L2348
CPC分类号： H01L21/76802 , H01L21/76804 , H01L21/76807 , H01L21/76877 , H01L21/76886 , H01L23/5226 , H01L23/53233 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and method of making the same includes a first metallization level, a first etch stop layer, a dielectric layer and an opening extending through the dielectric layer and the first etch stop layer. The first etch stop layer is disposed over the first metallization level. Metal within the opening forms a second metal feature, and the metal can comprise copper or a copper alloy. Dopants are introduced into the metal and are activated by laser thermal annealing. A concentration of the dopants within the metal in a lower portion of the second metal feature proximate the first metal feature is greater than a concentration of dopants in a central portion of the second metal feature, and a concentration of the dopants within the metal in an upper portion of the second metal feature is greater than a concentration of dopants in the central portion of the second metal feature.
摘要翻译：半导体器件及其制造方法包括第一金属化层，第一蚀刻停止层，电介质层和延伸穿过介电层和第一蚀刻停止层的开口。第一蚀刻停止层设置在第一金属化层上。开口内的金属形成第二金属特征，金属可以包括铜或铜合金。将掺杂剂引入金属中并通过激光热退火来激活。在第二金属特征附近的第二金属特征的下部中的金属内的掺杂剂的浓度大于第二金属特征的中心部分中的掺杂剂的浓度，并且金属中掺杂剂的浓度在第二金属特征的上部大于第二金属特征的中心部分中的掺杂剂的浓度。

30. 发明授权

US06727176B2 Method of forming reliable Cu interconnects 失效
标题翻译：形成可靠的Cu互连的方法
公开(公告)号：US06727176B2
公开(公告)日：2004-04-27
申请号：US09986267
申请日：2001-11-08
申请人： Minh Van Ngo , Arvind Halliyal , Eric Paton
发明人： Minh Van Ngo , Arvind Halliyal , Eric Paton
IPC分类号： H01L2144
CPC分类号： H01L21/76882
摘要： Reliable Cu interconnects are formed by filling an opening in a dielectric layer with Cu and then laser thermal annealing in NH3 to reduce copper oxide and to reflow the deposited Cu, thereby eliminating voids and reducing contact resistance. Embodiments include laser thermal annealing employing an NH3 flow rate of about 200 to about 2,000 sccn.
摘要翻译：通过用Cu填充电介质层中的开口，然后在NH 3中激光热退火以形成可靠的Cu互连，以减少氧化铜和回流沉积的Cu，从而消除空隙并降低接触电阻。实施例包括使用约200至约2,000sccn的NH 3流速的激光热退火。

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