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21. 发明授权

US06664837B1 Delay line trim unit having consistent performance under varying process and temperature conditions 有权
标题翻译：延迟线修剪单元在不同的工艺和温度条件下具有一致的性能
公开(公告)号：US06664837B1
公开(公告)日：2003-12-16
申请号：US10247241
申请日：2002-09-18
申请人： Kwansuhk Oh , Raymond C. Pang
发明人： Kwansuhk Oh , Raymond C. Pang
IPC分类号： H03H1126
CPC分类号： H03L7/0814 , H03K5/133 , H03K2005/00065 , H03K2005/00221 , H03L7/0818
摘要： A delay circuit has a delay that is consistent under varying process and temperature conditions. The delay through a delay path is controlled by inserting resistors on the pull-up and pull-down paths of the delaying inverters. Each resistor has a resistance value that is determined by a varying a number of enabled similarly-sized transistors coupled in parallel across the resistor, rather than by varying the size of a single transistor. In one embodiment, a first transistor in each resistor is always enabled, while additional transistors are enabled using select signals. In one embodiment, the select signals are provided by configuration memory cells in a PLD. Other embodiments include additional delay paths and a multiplexer circuit that selects one of the delay paths. The described delay circuit is particularly useful in a DLL trim unit, where variations between resistors can cause jitter and locking problems in the DLL.
摘要翻译：延迟电路具有在变化的工艺和温度条件下是一致的延迟。通过延迟路径的延迟通过在延迟逆变器的上拉和下拉路径上插入电阻来控制。每个电阻器具有由在电阻器上并联耦合的使能相似尺寸的晶体管的数量的变化确定的电阻值，而不是通过改变单个晶体管的尺寸来确定。在一个实施例中，每个电阻器中的第一晶体管总是使能，而使用选择信号启用附加晶体管。在一个实施例中，选择信号由PLD中的配置存储器单元提供。其他实施例包括额外的延迟路径和选择延迟路径之一的多路复用器电路。所描述的延迟电路在DLL修剪单元中特别有用，其中电阻之间的变化可能导致DLL中的抖动和锁定问题。

22. 发明授权

US06373779B1 Block RAM having multiple configurable write modes for use in a field programmable gate array 有权
标题翻译：具有用于现场可编程门阵列的多个可配置写模式的块RAM
公开(公告)号：US06373779B1
公开(公告)日：2002-04-16
申请号：US09574300
申请日：2000-05-19
申请人： Raymond C. Pang , Steven P. Young
发明人： Raymond C. Pang , Steven P. Young
IPC分类号： G11C800
CPC分类号： H03K19/1776 , G11C7/1045 , G11C7/1075 , G11C8/16
摘要： A dedicated block random access memory (RAM) is provided for a programmable logic device (PLD), such as a field programmable gate array (FPGA). The block RAM includes a memory cell array and control logic that is configurable to select one of a plurality of write modes for accessing the memory cell array. In one embodiment, the write modes include a write with write-back mode, a write without write-back mode, and a read then write mode. The control logic selects the write mode in response to configuration bits stored in corresponding configuration memory cells of the PLD. The configuration bits are programmed during configuration of the PLD. In one variation, the control logic selects the write mode in response to user signals. In a particular embodiment, the block RAM is a dual-port memory having a first port and a second port. In this embodiment, the first and second ports can be independently configured to have different (or the same) write modes. The widths of the first and second ports can also be independently configured.
摘要翻译：为诸如现场可编程门阵列（FPGA）的可编程逻辑器件（PLD）提供专用块随机存取存储器（RAM）。块RAM包括存储单元阵列和可配置为选择用于访问存储单元阵列的多个写入模式之一的控制逻辑。在一个实施例中，写入模式包括具有回写模式的写入，不具有回写模式的写入以及读取和写入模式。响应于存储在PLD的相应配置存储器单元中的配置位，控制逻辑选择写入模式。在配置PLD期间对配置位进行编程。在一个变化中，控制逻辑响应于用户信号选择写入模式。在特定实施例中，块RAM是具有第一端口和第二端口的双端口存储器。在该实施例中，第一和第二端口可以被独立地配置为具有不同的（或相同的）写入模式。第一和第二端口的宽度也可以独立地配置。

23. 发明授权

US07535278B1 Circuits and methods of using parallel counter controlled delay lines to generate a clock signal 有权
标题翻译：使用并行计数器控制的延迟线来产生时钟信号的电路和方法
公开(公告)号：US07535278B1
公开(公告)日：2009-05-19
申请号：US11717810
申请日：2007-03-13
申请人： Robert M. Ondris , Raymond C. Pang , Kwansuhk Oh
发明人： Robert M. Ondris , Raymond C. Pang , Kwansuhk Oh
IPC分类号： G06F1/04 , H03H11/26
CPC分类号： G06F1/08
摘要： A clock manager circuit includes a number of clock output blocks, each providing an independent output. Counter controlled delay devices (CCDs) are used in these clock output blocks. To achieve full cycle delays, the CCDs are placed in parallel with outputs of the CCD outputs driving set and reset terminals of a common latch. The parallel connection of the CCDs, as opposed to a series connection, offers an increase in maximum frequency and possibly fewer needed CCDs than if the CCDs are placed in series. In one embodiment, at least one of the CCDs includes a counter/compare circuit with a frequency divider enabling the frequency of the CCD to be varied relative to the common input clock.
摘要翻译：时钟管理器电路包括多个时钟输出块，每个时钟输出块提供独立的输出。这些时钟输出块中使用了计数器控制延迟器（CCD）。为了实现全周期延迟，CCD与公共锁存器的CCD输出驱动装置和复位端子的输出并联放置。与串联连接相比，CCD的并联连接提供了最大频率的增加，并且与CCD串联放置相比，可能需要更少的CCD。在一个实施例中，CCD中的至少一个包括具有使得CCD的频率相对于公共输入时钟变化的分频器的计数器/比较电路。

24. 发明授权

US07491576B1 Yield-enhancing methods of providing a family of scaled integrated circuits 有权
标题翻译：提供一系列缩放集成电路的产量增强方法
公开(公告)号：US07491576B1
公开(公告)日：2009-02-17
申请号：US11333990
申请日：2006-01-17
申请人： Steven P. Young , Trevor J. Bauer , F. Erich Goetting , P. Hugo Lamarche , Patrick J. McGuire , Kwansuhk Oh , Raymond C. Pang , Bruce E. Talley , Paul Ying-Fung Wu
发明人： Steven P. Young , Trevor J. Bauer , F. Erich Goetting , P. Hugo Lamarche , Patrick J. McGuire , Kwansuhk Oh , Raymond C. Pang , Bruce E. Talley , Paul Ying-Fung Wu
IPC分类号： H01L21/66 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L22/22 , H01L23/544 , H01L2223/5444 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit die (e.g., a programmable logic device (PLD) die) is manufactured that has the capability of being configured as at least two differently-sized family members. The IC die is tested prior to packaging. If a first portion of the IC die is fully functional, but a second portion includes a localized defect, then the IC die is packaged with a product selection code that configures the IC die to operate as only the first portion of the die. The second portion of the die is deliberately rendered non-operational. Therefore, the IC die can still be sold as a fully functional packaged IC.
摘要翻译：制造集成电路管芯（例如，可编程逻辑器件（PLD）管芯），其具有被配置为至少两个不同尺寸的家庭部件的能力。在封装之前测试IC芯片。如果IC芯片的第一部分是完全功能的，但是第二部分包括局部缺陷，则IC芯片被封装成产品选择代码，所述产品选择代码构成IC裸片仅作为芯片的第一部分进行操作。死亡的第二部分故意使其不能运作。因此，IC芯片仍然可以作为全功能封装IC出售。

25. 发明授权

US07190202B1 Trim unit having less jitter 有权
标题翻译：修剪单元具有较少的抖动
公开(公告)号：US07190202B1
公开(公告)日：2007-03-13
申请号：US11099908
申请日：2005-04-05
申请人： Kwansuhk Oh , Raymond C. Pang
发明人： Kwansuhk Oh , Raymond C. Pang
IPC分类号： H03L7/00
CPC分类号： H03L7/0814 , H03L7/0818
摘要： A trim unit includes a delay line and one or more individually selectable load elements. The delay line has a first end to receive an input clock signal, and has a second end to generate an output clock signal. Each load element includes a select transistor and a load capacitor coupled in series between the delay line and ground potential, and includes a filter circuit having an input to receive a select signal and having an output coupled to a gate of the select transistor. Upon assertion of each select signal, the filter circuit gradually charges the gate of the select transistor, which in turn causes the load element to gradually increase the phase-delay between the input and output clock signals.
摘要翻译：修剪单元包括延迟线和一个或多个可单独选择的负载元件。延迟线具有接收输入时钟信号的第一端，并具有产生输出时钟信号的第二端。每个负载元件包括在延迟线和接地电位之间串联耦合的选择晶体管和负载电容器，并且包括具有输入以接收选择信号并具有耦合到选择晶体管的栅极的输出的滤波器电路。在确定每个选择信号时，滤波器电路逐渐对选择晶体管的栅极充电，这又导致负载元件逐渐增加输入和输出时钟信号之间的相位延迟。

26. 发明授权

US07058177B1 Partially encrypted bitstream method 失效
标题翻译：部分加密比特流方法
公开(公告)号：US07058177B1
公开(公告)日：2006-06-06
申请号：US09724974
申请日：2000-11-28
申请人： Stephen M. Trimberger , Raymond C. Pang , Walter N. Sze
发明人： Stephen M. Trimberger , Raymond C. Pang , Walter N. Sze
IPC分类号： H04L9/00
CPC分类号： G06F21/76 , H04L9/0637 , H04L9/0894 , H04L2209/12 , H04L2209/34
摘要： It is sometimes desirable to encrypt a design for loading into a PLD so that an attacker may not learn and copy the design as it is being copied into the PLD. According to the invention, a method for generating a bitstream for storing an encrypted design begins by generating an unencrypted bitstream including bits representing the design and bits that control loading of the design. The bits representing the design are encrypted and are combined with the bits that control loading, which are not encrypted.
摘要翻译：有时期望加密设计以加载到PLD中，使得攻击者可能不会在将设计复制到PLD中时学习和复制设计。根据本发明，用于生成用于存储加密设计的比特流的方法开始于生成一个未加密比特流，包括表示设计的比特和控制加载设计的比特。表示设计的位被加密，并且与控制加载的位组合，这些位未被加密。

27. 发明授权

US07046052B1 Phase matched clock divider 有权
标题翻译：相位匹配时钟分频器
公开(公告)号：US07046052B1
公开(公告)日：2006-05-16
申请号：US10837210
申请日：2004-04-30
申请人： Andrew K. Percey , Raymond C. Pang
发明人： Andrew K. Percey , Raymond C. Pang
IPC分类号： H03K21/00 , H03K23/00 , H03K25/00
CPC分类号： H03K23/50
摘要： A phase matched clock divider includes a first feed-through flip-flop that receives a first input clock signal, and in response, provides a first output clock signal having the same frequency. The first feed-through flip-flop is enabled and disabled in response to a first reset signal. A plurality of series-connected flip-flops each receives the first input clock signal, and in response, provides a divided output clock signal. Each of the series-connected flip-flops is enabled and disabled in response to a second reset signal. The first and second release signals asynchronously disable the associated flip-flops in response to a third reset signal. The first release signal synchronously enables the first feed-through flip-flop in response to the third reset signal and a release clock signal. The second release signal enables the series-connected flip-flops in response to the third reset signal and a release control signal.
摘要翻译：相位匹配时钟分频器包括接收第一输入时钟信号的第一馈通触发器，并且作为响应，提供具有相同频率的第一输出时钟信号。响应于第一复位信号，第一馈通触发器被使能和禁止。多个串联触发器各自接收第一输入时钟信号，作为响应，提供分频的输出时钟信号。每个串联的触发器响应于第二复位信号被使能和禁止。响应于第三复位信号，第一和第二释放信号异步地禁用相关联的触发器。响应于第三复位信号和释放时钟信号，第一释放信号同步使第一馈通触发器使能。第二释放信号使得串联连接的触发器响应于第三复位信号和释放控制信号。

28. 发明授权

US06957340B1 Encryption key for multi-key encryption in programmable logic device 有权
标题翻译：可编程逻辑器件中多键加密的加密密钥
公开(公告)号：US06957340B1
公开(公告)日：2005-10-18
申请号：US09724873
申请日：2000-11-28
申请人： Raymond C. Pang , Stephen M. Trimberger , Jennifer Wong
发明人： Raymond C. Pang , Stephen M. Trimberger , Jennifer Wong
IPC分类号： G06F21/00 , H04L9/00 , H04L9/14
CPC分类号： G06F21/76 , H04L9/0637 , H04L9/0894 , H04L9/14
摘要： It is sometimes desirable to protect a design used in a PLD from being copied. If the design is stored in a different device from the PLD and read into the PLD through a bitstream, an unencrypted bitstream could be observed and copied as it is being loaded. According to the invention, a bitstream for configuring a PLD with an encrypted design includes unencrypted words for controlling loading of the configuration bitstream and encrypted words that actually specify the design.
摘要翻译：有时期望保护PLD中使用的设计不被复制。如果设计存储在与PLD不同的设备中并通过比特流读入PLD，则在加载时可以观察和复制未加密的比特流。根据本发明，用于配置具有加密设计的PLD的比特流包括用于控制配置比特流的加载的未加密的字和实际指定设计的加密的字。

29. 发明授权

US06897676B1 Configuration enable bits for PLD configurable blocks 有权
标题翻译：用于PLD可配置块的配置使能位
公开(公告)号：US06897676B1
公开(公告)日：2005-05-24
申请号：US10454055
申请日：2003-06-04
申请人： Raymond C. Pang
发明人： Raymond C. Pang
IPC分类号： H03K19/177 , H03K19/173
CPC分类号： H03K19/17748 , H03K19/1776
摘要： A programmable logic device (PLD) includes columns of block memory interposed between columns of configurable logic blocks (CLBs). Each column of block memory includes a plurality of random access memories (RAMs) that share common configuration address lines that do not allow the RAMs in block memory column to be individually addressed. For some embodiments, each RAM in the column includes interface logic that selectively enables the RAM during configuration operations in response to a configuration enable bit, which may be provided to the PLD in a configuration bitstream and stored in a shadow register associated with the RAM.
摘要翻译：可编程逻辑器件（PLD）包括插入在可配置逻辑块（CLB）列之间的块存储器列。块存储器的每列包括共享共同配置地址线的多个随机存取存储器（RAM），这些配置地址线不允许块存储器列中的RAM被单独寻址。对于一些实施例，列中的每个RAM包括接口逻辑，其响应于配置使能位可以在配置操作期间选择性地启用RAM，该配置使能位可以在配置比特流中提供给PLD并存储在与RAM相关联的影子寄存器中。

30. 发明授权

US06366117B1 Nonvolatile/battery-backed key in PLD 有权
标题翻译： PLD中的非易失性/电池供电密钥
公开(公告)号：US06366117B1
公开(公告)日：2002-04-02
申请号：US09724973
申请日：2000-11-28
申请人： Raymond C. Pang , Jennifer Wong , Scott O. Frake , Jane W. Sowards , Venu M. Kondapalli , F. Erich Goetting , Stephen M. Trimberger , Kameswara K. Rao
发明人： Raymond C. Pang , Jennifer Wong , Scott O. Frake , Jane W. Sowards , Venu M. Kondapalli , F. Erich Goetting , Stephen M. Trimberger , Kameswara K. Rao
IPC分类号： H04L900
CPC分类号： G06F21/76
摘要： It is sometimes desirable to encrypt a design for loading into a PLD so that an attacker may not learn and copy the design as it is being copied into the PLD. According to the invention, the encrypted design is decrypted by a key or keys within the PLD that are preserved when power is removed by either being stored in nonvolatile memory or by being backed up with a battery that switches into operation when the power is removed from the PLD.
摘要翻译：有时期望加密设计以加载到PLD中，使得攻击者可能不会在将设计复制到PLD中时学习和复制设计。根据本发明，加密设计由PLD内的密钥或密钥解密，当通过存储在非易失性存储器中的电力被去除或通过在电力被从 PLD。

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