专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09479179B2 Measuring setup and hold times using a virtual delay 有权
标题翻译：使用虚拟延迟测量设置和保持时间
公开(公告)号：US09479179B2
公开(公告)日：2016-10-25
申请号：US14263329
申请日：2014-04-28
申请人： Globalfoundries Inc.
发明人： Andy T. Nguyen , Navneet Jain
IPC分类号： G01R31/02 , H03K23/50 , H03K5/22 , G01R31/317
CPC分类号： H03K23/50 , G01R31/31727 , H03K5/22
摘要： Methodologies and an apparatus for measuring setup and hold times of fabricated semiconductor devices are provided. Embodiments include: providing a first digital frequency divider having an input and an output, the input of the first digital frequency divider receiving a first signal indicating an oscillating signal with a first delay; providing a second digital frequency divider having an input and output, the input of the second digital frequency divider receiving a second signal indicating the oscillating signal with a second delay; and providing a flip-flop having an input and an output, wherein the input of the flip-flop is coupled to the output of the second digital frequency divider and a data signal and clock signal for measuring a set-up time or hold time of a device under test are generated.
摘要翻译：提供了用于测量制造的半导体器件的建立和保持时间的方法和装置。实施例包括：提供具有输入和输出的第一数字分频器，第一数字分频器的输入接收指示具有第一延迟的振荡信号的第一信号; 提供具有输入和输出的第二数字分频器，所述第二数字分频器的输入端以第二延迟接收指示所述振荡信号的第二信号; 以及提供具有输入和输出的触发器，其中所述触发器的输入耦合到所述第二数字分频器的输出，以及数据信号和时钟信号，用于测量所述触发器的建立时间或保持时间生成被测设备。

2. 发明申请

US20150129748A1 Multiple Data Rate Counter, Data Converter including the Same, and Image Sensor Including the Same 审中-公开
标题翻译：多数据速率计数器，包括它的数据转换器和包括它的图像传感器
公开(公告)号：US20150129748A1
公开(公告)日：2015-05-14
申请号：US14602377
申请日：2015-01-22
申请人： Kyung-min Kim , Kyoung-min Koh , Yoon-seok Han
发明人： Kyung-min Kim , Kyoung-min Koh , Yoon-seok Han
IPC分类号： H03K23/50 , H04N5/378 , H03K21/10
CPC分类号： H03K23/50 , H03K21/10 , H03K23/58 , H04N5/378
摘要： A counter includes a buffer unit and a ripple counter. The buffer unit generates at least one least significant signal of a count by buffering at least one clock signal until a termination time point. The ripple counter generates at least one most significant signal of the count by sequentially toggling in response to at least one of the least significant signal. The counter performs multiple data rate counting with enhance operation speed and reduced power consumption.
摘要翻译：计数器包括一个缓冲单元和一个纹波计数器。缓冲单元通过缓冲至少一个时钟信号直到终止时间点来产生计数的至少一个最低有效信号。纹波计数器通过响应于至少一个最低有效信号顺序切换来产生计数的至少一个最高有效信号。计数器可以提高操作速度和降低功耗，从而实现多种数据速率计数。

3. 发明授权

US08212602B2 System and method for signal mixing based on high order harmonics 有权
标题翻译：基于高次谐波信号混合的系统和方法
公开(公告)号：US08212602B2
公开(公告)日：2012-07-03
申请号：US12873323
申请日：2010-09-01
申请人： Hao Meng , Peiqi Xuan
发明人： Hao Meng , Peiqi Xuan
IPC分类号： G06G7/12
CPC分类号： G06F1/06 , H03K23/50
摘要： A system and method for signal mixing using high-order harmonics of a local oscillation (LO) signal. In a radio frequency (RF) system, the input RF signal is converted to a lower frequency signal such as an intermediate frequency (IF) signal or a baseband signal for further processing. A voltage controlled oscillator (VCO) is often used to generate a VCO signal which is then divided down to provide the needed LO signals for down conversion. The present invention discloses a system and method for generating a composite harmonic signal based on a linear combination of divided down LO signals with specific phase shifts. Consequently a VCO signal with lower frequency can be used to conserve power. The composite harmonic signal is mixed with the input RF signal to generate a series of mixed signal including one associated with a high-order harmonic of the divided down LO signal. Systems to implement the high order harmonic mixing is also disclosed which comprises a plurality of mixer sections with configurable weighting factors. A combination circuit is used to combine the weighted mixed signals which contains a term corresponding the mixing of the input RF signal with a high order LO harmonic.
摘要翻译：一种使用本地振荡（LO）信号的高次谐波进行信号混合的系统和方法。在射频（RF）系统中，输入RF信号被转换为诸如中频（IF）信号或基带信号的较低频率信号，用于进一步处理。压控振荡器（VCO）通常用于产生VCO信号，然后将其分频以提供所需的LO信号用于下变频。本发明公开了一种基于具有特定相移的分频LO信号的线性组合来生成复合谐波信号的系统和方法。因此，可以使用具有较低频率的VCO信号来节省功率。复合谐波信号与输入RF信号混合，以产生一系列混合信号，包括与分频LO信号的高次谐波相关的混合信号。还公开了实现高阶谐波混合的系统，其包括具有可配置加权因子的多个混频器部分。组合电路用于组合加权混合信号，该混合信号包含对应于输入RF信号的混合的项与高阶LO谐波。

4. 发明申请

US20120007638A1 SYSTEM AND METHOD FOR MULTIPLE-PHASE CLOCK GENERATION 有权
标题翻译：多相时钟生成系统与方法
公开(公告)号：US20120007638A1
公开(公告)日：2012-01-12
申请号：US12872371
申请日：2010-08-31
申请人： Hao Meng , Peiqi Xuan
发明人： Hao Meng , Peiqi Xuan
IPC分类号： H03K23/00
CPC分类号： G06F1/06 , H03K23/50
摘要： A system and method of clock generation to provide divided-by-2 clocks with prescribed phase shifts are disclosed. In a communication system with high-order harmonic mixing, the system requires LO signals with a set of prescribed phase shifts, such as 0°, 45°, 90°, and 135°, or 0°, 60° and 120°. Often, the clock generation system involves a divide-by-2 divider to derive the clock signals with the prescribed phase shifts. In a conventional implementation of the divide-by-2 divider, the system is subject to phase uncertainty in the output signal. Accordingly, a system comprises multiple latch pairs and respective differential clocks are used to generate the clocks with the set of correct prescribed phase shifts.
摘要翻译：公开了一种提供具有规定相移的二分之一秒钟的时钟产生系统和方法。在具有高次谐波混合的通信系统中，系统需要具有一定规定相移的LO信号，例如0°，45°，90°和135°，或0°，60°和120°。通常，时钟发生系统涉及一个除以2的分频器，以规定的相移导出时钟信号。在2分频器的传统实现中，系统在输出信号中受到相位不确定性的影响。因此，系统包括多个锁存器对，并且使用相应的差分时钟来产生具有正确规定相移集合的时钟。

5. 发明授权

US07800417B2 Method and apparatus for generating frequency divided signals 有权
标题翻译：用于产生分频信号的方法和装置
公开(公告)号：US07800417B2
公开(公告)日：2010-09-21
申请号：US11740638
申请日：2007-04-26
申请人： Mel Bazes
发明人： Mel Bazes
IPC分类号： H03B19/00
CPC分类号： H03K5/1534 , H03K23/50
摘要： In a method for dividing a frequency of a clock signal, a first frequency divided signal is generated based on a clock signal. Rising edges in the first frequency divided signal are detected. Alternatively, falling edges in the first frequency divided signal are detected. An edge detection signal that includes a pulse for each detected edge is generated. A second frequency divided signal is generated based on the edge detection signal.
摘要翻译：在分频时钟信号的频率的方法中，基于时钟信号产生第一分频信号。检测第一分频信号中的上升沿。或者，检测第一分频信号中的下降沿。生成包含每个检测边缘的脉冲的边缘检测信号。基于边缘检测信号产生第二分频信号。

6. 发明授权

US07791979B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07791979B2
公开(公告)日：2010-09-07
申请号：US12402151
申请日：2009-03-11
申请人： Noboru Asauchi , Eitaro Otsuka
发明人： Noboru Asauchi , Eitaro Otsuka
IPC分类号： G11C8/00
CPC分类号： G11C16/06 , G06F21/6218 , H03K23/50
摘要： When the input write data is a value of a value greater than the existing data of the memory array 100, the semiconductor memory device enables writing of input write data to the memory array 100. In specific terms, the increment controller 150 reads the existing data from the memory array 100, and compares it with the write data latched to the 8-bit latch register 170. When the value of the write data is a value greater than the existing data, the increment controller 150 outputs the write enable signal WEN1 to the write/read controller 140, and executes writing of the write data latched to the 8-bit latch register 170 to the memory array 100.
摘要翻译：当输入写入数据是大于存储器阵列100的现有数据的值的值时，半导体存储器件能够将输入写入数据写入存储器阵列100.具体而言，增量控制器150读取现有数据并将其与锁存到8位锁存寄存器170的写入数据进行比较。当写入数据的值大于现有数据时，增量控制器150将写使能信号WEN1输出到写/读控制器140，并且将锁存到8位锁存寄存器170的写数据写入存储器阵列100。

7. 发明授权

US07522470B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07522470B2
公开(公告)日：2009-04-21
申请号：US11420535
申请日：2006-05-26
申请人： Noboru Asauchi , Eitaro Otsuka
发明人： Noboru Asauchi , Eitaro Otsuka
IPC分类号： G11C8/00
CPC分类号： G11C16/06 , G06F21/6218 , H03K23/50
摘要： When the input write data is a value of a value greater than the existing data of the memory array 100, the semiconductor memory device enables writing of input write data to the memory array 100. In specific terms, the increment controller 150 reads the existing data from the memory array 100, and compares it with the write data latched to the 8-bit latch register 170. When the value of the write data is a value greater than the existing data, the increment controller 150 outputs the write enable signal WEN1 to the write/read controller 140, and executes writing of the write data latched to the 8-bit latch register 170 to the memory array 100.
摘要翻译：当输入写入数据是大于存储器阵列100的现有数据的值的值时，半导体存储器件能够将输入写入数据写入存储器阵列100.具体而言，增量控制器150读取现有数据并将其与锁存到8位锁存寄存器170的写入数据进行比较。当写入数据的值大于现有数据时，增量控制器150将写使能信号WEN1输出到写/读控制器140，并且将锁存到8位锁存寄存器170的写数据写入存储器阵列100。

8. 发明授权

US07372300B2 Shift register and image display apparatus containing the same 失效
标题翻译：移位寄存器和包含它的图像显示装置
公开(公告)号：US07372300B2
公开(公告)日：2008-05-13
申请号：US11614384
申请日：2006-12-21
申请人： Youichi Tobita
发明人： Youichi Tobita
IPC分类号： G09G3/36 , H03K19/173
CPC分类号： G09G3/3677 , G09G3/3648 , G09G3/3688 , G09G2310/027 , G11C19/28 , H03K23/50
摘要： A shift register includes a first transistor connected between an output terminal and a first clock terminal, a second transistor connected between the output terminal and a first power terminal, and an inverter in which a first node to which the gate of the first transistor is connected serves as an input node and a second node to which the gate of the second transistor is connected serves as an output node. The inverter has third and fourth transistors connected in series between the second node and a first power terminal, both having their gates connected to the first node, a fifth transistor connected between the second node and a third power terminal having its gate connected to the third power terminal, and a sixth transistor connected between a fourth power terminal and a third node serving as a connection node between the third and fourth transistors. The sixth transistor has its gate connected to the second node.
摘要翻译：移位寄存器包括连接在输出端和第一时钟端之间的第一晶体管，连接在输出端和第一电源端之间的第二晶体管，以及反相器，其中第一晶体管的栅极连接到第一晶体管用作输入节点，并且第二晶体管的栅极连接到的第二节点用作输出节点。逆变器具有串联连接在第二节点和第一电源端子之间的第三和第四晶体管，它们的栅极连接到第一节点，第五晶体管连接在第二节点和第三电源端子之间，其栅极连接到第三节点的第三节点电源端子和连接在第四电源端子和第三节点之间的第六晶体管，用作第三和第四晶体管之间的连接节点。第六晶体管的栅极连接到第二节点。

9. 发明授权

US5706322A Precision time of day counter 失效
标题翻译：精确的日间计时器
公开(公告)号：US5706322A
公开(公告)日：1998-01-06
申请号：US439186
申请日：1995-05-11
申请人： Albert D. Scalo , Bruce F. Karaffa
发明人： Albert D. Scalo , Bruce F. Karaffa
IPC分类号： H03K23/00 , G04G3/02 , H03K21/16 , H03K23/40 , H03K23/50 , H03K21/40
CPC分类号： G04G3/02 , H03K21/16 , H03K23/50
摘要： A very high speed counter system of operating at frequencies of up to around 800 MHz provides timing measurements with accuracies on the order of (1/f) seconds where f is the frequency of operation. The least significant bit of the counter operates at the given frequency of a first clock signal while the other higher order bits operate at a second clock signal where the second clock signal is one-half the frequency of the first clock signal and is inverted. Carry lookahead circuits connected between stages of the second counter operate in conjunction with the clocking scheme to produce a high speed and accurate counter.
摘要翻译：以高达800MHz的频率工作的非常高速的计数器系统提供了时间测量，精度在（1 / f）秒的数量级，其中f是工作频率。计数器的最低有效位以第一时钟信号的给定频率工作，而另一较高位在第二时钟信号下工作，其中第二时钟信号是第一时钟信号的频率的二分之一并被反相。连接在第二计数器的级之间的进位先行电路与时钟方案一起操作以产生高速和精确的计数器。

10. 发明授权

US5559844A Binary counter with sped-up ripple carry 失效
标题翻译：带加速波纹的二进制计数器
公开(公告)号：US5559844A
公开(公告)日：1996-09-24
申请号：US337503
申请日：1994-11-08
申请人： Si-Yeol Lee
发明人： Si-Yeol Lee
IPC分类号： H03K23/40 , G11C8/04 , G11C11/408 , H03K23/50 , H03K21/00
CPC分类号： H03K23/50
摘要： A binary counter or binary-coded-arithmetic counter uses local look-ahead to speed up ripple carry propagation. A succession of counter stages therein can be identified by respective consecutive ordinal numbers assigned in accordance with the order of carry propagation. Each counter stage receives a respective carry input and supplies a respective output signal, and each counter stage identified by even number supplies a respective complemented output signal. Each counter stage identified by odd number has a respective carry generation circuit for supplying a respective carry output signal which includes a NAND gate responsive to carry input to that counter stage and responsive to output signal from that counter stage, carry input for the next counter stage being supplied in response to the NAND gate response. Each counter stage identified by even number has a respective carry generation circuit for supplying a respective carry output signal which includes a NOR gate responsive to the NAND gate response used for determining carry input for that counter stage and responsive to complemented output signal from that counter stage, carry input for the next counter stage being supplied in response to said NOR gate response.
摘要翻译：二进制计数器或二进制编码算术计数器使用本地预先加速纹波进位传播。可以通过按照进位传播的顺序分配的相应的连续序号来识别其中的一系列计数器级。每个计数器级接收相应的进位输入并提供相应的输出信号，并且由偶数标识的每个计数器级提供相应的补码输出信号。由奇数标识的每个计数器级具有各自的进位产生电路，用于提供包括与非门的各个进位输出信号，所述NAND门响应于对该计数器级的输入进行响应，并且响应来自该计数器级的输出信号，进行下一个计数器级的输入响应于NAND门响应而被提供。由偶数标识的每个计数器级具有相应的进位产生电路，用于响应于用于确定该计数器级的进位输入的NAND门响应提供包括NOR门的相应进位输出信号，并且响应来自该计数器级的补码输出信号响应于所述或非门响应而提供下一个计数级的输入。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式