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11. 发明授权

US07679952B2 Electronic circuit with a memory matrix 有权
标题翻译：具有记忆矩阵的电子电路
公开(公告)号：US07679952B2
公开(公告)日：2010-03-16
申请号：US12096226
申请日：2006-12-04
申请人： Nicolaas Lambert , Victor Martinus Gerardus Van Acht , Pierre Hermanus Woerlee , Andrei Mijiritskii
发明人： Nicolaas Lambert , Victor Martinus Gerardus Van Acht , Pierre Hermanus Woerlee , Andrei Mijiritskii
IPC分类号： G11C16/02 , H01L27/105
CPC分类号： G11C13/003 , G11C13/0004 , G11C17/16 , G11C2213/78 , G11C2213/79 , H01L27/101 , H01L27/2454 , H01L27/2472
摘要： In an example embodiment, an electronic circuit comprises a memory matrix with rows and columns of memory cells. First row conductors are provided for each of the rows. Second row conductors correspond to pairs of rows, each successive row forming a respective pair with a preceding one of the rows, so that each pair overlaps with one row of the next pair. Column conductors are provided for each of the columns. Each of the memory cells comprises an access transistor, a node and a first and a second resistive memory element. The access transistor has a control electrode coupled to the first row conductor of the row of the memory cell, a main current channel coupled between the column conductor for the column of the memory cell and the node. The first and second the resistive memory element are coupled between the node and the second row conductors for the pairs of rows to which the memory cell belongs.
摘要翻译：在示例实施例中，电子电路包括具有存储器单元的行和列的存储器矩阵。为每行提供第一行导体。第二行导体对应于行对，每个连续的行与前面的行之一形成相应的对，使得每一对与下一对的一行重叠。为每个列提供列导体。每个存储单元包括存取晶体管，节点和第一和第二电阻存储器元件。存取晶体管具有耦合到存储单元行的第一行导体的控制电极，耦合在存储单元的列的列导体和节点之间的主电流通道。第一和第二电阻性存储器元件耦合在该存储器单元所属的行对之间的节点和第二行导体之间。

12. 发明申请

US20080258770A1 Single Threshold and Single Conductivity Type Logic 有权
标题翻译：单阈值和单电导型逻辑
公开(公告)号：US20080258770A1
公开(公告)日：2008-10-23
申请号：US12067075
申请日：2006-09-14
申请人： Victor Martinus Gerardus Van Acht , Nicolaas Lambert , Andrei Mijiritskii , Pierre Hermanus Woerlee
发明人： Victor Martinus Gerardus Van Acht , Nicolaas Lambert , Andrei Mijiritskii , Pierre Hermanus Woerlee
IPC分类号： H03K19/094
CPC分类号： H03K19/017 , H03K19/096
摘要： A logic assembly (400) is composed from circuit elements of a single threshold and single conductivity type and comprises a logic circuitry (410) having at least a set of switches each having a main current path and a control terminal. The main current path forms a series arrangement having first and second conducting terminals coupled to power supply lines. The main current pathes being coupled to a common node that forms an output of logic assembly (400). The control terminals of said switches being coupled to clock circuitry for providing mutually non-overlapping clock signals to said control terminal. The logic assembly further comprises an output boosting circuit (420) for boosting the output of said logic assembly (400) including a capacitive means (421) for enabling supply of additional charge to the output of said logic assembly (400). It further includes a bootstrapping circuit (422) for enabling an additional supply of charge to a first end of said capacitive means, resulting in a boosted voltage at a second end of said capacitive means.
摘要翻译：逻辑组件（400）由单个阈值和单导电类型的电路元件组成，并且包括具有至少一组开关的逻辑电路（410），每组开关各自具有主电流路径和控制端子。主电流路径形成具有耦合到电源线的第一和第二导电端子的串联装置。主要的当前裸片耦合到形成逻辑组件（400）的输出的公共节点。所述开关的控制端耦合到时钟电路，用于向所述控制端提供相互不重叠的时钟信号。逻辑组件还包括用于升压所述逻辑组件（400）的输出的输出升压电路（420），包括用于使能向所述逻辑组件（400）的输出提供附加电荷的电容装置（421）。它还包括一个自举电路（422），用于使得能够向所述电容性装置的第一端额外提供电荷，导致在所述电容装置的第二端处的升压电压。

13. 发明申请

US20110313327A1 METHOD FOR AUTOMATIC ALIGNMENT OF A POSITION AND ORIENTATION INDICATOR AND DEVICE FOR MONITORING THE MOVEMENTS OF A BODY PART 审中-公开
标题翻译：自动对准位置和方向指示器的方法和用于监测身体部位运动的装置
公开(公告)号：US20110313327A1
公开(公告)日：2011-12-22
申请号：US13142447
申请日：2010-01-12
申请人： Victor Martinus Gerardus Van Acht , Nicolaas Lambert
发明人： Victor Martinus Gerardus Van Acht , Nicolaas Lambert
IPC分类号： A61B5/11
摘要： A method for automatic alignment of a position and orientation indicator with respect to a body part is provided. The method comprises the steps: attaching a position and orientation indicator (2, 4) to a body part (3, 5); moving the body part and measuring movements of the position and orientation indicator; and exploiting physical constraints to motion to determine the alignment of the position and orientation indicator with respect to the body part.
摘要翻译：提供了一种用于相对于身体部位自动对准位置和姿态指示器的方法。该方法包括以下步骤：将位置和方向指示器（2,4）附接到主体部分（3,5）上; 移动身体部位并测量位置和姿势指示器的运动; 并利用物理约束来运动以确定位置和姿态指示器相对于身体部分的对准。

14. 发明申请

US20100250177A1 ORIENTATION MEASUREMENT OF AN OBJECT 审中-公开
标题翻译：对象的方位测量
公开(公告)号：US20100250177A1
公开(公告)日：2010-09-30
申请号：US12742108
申请日：2008-11-11
申请人： Victor Martinus Gerardus Van Acht , Nicolaas Lambert
发明人： Victor Martinus Gerardus Van Acht , Nicolaas Lambert
IPC分类号： G06F19/00
CPC分类号： G01C21/165 , G01C25/005
摘要： There is provided an object orientation measurement system for improving the accuracy of a first estimate of the orientation of an object to which the system is attached, the system comprising an accelerometer for measuring a first acceleration of the object; and an estimation unit for providing a position or velocity of the object; processing means for comparing the first acceleration and output of the estimation unit to form a correction signal, and for applying the correction signal to the first estimate of the orientation of the object to produce a second estimate of the orientation of the object.
摘要翻译：提供了一种用于提高系统所附接的物体的取向的第一估计精度的物体朝向测量系统，该系统包括用于测量物体的第一加速度的加速度计; 以及估计单元，用于提供所述物体的位置或速度; 处理装置，用于比较估计单元的第一加速度和输出以形成校正信号，并且用于将校正信号应用于对象的取向的第一估计，以产生对象的取向的第二估计。

15. 发明授权

US10821047B2 Method for automatic alignment of a position and orientation indicator and device for monitoring the movements of a body part 有权
公开(公告)号：US10821047B2
公开(公告)日：2020-11-03
申请号：US13142447
申请日：2010-01-12
申请人： Victor Martinus Gerardus Van Acht , Nicolaas Lambert
发明人： Victor Martinus Gerardus Van Acht , Nicolaas Lambert
IPC分类号： A61B5/11 , A61H1/02 , A61B5/00 , G06F19/00 , G16H40/40
摘要： A method for automatic alignment of a position and orientation indicator with respect to a body part is provided. The method includes the acts of attaching a position and orientation indicator to a body part; moving the body part and measuring movements of the position and orientation indicator; and exploiting physical constraints to motion to determine the alignment of the position and orientation indicator with respect to the body part.

16. 发明申请

US20100169546A1 FLASH MEMORY ACCESS CIRCUIT 审中-公开
标题翻译：闪存存取电路
公开(公告)号：US20100169546A1
公开(公告)日：2010-07-01
申请号：US12377675
申请日：2007-08-13
申请人： Victor Martinus Gerardus Van Acht , Nicolaas Lambert
发明人： Victor Martinus Gerardus Van Acht , Nicolaas Lambert
IPC分类号： G06F12/00 , G06F12/02 , G06F13/28 , G06F13/24
CPC分类号： G06F9/4812
摘要： A system comprises an instruction processor (10), a flash memory device (14a), a flash control circuit (14) and a working memory (16). Instructions of an interrupt program are kept stored in the flash memory device (14a). When the instruction processor (10) receives an interrupt signal, the instruction processor (10) executes loading instructions, to cause the flash control circuit (14) to load said instructions of the interrupt program from the flash memory device (14a) into the working memory (16). The instructions of the interrupt program are subsequently executed with the instruction processor (10) from the working memory (16). Preferably it is tested whether a copy of said instructions of the interrupt program is stored in the working memory (16) at the time of the interrupt. If the copy is found stored, execution of said instructions from the copy is started before completing execution of of access instructions that were in progress at the time of the interrupt. If the copy is not found stored, execution of the access instructions is first completed and subsequently the instruction processor (10) executes the loading instructions, followed by execution of the instructions of the copy of interrupt program from the working memory (16).
摘要翻译：系统包括指令处理器（10），闪存设备（14a），闪存控制电路（14）和工作存储器（16）。中断程序的指令被保存在闪速存储器件（14a）中。当指令处理器（10）接收到中断信号时，指令处理器（10）执行加载指令，使闪存控制电路（14）将来自闪存设备（14a）的中断程序指令加载到工作记忆（16）。随后使用来自工作存储器（16）的指令处理器（10）执行中断程序的指令。优选地，在中断时测试中断程序的所述指令的副本是否存储在工作存储器（16）中。如果找到存储的副本，则在中断之前完成正在进行的访问指令的执行之前，开始从副本执行所述指令。如果没有存储副本，则首先完成访问指令的执行，随后指令处理器（10）执行加载指令，随后从工作存储器（16）执行中断程序副本的指令。

17. 发明申请

US20080316805A1 Electronic Circuit With a Memory Matrix 有权
标题翻译：具有存储矩阵的电子电路
公开(公告)号：US20080316805A1
公开(公告)日：2008-12-25
申请号：US12096226
申请日：2006-12-04
申请人： Nicolaas Lambert , Victor Martinus Gerardus Van Acht , Pierre Hermanus Woerlee , Andrei Mijiritskii
发明人： Nicolaas Lambert , Victor Martinus Gerardus Van Acht , Pierre Hermanus Woerlee , Andrei Mijiritskii
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/003 , G11C13/0004 , G11C17/16 , G11C2213/78 , G11C2213/79 , H01L27/101 , H01L27/2454 , H01L27/2472
摘要： An electronic circuit comprises a memory matrix (60) with rows and columns of memory cells (16). First row conductors (10, 12) are provided for each of the rows. Second row conductors (12) are provided for successively overlapping pairs of adjacent rows. Column conductors (14) are provided for each of the columns. Each of the memory cells (16) comprises an access transistor (160), a node (166) and a first and second resistive memory element (162, 164). The access transistor (160) is preferably a vertical transistor having a control electrode coupled to the first row conductor (10) of the row of the memory cell (16), a main current channel coupled between the column conductor (14) for the column of the memory cell (160) and the node (166). The first and second resistive memory element (162, 164) are coupled between the node (166) and the second row conductors (12) for the pairs of rows to which the memory cell belongs.
摘要翻译：电子电路包括具有存储单元（16）的行和列的存储矩阵（60）。为每行设置第一行导体（10,12）。提供第二行导体（12）用于连续重叠相邻行对。为每个列提供列导体（14）。每个存储器单元（16）包括存取晶体管（160），节点（166）和第一和第二电阻性存储元件（162,164）。存取晶体管（160）优选地是具有耦合到存储单元（16）的行的第一行导体（10）的控制电极的垂直晶体管，耦合在用于列的列导体（14）之间的主电流通道的存储单元（160）和节点（166）。第一和第二电阻性存储器元件（162,164）耦合在存储器单元所属的行对之间的节点（166）和第二行导体（12）之间。

18. 发明授权

US07834668B2 Single threshold and single conductivity type amplifier/buffer 有权
标题翻译：单阈值和单导电型放大器/缓冲器
公开(公告)号：US07834668B2
公开(公告)日：2010-11-16
申请号：US12088735
申请日：2006-10-04
申请人： Victor Martinus Gerardus Van Acht , Nicolaas Lambert , Andrei Mijiritskii , Pierre Hermanus Woerlee
发明人： Victor Martinus Gerardus Van Acht , Nicolaas Lambert , Andrei Mijiritskii , Pierre Hermanus Woerlee
IPC分类号： H03B1/00
CPC分类号： H03K19/01721 , H03K19/09441
摘要： An amplifier/buffer composed from circuit elements of a single threshold and single conductivity type, comprising an input stage for receiving one or more inputs for buffering/amplification and providing an intermediate to control output of the amplifier/buffer. The intermediate signal is provided to a boosting circuit configured to boosts said signal when said signal has exceeded a predetermined value. The amplifier/buffer further has an output stage for receiving at least said signal and providing an amplified/buffered output.
摘要翻译：由单阈值和单导电类型的电路元件组成的放大器/缓冲器，包括用于接收用于缓冲/放大的一个或多个输入的输入级，并且提供中间级以控制放大器/缓冲器的输出。中间信号被提供给升压电路，该升压电路被配置为当所述信号超过预定值时升高所述信号。放大器/缓冲器还具有用于至少接收所述信号并提供放大/缓冲输出的输出级。

19. 发明授权

US07671660B2 Single threshold and single conductivity type logic 有权
标题翻译：单阈值和单导电类型逻辑
公开(公告)号：US07671660B2
公开(公告)日：2010-03-02
申请号：US12067075
申请日：2006-09-14
申请人： Victor Martinus Gerardus Van Acht , Nicolaas Lambert , Andrei Mijiritskii , Pierre Hermanus Woerlee
发明人： Victor Martinus Gerardus Van Acht , Nicolaas Lambert , Andrei Mijiritskii , Pierre Hermanus Woerlee
IPC分类号： H03K17/16
CPC分类号： H03K19/017 , H03K19/096
摘要： A logic assembly (400) is composed from circuit elements of a single threshold and single conductivity type and comprises a logic circuitry (410) having at least a set of switches each having a main current path and a control terminal. The main current path forms a series arrangement having first and second conducting terminals coupled to power supply lines. The main current paths being coupled to a common node that forms an output of logic assembly (400). The control terminals of said switches being coupled to clock circuitry for providing mutually non-overlapping clock signals to said control terminal. The logic assembly further comprises an output boosting circuit (420) for boosting the output of said logic assembly (400) including a capacitive means (421) for enabling supply of additional charge to the output of said logic assembly (400). It further includes a bootstrapping circuit (422) for enabling an additional supply of charge to a first end of said capacitive means, resulting in a boosted voltage at a second end of said capacitive means.
摘要翻译：逻辑组件（400）由单个阈值和单导电类型的电路元件组成，并且包括具有至少一组开关的逻辑电路（410），每组开关各自具有主电流路径和控制端子。主电流路径形成具有耦合到电源线的第一和第二导电端子的串联装置。主电流路径耦合到形成逻辑组件（400）的输出的公共节点。所述开关的控制端耦合到时钟电路，用于向所述控制端提供相互不重叠的时钟信号。逻辑组件还包括用于升压所述逻辑组件（400）的输出的输出升压电路（420），包括用于使能向所述逻辑组件（400）的输出提供附加电荷的电容装置（421）。它还包括一个自举电路（422），用于使得能够向所述电容性装置的第一端额外提供电荷，导致在所述电容装置的第二端处的升压电压。

20. 发明申请

US20080279025A1 Electronic Circuit with Memory for Which a Threshold Level is Selected 审中-公开
标题翻译：具有选择阈值电平的具有存储器的电子电路
公开(公告)号：US20080279025A1
公开(公告)日：2008-11-13
申请号：US11568003
申请日：2005-04-21
申请人： Victor Martinus Gerardus Van Acht , Albert W. Marsman , Boon Keat Chong , Nicolaas Lambert , Pierre Hermanus Woerlee , Teunis Jan Ikkink , Aalbert Stek , Hans Marc Bert Boeve , Gavin Nicholas Phillips
发明人： Victor Martinus Gerardus Van Acht , Albert W. Marsman , Boon Keat Chong , Nicolaas Lambert , Pierre Hermanus Woerlee , Teunis Jan Ikkink , Aalbert Stek , Hans Marc Bert Boeve , Gavin Nicholas Phillips
IPC分类号： G11C7/02 , H03M7/00
CPC分类号： G11C7/14 , G11C7/1006 , G11C2207/104 , G11C2207/2254 , G11C2211/5634
摘要： A memory (10) is organized as a matrix rows and columns of memory cell circuits (100) and comprises bit line conductors (12) coupled to rows of the memory cells (100). A sensing circuit (14) is coupled to the bit line conductors (12). The sensing circuit (14) is arranged to form respective data signals, each by comparing a respective signal from a plurality of the bit line conductors (12) with a reference level that is common for the bit line conductors (12). A reference level selection circuit (16) with inputs coupled to the plurality of bit line conductors (12) is arranged to control the reference level. The reference level selection circuit (16) selects the reference level dependent on respective analog signal levels on the plurality of the bit line conductors (12), so that analog signal levels from at least respective ones of the plurality of bit line conductors (12) lie on respective sides of the reference level.
摘要翻译：存储器（10）被组织为存储单元电路（100）的矩阵行和列，并且包括耦合到存储器单元（100）的行的位线导体（12）。感测电路（14）耦合到位线导体（12）。感测电路（14）被布置成通过将来自多个位线导体（12）的相应信号与位线导体（12）共用的基准电平进行比较来形成相应的数据信号。具有耦合到多个位线导体（12）的输入的参考电平选择电路（16）被布置成控制参考电平。参考电平选择电路（16）根据多个位线导体（12）上的相应模拟信号电平选择参考电平，使得来自多个位线导体（12）中的至少相应的模拟信号电平，位于参考水平的相应侧。

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