专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US06311234B1 Direct memory access controller with split channel transfer capability and FIFO buffering 有权
标题翻译：直接存储器访问控制器，具有分离的信道传输能力和FIFO缓冲
公开(公告)号：US06311234B1
公开(公告)日：2001-10-30
申请号：US09633998
申请日：2000-08-08
申请人： Natarajan Seshan , Jeffrey R. Quay , Kenneth L. Williams , Michael J. Moody
发明人： Natarajan Seshan , Jeffrey R. Quay , Kenneth L. Williams , Michael J. Moody
IPC分类号： G06F1328
CPC分类号： G06F9/3001 , G06F9/30098 , G06F15/7832
摘要： A microprocessor 1 is described which includes a direct memory access (DMA) circuitry 143. DMA 143 is interconnected with a program memory 23 and a data memory 22 and is operational to transfer data to or from these memories. DMA 143 is interconnected with a peripheral bus 110 and thereby to various peripherals internal to microprocessor 1. DMA 143 is also interconnected with an external memory interface 103 and thereby to various external memory circuits and peripherals external to microprocessor 1. An auxiliary channel control circuitry 160 provides DMA transfers by interacting with a peripheral such as host port 150 which has its own address generation circuitry. DMA 143 provides frame synchronization for triggering a frame transfer, or group of transfers. DMA 143 is auto-initialized through registers. DMA action complete pins DMAC0-3 indicate DMA status to external devices. DMA 143 allows for local variability of transfer rates in a split channel mode of operation by allowing a transmit channel to get ahead of a corresponding receive channel by a preselected number of data words.
摘要翻译：描述了包括直接存储器访问（DMA）电路143的微处理器1.DMA 143与程序存储器23和数据存储器22互连，并且可操作以将数据传送到这些存储器或从这些存储器传送数据。 DMA 143与外围总线110互连，从而与微处理器1内部的各种外围设备互连.DMA 143也与外部存储器接口103互连，从而连接到微处理器1外部的各种外部存储器电路和外围设备。辅助通道控制电路160 通过与诸如具有其自己的地址产生电路的主机端口150的外围设备交互来提供DMA传输。 DMA 143提供用于触发帧传送或传送组的帧同步。 DMA 143通过寄存器自动初始化。 DMA操作完成引脚DMAC0-3指示外部设备的DMA状态。 DMA 143允许通过允许发送信道通过预选数量的数据字而在对应的接收信道之前的分离信道操作模式中的传输速率的局部变化。

12. 发明授权

US6145027A DMA controller with split channel transfer capability and FIFO buffering allowing transmit channel to get ahead of corresponding receive channel by preselected number of elements 失效
标题翻译：具有分离信道传输能力的DMA控制器和FIFO缓冲，允许发射信道通过预先选择的元素数量超前于相应的接收信道
公开(公告)号：US6145027A
公开(公告)日：2000-11-07
申请号：US54833
申请日：1998-04-03
申请人： Natarajan Seshan , Jeffrey R. Quay , Kenneth L. Williams , Michael J. Moody
发明人： Natarajan Seshan , Jeffrey R. Quay , Kenneth L. Williams , Michael J. Moody
IPC分类号： G06F9/30 , G06F9/302 , G06F15/78 , G06F3/00 , G06F13/00 , G06F13/14 , G06F13/28
CPC分类号： G06F9/3001 , G06F15/7832 , G06F9/30098
摘要： A microprocessor 1 is described which includes a direct memory access (DMA) circuitry 143. DMA 143 is interconnected with a program memory 23 and a data memory 22 and is operational to transfer data to or from these memories. DMA 143 is interconnected with a peripheral bus 110 and thereby to various peripherals internal to microprocessor 1. DMA 143 is also interconnected with an external memory interface 103 and thereby to various external memory circuits and peripherals external to microprocessor 1. An auxiliary channel control circuitry 160 provides DMA transfers by interacting with a peripheral such as host port 150 which has its own address generation circuitry. DMA 143 provides frame synchronization for triggering a frame transfer, or group of transfers. DMA 143 is auto-initialized through registers. DMA action complete pins DMAC0-3 indicate DMA status to external devices. DMA 143 allows for local variability of transfer rates in a split channel mode of operation by allowing a transmit channel to get ahead of a corresponding receive channel by a preselected number of data words.
摘要翻译：描述了包括直接存储器访问（DMA）电路143的微处理器1.DMA 143与程序存储器23和数据存储器22互连，并且可操作以将数据传送到这些存储器或从这些存储器传送数据。 DMA 143与外围总线110互连，从而与微处理器1内部的各种外围设备互连.DMA 143也与外部存储器接口103互连，从而连接到微处理器1外部的各种外部存储器电路和外围设备。辅助通道控制电路160 通过与诸如具有其自己的地址产生电路的主机端口150的外围设备交互来提供DMA传输。 DMA 143提供用于触发帧传送或传送组的帧同步。 DMA 143通过寄存器自动初始化。 DMA操作完成引脚DMAC0-3指示外部设备的DMA状态。 DMA 143允许通过允许发送信道通过预选数量的数据字而在对应的接收信道之前的分离信道操作模式中的传输速率的局部变化。

13. 发明申请

US20050086400A1 FIFO interface for flag-initiated DMA frame synchro-burst operation 有权
标题翻译：用于标志发起的DMA帧同步突发操作的FIFO接口
公开(公告)号：US20050086400A1
公开(公告)日：2005-04-21
申请号：US10690119
申请日：2003-10-21
申请人： Clayton Gibbs , Kyle Castille , Natarajan Seshan
发明人： Clayton Gibbs , Kyle Castille , Natarajan Seshan
IPC分类号： G06F5/06 , G06F5/12 , G06F13/28
CPC分类号： G06F13/28 , G06F5/065 , G06F5/12 , G06F2205/126
摘要： The invention describes a modification of FIFO hardware to allow improved use of FIFOs for burst reading from or writing to a processor direct memory access unit via either an expansion bus or an external memory interface using FIFO flag initiated bursts. The hardware and FIFO signal modifications make the FIFO-DMA interface immune to deadlock conditions and generation of spurious interrupt events in the process of initiating burst transfers. The FIFO function is modified to synchronize the frame transfer on the digital signal processor even if the digital signal processor lacks this functionality. By delaying the programmable flag assertions within the FIFO until after the current burst is complete the DSP-FIFO interface may be made immune to deadlock conditions and generation of spurious events.
摘要翻译：本发明描述了FIFO硬件的修改，以便通过使用FIFO标志发起的脉冲串的扩展总线或外部存储器接口来改进对FIFO进行突发读取或从处理器直接存储器访问单元的写入。硬件和FIFO信号修改使得FIFO-DMA接口在发起突发传输的过程中免于死锁条件和产生假中断事件。即使数字信号处理器缺乏此功能，FIFO功能也被修改为使数字信号处理器上的帧传输同步。通过延迟FIFO内的可编程标志声明，直到当前突发完成，DSP-FIFO接口可以免受死锁条件的影响，并产生杂散事件。

14. 发明授权

US06374346B1 Processor with conditional execution of every instruction 失效
标题翻译：处理器有条件执行每个指令
公开(公告)号：US06374346B1
公开(公告)日：2002-04-16
申请号：US09012326
申请日：1998-01-23
申请人： Natarajan Seshan , Laurence R. Simar, Jr. , Reid E. Tatge , Alan L. Davis
发明人： Natarajan Seshan , Laurence R. Simar, Jr. , Reid E. Tatge , Alan L. Davis
IPC分类号： G06F9302
CPC分类号： G06F9/30094 , G06F9/30101 , G06F9/3842
摘要： A general purpose microprocessor architecture enabling more efficient computations of a type in which Boolean operations and arithmetic operations conditioned on the results of the Boolean operations are interleaved. The microprocessor is provided with a plurality of general purpose registers (“GPRs” 102)and an arithmetic logic unit (“ALU” 104), capable of performing arithmetic operations and Boolean operations. The ALU has a first input (108) and a second input (110), and an output (112), the first and second inputs receiving values stored in the GPRs. The output stores the results of the arithmetic logic unit operations in the GPRs. At least one of the GPRs is capable of receiving directly from the ALU a result of a Boolean operation. In one embodiment, at least one of the GPRs (PN)capable of receiving directly from the ALU a result of a Boolean operation is configured so as to cause the conditioning of an arithmetic operation of the ALU based on the value stored in the GPR.
摘要翻译：一种通用的微处理器架构，能够更有效地计算一种类型，其中布尔运算和运算布置运算结果的算术运算被交错。微处理器具有能够执行算术运算和布尔运算的多个通用寄存器（“GPR”102）和算术逻辑单元（“ALU”104）“。 ALU具有第一输入（108）和第二输入（110）以及输出（112），第一和第二输入接收存储在GPR中的值。输出将算术逻辑单元操作的结果存储在GPR中。至少有一个GPR能够直接从ALU接收布尔运算的结果。在一个实施例中，能够直接从ALU接收到布尔运算结果的至少一个GPR（PN）被配置成基于存储在GPR中的值来调节ALU的算术运算。

15. 发明授权

US06182203B2 Microprocessor 失效
标题翻译：微处理器
公开(公告)号：US06182203B2
公开(公告)日：2001-01-30
申请号：US09012813
申请日：1998-01-23
申请人： Laurence R. Simar, Jr. , Richard H. Scales , Natarajan Seshan
发明人： Laurence R. Simar, Jr. , Richard H. Scales , Natarajan Seshan
IPC分类号： G06F938
CPC分类号： G06F9/3891 , G06F9/30036 , G06F9/30072 , G06F9/30112 , G06F9/3012 , G06F9/30145 , G06F9/30167 , G06F9/3552 , G06F9/3824 , G06F9/3828 , G06F9/3853 , G06F9/3885 , G06F15/7857
摘要： A microprocessor, comprising a first set of functional units capable of performing parallel data operations, a second set of functional units capable of performing parallel data operations, and a data interconnection path connecting the first and second functional units.
摘要翻译：一种微处理器，包括能够执行并行数据操作的第一组功能单元，能够执行并行数据操作的第二组功能单元，以及连接第一和第二功能单元的数据互连路径。

16. 发明授权

US06112298A Method for managing an instruction execution pipeline during debugging of a data processing system 失效
标题翻译：在数据处理系统调试期间管理指令执行流水线的方法
公开(公告)号：US06112298A
公开(公告)日：2000-08-29
申请号：US974742
申请日：1997-11-19
申请人： Douglas E. Deao , Natarajan Seshan
发明人： Douglas E. Deao , Natarajan Seshan
IPC分类号： G06F9/38 , G06F11/22 , G06F11/28 , G06F11/36 , G06F11/00
CPC分类号： G06F11/3648 , G06F11/3636
摘要： A data processing system on an integrated circuit 42 with microprocessor 1 and peripheral devices 60-61 is provided with an emulation unit 50 which allows debugging and emulation of integrated circuit 42 when connected to an external test system 51. Microprocessor 1 has in instruction execution pipeline which has several execution phases which involve fetch/decode units 10a-c and functional execution units 12, 14, 16 and 18. The pipeline of microprocessor 1 is unprotected so that memory access latency to data memory 22 and register file 20 can be utilized by system program code which is stored in instruction memory 23. Emulation unit 50 provides means for emulating the unprotected pipeline of microprocessor 1 and for rapidly uploading and downloading memories 22-23. Emulation unit 50 operates in a manner to prevent extraneous operations from occurring which could otherwise affect memories 22-23 or peripheral devices 60-61 during emulation.
摘要翻译：具有微处理器1和外围设备60-61的集成电路42上的数据处理系统设置有仿真单元50，其在连接到外部测试系统51时允许集成电路42的调试和仿真。微处理器1在指令执行管线其具有涉及获取/解码单元10a-c和功能执行单元12,14,16和18的多个执行阶段。微处理器1的流水线是不受保护的，从而可以利用数据存储器22和寄存器文件20的存储器访问等待时间存储在指令存储器23中的系统程序代码。仿真单元50提供用于模拟微处理器1的未受保护流水线并用于快速上载和下载存储器22-23的装置。仿真单元50以防止在仿真期间可能影响存储器22-23或外围设备60-61的外来操作的方式操作。

17. 发明授权

US6058474A Method and apparatus for DMA boot loading a microprocessor without an internal ROM 失效
标题翻译：用于DMA引导的方法和装置装载没有内部ROM的微处理器
公开(公告)号：US6058474A
公开(公告)日：2000-05-02
申请号：US12332
申请日：1998-01-23
申请人： Philip K. Baltz , Natarajan Seshan , Ron A. Shipp
发明人： Philip K. Baltz , Natarajan Seshan , Ron A. Shipp
IPC分类号： G06F9/445
CPC分类号： G06F9/4401
摘要： A microprocessor 10 has an internal program memory 23 and direct memory access (DMA) circuitry 100. Microprocessor 10 also has provisions for connecting to an external source of data via an external bus 73. Configuration circuitry 74 or 81 provides configuration parameters to DMA 100 when a reset signal 76 is deasserted. DMA 100 boot loads microprocessor 10 by transferring a block of data which contains an initial program from an external source to internal program memory after reset signal 76 is deasserted. At the completion of the boot load, microprocessor begins execution of the initial program.
摘要翻译：微处理器10具有内部程序存储器23和直接存储器访问（DMA）电路100.微处理器10还具有用于经由外部总线73连接到外部数据源的设备。配置电路74或81向DMA 100提供配置参数，当DMA 复位信号76被断言。 DMA 100引导通过在复位信号76被置为无效之后，将包含初始程序的数据块从外部源传送到内部程序存储器来加载微处理器10。在引导加载完成后，微处理器开始执行初始程序。

18. 发明授权

US5958044A Multicycle NOP 失效
标题翻译：多周期NOP
公开(公告)号：US5958044A
公开(公告)日：1999-09-28
申请号：US8909
申请日：1998-01-20
申请人： Richard A. Brown , Ray Simar , Natarajan Seshan
发明人： Richard A. Brown , Ray Simar , Natarajan Seshan
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38 , G06F9/28
CPC分类号： G06F9/30079 , G06F9/325 , G06F9/3836 , G06F9/3838 , G06F9/3869 , G06F9/3885
摘要： A method for controlling the execution of a microprocessor to cause it to execute a NOP instruction for a programmable number of sequential cycles. A NOP instruction is provided, that includes a predetermined OP code field identifying the NOP instruction as a programmably multiple NOP instruction. A predetermined count field is provided, representing the number of sequential cycles in which a NOP operation is to be performed by said microprocessor. The NOP instruction OP code field is read, as is the NOP instruction count field. In response thereto, a NOP operation is performed for the number of sequential cycles represented by said NOP instruction count field.
摘要翻译：一种用于控制微处理器的执行以使得其执行用于可编程数量的连续循环的NOP指令的方法。提供NOP指令，其包括将NOP指令识别为可编程多个NOP指令的预定OP代码字段。提供预定的计数字段，表示由微处理器执行NOP操作的连续周期数。读取NOP指令OP代码字段，NOP指令计数字段也被读取。响应于此，对由所述NOP指令计数字段表示的连续周期数进行NOP操作。

19. 发明申请

US20060259663A1 Direct memory access channel controller with quick channels, event queue and active channel memory protection 有权
公开(公告)号：US20060259663A1
公开(公告)日：2006-11-16
申请号：US11383045
申请日：2006-05-12
申请人： Roger Castille , Natarajan Seshan , Marco Lazar , Joseph Zbiciak
发明人： Roger Castille , Natarajan Seshan , Marco Lazar , Joseph Zbiciak
IPC分类号： G06F3/00
CPC分类号： G06F13/28
摘要： A data transfer control apparatus includes a channel controller and a transfer controller. The channel controller receives, prioritizes and queues event signals and predetermined memory writes which trigger data transfer requests controlling the transfer controller. The event queue stores event numbers mapped to parameter memory locations storing data transfer parameters. The mapping table and the parameter memory are writeable via a memory mapped write operation. Memory protection registers store data indicative of permitted data accesses to the memory map.

20. 发明申请

US20060259660A1 Data Transfer With Single Channel Controller Controlling Plural Transfer Controllers 有权
标题翻译：数据传输与单通道控制器控制多个传输控制器
公开(公告)号：US20060259660A1
公开(公告)日：2006-11-16
申请号：US11383063
申请日：2006-05-12
申请人： Roger Castille , Natarajan Seshan , Henry C. Nguyen , Marco Lazar , Jason Jones
发明人： Roger Castille , Natarajan Seshan , Henry C. Nguyen , Marco Lazar , Jason Jones
IPC分类号： G06F3/00
CPC分类号： G06F13/28
摘要： A data transfer control apparatus includes a channel controller and plural transfer controllers. The channel controller receives, prioritizes and queues data transfer requests. An event to transfer controller table enables recall of a transfer controller number corresponding to the data transfer request. The plural transfer controllers are independent and can operate simultaneously in parallel. Each transfer controller includes a read bus interface and a write bus interface which arbitrate with other bus masters in the case of blocking accesses directed to interfering devices or address ranges.
摘要翻译：数据传送控制装置包括信道控制器和多个传送控制器。信道控制器接收数据传输请求的优先次序和队列。传输控制器表的事件使得能够调用对应于数据传送请求的传送控制器号码。多个传送控制器是独立的并且可以同时并行操作。每个传送控制器包括一读读总线接口和一写写总线接口，在阻塞对干扰设备或地址范围的访问的情况下，与其它总线主机进行仲裁。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式