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1. 发明申请

US20060259568A1 Command re-ordering in hub interface unit based on priority 有权
标题翻译：基于优先级命令在集线器接口单元中重新排序
公开(公告)号：US20060259568A1
公开(公告)日：2006-11-16
申请号：US11128568
申请日：2005-05-13
申请人： Shoban Jagathesan , Sanjive Agarwala , Kyle Castille , Quang-Dieu An
发明人： Shoban Jagathesan , Sanjive Agarwala , Kyle Castille , Quang-Dieu An
IPC分类号： G06F15/167
CPC分类号： G06F13/28 , G06F13/385
摘要： Command reordering in the hub-interface unit (HIU) of Enhanced Direct Memory Access (EDMA) functions is described. Without command reordering in the EDMA, commands are issued by the HIU to the peripheral in order of issue. If the higher priority transfers are issued later by the EDMA, the previously issued lower priority transfers would block the higher priority transfers. Command reordering in the HIU causes transfers to be reordered and issued to the peripheral based on their priority. Reordering allows the EDMA and HIU is to give due service to high priority transfer requests with decreased weight placed on the order in which the requests were issued.
摘要翻译：描述了增强型直接存储器访问（EDMA）功能的集线器接口单元（HIU）中的命令重新排序。在EDMA中没有命令重新排序，命令由HIU按照问题的顺序发给外设。如果较高优先级的传输由EDMA稍后发出，则先前发布的较低优先级传输将阻止较高优先级的传输。 HIU中的命令重新排序使得根据它们的优先级重新排序并向外围设备发送传输。重新排序允许EDMA和HIU为优先权转移请求提供适当的服务，减少重量放在发出请求的顺序上。

2. 发明申请

US20050086400A1 FIFO interface for flag-initiated DMA frame synchro-burst operation 有权
标题翻译：用于标志发起的DMA帧同步突发操作的FIFO接口
公开(公告)号：US20050086400A1
公开(公告)日：2005-04-21
申请号：US10690119
申请日：2003-10-21
申请人： Clayton Gibbs , Kyle Castille , Natarajan Seshan
发明人： Clayton Gibbs , Kyle Castille , Natarajan Seshan
IPC分类号： G06F5/06 , G06F5/12 , G06F13/28
CPC分类号： G06F13/28 , G06F5/065 , G06F5/12 , G06F2205/126
摘要： The invention describes a modification of FIFO hardware to allow improved use of FIFOs for burst reading from or writing to a processor direct memory access unit via either an expansion bus or an external memory interface using FIFO flag initiated bursts. The hardware and FIFO signal modifications make the FIFO-DMA interface immune to deadlock conditions and generation of spurious interrupt events in the process of initiating burst transfers. The FIFO function is modified to synchronize the frame transfer on the digital signal processor even if the digital signal processor lacks this functionality. By delaying the programmable flag assertions within the FIFO until after the current burst is complete the DSP-FIFO interface may be made immune to deadlock conditions and generation of spurious events.
摘要翻译：本发明描述了FIFO硬件的修改，以便通过使用FIFO标志发起的脉冲串的扩展总线或外部存储器接口来改进对FIFO进行突发读取或从处理器直接存储器访问单元的写入。硬件和FIFO信号修改使得FIFO-DMA接口在发起突发传输的过程中免于死锁条件和产生假中断事件。即使数字信号处理器缺乏此功能，FIFO功能也被修改为使数字信号处理器上的帧传输同步。通过延迟FIFO内的可编程标志声明，直到当前突发完成，DSP-FIFO接口可以免受死锁条件的影响，并产生杂散事件。

3. 发明申请

US20060259665A1 Configurable multiple write-enhanced direct memory access unit 审中-公开
标题翻译：可配置多个写入增强型直接存储器存取单元
公开(公告)号：US20060259665A1
公开(公告)日：2006-11-16
申请号：US11128597
申请日：2005-05-13
申请人： Sanjive Agarwala , Kyle Castille , Quang An , David Bell , Natarajan Seshan
发明人： Sanjive Agarwala , Kyle Castille , Quang An , David Bell , Natarajan Seshan
IPC分类号： G06F13/38
CPC分类号： G06F13/28
摘要： The configurable multiple write-enhanced EDMA of this invention processes multiple priority channels and utilizes as much write data bus as practical. A write queue stores write requests with their corresponding data width and priority. A dispatch circuit dispatches a highest priority maximum data width write request if that is the highest priority stored write request or if the prior dispatch was not a maximum data width write request. The dispatch circuit dispatches two write requests if their total data width is less than or equal to the maximum data width and they both have a priority higher than the highest priority maximum data width write request.
摘要翻译：本发明的可配置多写增强型EDMA处理多个优先级信道并且尽可能多地使用写入数据总线。写队列存储具有相应数据宽度和优先级的写请求。调度电路调度最高优先级的最大数据宽度写请求，如果这是最高优先级存储的写请求，或者先前的调度不是最大数据宽度写请求。如果它们的总数据宽度小于或等于最大数据宽度并且它们都具有高于最高优先级最大数据宽度写入请求的优先级，则调度电路调度两个写入请求。

4. 发明申请

US20060256796A1 Independent source read and destination write enhanced DMA 有权
公开(公告)号：US20060256796A1
公开(公告)日：2006-11-16
申请号：US11128507
申请日：2005-05-13
申请人： Sanjive Agarwala , Kyle Castille , Quang-Dieu An , Hung Ong
发明人： Sanjive Agarwala , Kyle Castille , Quang-Dieu An , Hung Ong
IPC分类号： H04L12/28
CPC分类号： G06F13/28 , H04L49/90 , H04L49/901
摘要： The present invention provides for independent source-read and destination-write functionality for Enhanced Direct Memory Access (EDMA). Allowing source read and destination write pipelines to operate independently makes it possible for the source pipeline to issue multiple read requests and stay ahead of the destination write for fully pipelined operation. The result is that fully pipelined capability may be achieved and utilization of the full DMA bandwidth and maximum throughput performance are provided.

5. 发明授权

US07716388B2 Command re-ordering in hub interface unit based on priority 有权
标题翻译：基于优先级命令在集线器接口单元中重新排序
公开(公告)号：US07716388B2
公开(公告)日：2010-05-11
申请号：US11128568
申请日：2005-05-13
申请人： Shoban Srikrishna Jagathesan , Sanjive Agarwala , Kyle Castille , Quang-Dieu An
发明人： Shoban Srikrishna Jagathesan , Sanjive Agarwala , Kyle Castille , Quang-Dieu An
IPC分类号： G06F13/28 , G06F15/167
CPC分类号： G06F13/28 , G06F13/385
摘要： Command reordering in the hub interface unit (HIU) of Enhanced Direct Memory Access (EDMA) functions is described. Without command reordering in the EDMA, commands are issued by the HIU to the peripheral in order of issue. If the higher priority transfers are issued later by the EDMA, the previously issued lower priority transfers would block the higher priority transfers. Command reordering in the HIU causes transfers to be reordered and issued to the peripheral based on their priority. Reordering allows the EDMA and HIU to give due service to high priority transfer requests with decreased weight placed on the order in which the requests were issued.
摘要翻译：描述了增强型直接存储器访问（EDMA）功能的集线器接口单元（HIU）中的命令重新排序。在EDMA中没有命令重新排序，命令由HIU按照问题的顺序发给外设。如果较高优先级的传输由EDMA稍后发出，则先前发布的较低优先级传输将阻止较高优先级的传输。 HIU中的命令重新排序使得根据它们的优先级重新排序并向外围设备发送传输。重新排序允许EDMA和HIU为优先权转移请求提供适当的服务，减少重量发放在请求的顺序上。

6. 发明授权

US09075743B2 Managing bandwidth allocation in a processing node using distributed arbitration 有权
标题翻译：使用分布式仲裁管理处理节点中的带宽分配
公开(公告)号：US09075743B2
公开(公告)日：2015-07-07
申请号：US13237749
申请日：2011-09-20
申请人： Raguram Damodaran , Abhijeet Ashok Chachad , Dheera Balasubramanian , Roger Kyle Castille , David Quintin Bell
发明人： Raguram Damodaran , Abhijeet Ashok Chachad , Dheera Balasubramanian , Roger Kyle Castille , David Quintin Bell
IPC分类号： G06F13/16 , G06F11/10 , G06F7/483 , G06F9/30 , H03M13/35 , H03M13/29 , G06F13/18 , H03K19/00 , G06F1/32 , H03K21/00 , G06F12/02 , G06F13/364
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： Management of access to shared resources within a system comprising a plurality of requesters and a plurality of target resources is provided. A separate arbitration point is associated with each target resource. An access priority value is assigned to each requester. An arbitration contest is performed for access to a first target resource by requests from two or more of the requesters using a first arbitration point associated with the first target resource to determine a winning requester. The request from the winning requester is forwarded to a second target resource. A second arbitration contest is performed for access to the second target resource by the forwarded request from the winning requester and requests from one or more of the plurality of requesters using a second arbitration point associated with the second target resource.
摘要翻译：提供对包括多个请求者和多个目标资源的系统内对共享资源的访问的管理。单独的仲裁点与每个目标资源相关联。访问优先级值被分配给每个请求者。执行仲裁比赛，以通过使用与第一目标资源相关联的第一仲裁点的两个或多个请求者的请求来访问第一目标资源来确定获胜请求者。来自获胜请求者的请求被转发到第二目标资源。执行第二仲裁比赛，以通过来自获胜请求者的转发请求访问第二目标资源，以及使用与第二目标资源相关联的第二仲裁点的来自一个或多个请求者的请求。

7. 发明申请

US20120290756A1 Managing Bandwidth Allocation in a Processing Node Using Distributed Arbitration 有权
标题翻译：使用分布式仲裁管理处理节点中的带宽分配
公开(公告)号：US20120290756A1
公开(公告)日：2012-11-15
申请号：US13237749
申请日：2011-09-20
申请人： Raguram Damodaran , Abhijeet Ashok Chachad , Dheera Balasubramanian , Roger Kyle Castille , David Quintin Bell
发明人： Raguram Damodaran , Abhijeet Ashok Chachad , Dheera Balasubramanian , Roger Kyle Castille , David Quintin Bell
IPC分类号： G06F13/18
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： Management of access to shared resources within a system comprising a plurality of requesters and a plurality of target resources is provided. A separate arbitration point is associated with each target resource. An access priority value is assigned to each requester. An arbitration contest is performed for access to a first target resource by requests from two or more of the requesters using a first arbitration point associated with the first target resource to determine a winning requester. The request from the winning requester is forwarded to a second target resource. A second arbitration contest is performed for access to the second target resource by the forwarded request from the winning requester and requests from one or more of the plurality of requesters using a second arbitration point associated with the second target resource.
摘要翻译：提供对包括多个请求者和多个目标资源的系统内对共享资源的访问的管理。单独的仲裁点与每个目标资源相关联。访问优先级值被分配给每个请求者。执行仲裁比赛，以通过使用与第一目标资源相关联的第一仲裁点的两个或多个请求者的请求来访问第一目标资源来确定获胜请求者。来自获胜请求者的请求被转发到第二目标资源。执行第二仲裁比赛，以通过来自获胜请求者的转发请求访问第二目标资源，以及使用与第二目标资源相关联的第二仲裁点的来自一个或多个请求者的请求。

8. 发明申请

US20120198160A1 Efficient Cache Allocation by Optimizing Size and Order of Allocate Commands Based on Bytes Required by CPU 有权
标题翻译：通过优化基于CPU所需字节的分配命令的大小和顺序来实现高效缓存分配
公开(公告)号：US20120198160A1
公开(公告)日：2012-08-02
申请号：US13243411
申请日：2011-09-23
申请人： Abhijeet Ashok Chachad , Roger Kyle Castille , Joseph Raymond Michael Zbiciak , Dheera Balasubramanian
发明人： Abhijeet Ashok Chachad , Roger Kyle Castille , Joseph Raymond Michael Zbiciak , Dheera Balasubramanian
IPC分类号： G06F12/08
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： This invention is a data processing system having a multi-level cache system. The multi-level cache system includes at least first level cache and a second level cache. Upon a cache miss in both the at least one first level cache and the second level cache the data processing system evicts and allocates a cache line within the second level cache. The data processing system determine from the miss address whether the request falls within a low half or a high half of the allocated cache line. The data processing system first requests data from external memory of the miss half cache line. Upon receipt data is supplied to the at least one first level cache and the CPU. The data processing system then requests data from external memory for the other half of the second level cache line.
摘要翻译：本发明是一种具有多级缓存系统的数据处理系统。多级缓存系统至少包括第一级缓存和第二级高速缓存。在所述至少一个第一级高速缓存和所述第二级高速缓存中的高速缓存未命中时，所述数据处理系统在所述第二级高速缓存内驱逐并分配高速缓存行。数据处理系统从未命中地址确定请求是否落在所分配的高速缓存行的低一半或高一半内。数据处理系统首先从缺失半高速缓存行的外部存储器请求数据。当接收数据被提供给至少一个第一级高速缓存和CPU时。数据处理系统然后从第二级高速缓存行的另一半请求来自外部存储器的数据。

9. 发明授权

US07577774B2 Independent source read and destination write enhanced DMA 有权
标题翻译：独立的源读取和目标写入增强型DMA
公开(公告)号：US07577774B2
公开(公告)日：2009-08-18
申请号：US11128507
申请日：2005-05-13
申请人： Sanjive Agarwala , Kyle Castille , Quang-Dieu An , Hung Ong
发明人： Sanjive Agarwala , Kyle Castille , Quang-Dieu An , Hung Ong
IPC分类号： G06F13/28 , G06F13/00
CPC分类号： G06F13/28 , H04L49/90 , H04L49/901
摘要： The present invention provides for independent source-read and destination-write functionality for Enhanced Direct Memory Access (EDMA). Allowing source read and destination write pipelines to operate independently makes it possible for the source pipeline to issue multiple read requests and stay ahead of the destination write for fully pipelined operation. The result is that fully pipelined capability may be achieved and utilization of the full DMA bandwidth and maximum throughput performance are provided.
摘要翻译：本发明提供用于增强型直接存储器访问（EDMA）的独立的源读取和目的地写入功能。允许源读取和目标写入管道独立运行，使得源管道可以发出多个读取请求，并保持在目标写入之前完全流水线操作。结果是可以实现完全流水线的功能，并且提供了全DMA带宽和最大吞吐量性能的利用。

10. 发明申请

US20060259648A1 Concurrent read response acknowledge enhanced direct memory access unit 有权
标题翻译：并发读取响应确认增强的直接存储器存取单元
公开(公告)号：US20060259648A1
公开(公告)日：2006-11-16
申请号：US11128598
申请日：2005-05-13
申请人： Sanjive Agarwala , Kyle Castille , Quang-Dieu An
发明人： Sanjive Agarwala , Kyle Castille , Quang-Dieu An
IPC分类号： G06F3/00
CPC分类号： G06F13/28
摘要： An extended direct memory access (EDMA) operation issues a read command to the source port to request data. The port returns the data along with response information, which contains the channel and valid byte count. The EDMA stores the read data into a write buffer and acknowledges to the source port that the EDMA can accept more data. The read response and data can come from more than one port and belong to different channels. Removing channel prioritizing according to this invention allows the EDMA to store read data in the write buffer and the EDMA then can acknowledge the port read response concurrently across all channels. This improves the EDMA inbound and outbound data flow dramatically.
摘要翻译：扩展的直接存储器访问（EDMA）操作向源端口发出读取命令以请求数据。端口返回数据以及包含通道和有效字节计数的响应信息。 EDMA将读取的数据存储到写入缓冲区中，并向源端口确认EDMA可以接收更多的数据。读取响应和数据可以来自多个端口，属于不同的通道。根据本发明去除信道优先级允许EDMA将读数据存储在写缓冲器中，然后EDMA可以在所有信道上同时确认端口读取响应。这显着改善了EDMA入站和出站数据流。

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