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1. 发明申请

US20060259663A1 Direct memory access channel controller with quick channels, event queue and active channel memory protection 有权
公开(公告)号：US20060259663A1
公开(公告)日：2006-11-16
申请号：US11383045
申请日：2006-05-12
申请人： Roger Castille , Natarajan Seshan , Marco Lazar , Joseph Zbiciak
发明人： Roger Castille , Natarajan Seshan , Marco Lazar , Joseph Zbiciak
IPC分类号： G06F3/00
CPC分类号： G06F13/28
摘要： A data transfer control apparatus includes a channel controller and a transfer controller. The channel controller receives, prioritizes and queues event signals and predetermined memory writes which trigger data transfer requests controlling the transfer controller. The event queue stores event numbers mapped to parameter memory locations storing data transfer parameters. The mapping table and the parameter memory are writeable via a memory mapped write operation. Memory protection registers store data indicative of permitted data accesses to the memory map.

2. 发明申请

US20060259660A1 Data Transfer With Single Channel Controller Controlling Plural Transfer Controllers 有权
标题翻译：数据传输与单通道控制器控制多个传输控制器
公开(公告)号：US20060259660A1
公开(公告)日：2006-11-16
申请号：US11383063
申请日：2006-05-12
申请人： Roger Castille , Natarajan Seshan , Henry C. Nguyen , Marco Lazar , Jason Jones
发明人： Roger Castille , Natarajan Seshan , Henry C. Nguyen , Marco Lazar , Jason Jones
IPC分类号： G06F3/00
CPC分类号： G06F13/28
摘要： A data transfer control apparatus includes a channel controller and plural transfer controllers. The channel controller receives, prioritizes and queues data transfer requests. An event to transfer controller table enables recall of a transfer controller number corresponding to the data transfer request. The plural transfer controllers are independent and can operate simultaneously in parallel. Each transfer controller includes a read bus interface and a write bus interface which arbitrate with other bus masters in the case of blocking accesses directed to interfering devices or address ranges.
摘要翻译：数据传送控制装置包括信道控制器和多个传送控制器。信道控制器接收数据传输请求的优先次序和队列。传输控制器表的事件使得能够调用对应于数据传送请求的传送控制器号码。多个传送控制器是独立的并且可以同时并行操作。每个传送控制器包括一读读总线接口和一写写总线接口，在阻塞对干扰设备或地址范围的访问的情况下，与其它总线主机进行仲裁。

3. 发明申请

US20060259659A1 Data Transfer Apparatus With Channel Controller and Transfer Controller Capable of Slave and Standalone Operation 有权
标题翻译：具有通道控制器和转移控制器的数据传输设备，能够进行从属和独立操作
公开(公告)号：US20060259659A1
公开(公告)日：2006-11-16
申请号：US11383055
申请日：2006-05-12
申请人： Roger Castille , Natarajan Seshan , Marco Lazar , Henry C. Nguyen
发明人： Roger Castille , Natarajan Seshan , Marco Lazar , Henry C. Nguyen
IPC分类号： G06F3/00
CPC分类号： G06F13/4027 , H04L49/90
摘要： A data transfer control apparatus includes a channel controller and a transfer controller. The channel controller receives, prioritizes and queues data transfer requests. The transfer controller includes separate control of data source and data destination in a data transfer corresponding to the data transfer requests. The transfer controller includes a data transfer program register and active source and destination registers. The transfer controller operates from the active source and destination registers. Upon completion of a data transfer the transfer controller writes data transfer parameters from the data transfer program register to the active source and destination registers.
摘要翻译：数据传送控制装置包括通道控制器和传送控制器。信道控制器接收数据传输请求的优先次序和队列。传输控制器包括对与数据传输请求相对应的数据传输中的数据源和数据目的地的单独控制。传输控制器包括数据传输程序寄存器和有源源寄存器和目标寄存器。传输控制器从有源源和目标寄存器进行操作。数据传输完成后，传输控制器将数据传输参数从数据传输程序寄存器写入有源源寄存器和目标寄存器。

4. 发明授权

US6167466A Multi-channel serial port with programmable features 失效
标题翻译：具有可编程功能的多通道串口
公开(公告)号：US6167466A
公开(公告)日：2000-12-26
申请号：US55011
申请日：1998-04-03
申请人： Tai H. Nguyen , Jason A. T. Jones , Jonathan G. Bradley , Natarajan Seshan
发明人： Tai H. Nguyen , Jason A. T. Jones , Jonathan G. Bradley , Natarajan Seshan
IPC分类号： G06F9/30 , G06F9/302 , G06F15/78 , G06F13/00 , G06F9/00 , G06F13/14
CPC分类号： G06F9/3001 , G06F9/30098 , G06F15/7832
摘要： A microprocessor 1 is described which includes a multi-channel serial port (MCSP) 120. MCSP 120 includes clock generation and frame sync generation circuitry 300, multi-channel selection circuitry 310, and companding circuitry 320. The clock generation and frame sync generation circuitry is configurable by means of a Serial Port Control Register SPCR, and Receive Control Register RCR, a Transmit Control Register XCR, a Sample Rate Generator Register SRGR, and Pin Control Register PCR. The multi-channel selection circuitry is configurable by means of a Multi-Channel Register MCR, a Receive Channel Enable Register RCER and a Transmit Channel Enable Register XCER. Companding circuitry 320 performs optional expansion or compression of received or transmitted data using .mu.-LAW or A-LAW, as selected by the Receive Control Register or the Transmit Control Register.
摘要翻译：描述了包括多通道串行端口（MCSP）120的微处理器1.MCSP 120包括时钟产生和帧同步产生电路300，多通道选择电路310和压扩电路320.时钟产生和帧同步产生电路可通过串行端口控制寄存器SPCR和接收控制寄存器RCR，发送控制寄存器XCR，采样率发生器寄存器SRGR和引脚控制寄存器PCR进行配置。多通道选择电路可以通过多通道寄存器MCR，接收通道使能寄存器RCER和发送通道使能寄存器XCER进行配置。压缩电路320使用由接收控制寄存器或发送控制寄存器选择的mu -LAW或A-LAW来执行对接收或发送的数据的可选扩展或压缩。

5. 发明授权

US6055649A Processor test port with scan chains and data streaming 失效
标题翻译：具有扫描链和数据流的处理器测试端口
公开(公告)号：US6055649A
公开(公告)日：2000-04-25
申请号：US974630
申请日：1997-11-19
申请人： Douglas E. Deao , Natarajan Seshan , Anthony J. Lell
发明人： Douglas E. Deao , Natarajan Seshan , Anthony J. Lell
IPC分类号： G06F11/26 , G06F11/267 , G06F11/00
CPC分类号： G06F11/261 , G06F11/2236
摘要： A data processing system on an integrated circuit 42 with microprocessor 1 and peripheral devices 60-61 is provided with an emulation unit 50 which allows debugging and emulation of integrated circuit 42 when connected to an external test system 51. Microprocessor 1 has in instruction execution pipeline which has several execution phases which involve fetch/decode units 10a-c and functional execution units 12, 14, 16 and 18. The pipeline of microprocessor 1 is unprotected so that memory access latency to data memory 22 and register file 20 can be utilized by system program code which is stored in instruction memory 23. Emulation unit 50 provides means for emulating the unprotected pipeline of microprocessor 1 and for rapidly uploading and downloading memories 22-23. Emulation unit 50 operates in a manner to prevent extraneous operations from occurring which could otherwise affect memories 22-23 or peripheral devices 60-61 during emulation.
摘要翻译：具有微处理器1和外围设备60-61的集成电路42上的数据处理系统设置有仿真单元50，其在连接到外部测试系统51时允许集成电路42的调试和仿真。微处理器1在指令执行管线其具有涉及获取/解码单元10a-c和功能执行单元12,14,16和18的多个执行阶段。微处理器1的流水线是不受保护的，从而可以利用数据存储器22和寄存器文件20的存储器访问等待时间存储在指令存储器23中的系统程序代码。仿真单元50提供用于模拟微处理器1的未受保护流水线并用于快速上载和下载存储器22-23的装置。仿真单元50以防止在仿真期间可能影响存储器22-23或外围设备60-61的外来操作的方式操作。

6. 发明授权

US5862159A Parallelized cyclical redundancy check method 失效
标题翻译：并行循环冗余校验方法
公开(公告)号：US5862159A
公开(公告)日：1999-01-19
申请号：US712007
申请日：1996-09-11
申请人： Natarajan Seshan
发明人： Natarajan Seshan
IPC分类号： G06F11/10 , H03M13/09
CPC分类号： H03M13/091 , G06F11/10
摘要： A method for encoding information bits to derive a cyclically encoded group of code bits from the information bits that were encoded, using a computer processor. A sequence of data states are generated that are the result of a series of exclusive OR operations of each of the code bits with each of the bits of a first generator word and bitwise ANDing each of the resultant bits with the results of the next previous such exclusive OR operations shifted in the direction of the least significant bit ("LSB") so as to generate a data state. The invention involves the following steps. First, an initial data state of zero is provided. Next, the LSB of the code bits is bitwise exclusive ORed with the current data state. Next, the result of the previous step is bitwise ANDed with the value n, where n is a selected binary value 2.sup.x -1, where x is any positive integer. Next, the current data state is changed to the next sequential data state by changing the data state to one of 2.sup.x predetermined data states, depending on the x LSBs of the result of the previous step. Then, both the code bits and the now current data state are shifted by x bits in the direction of the LSB; and, finally, the second through fifth of the foregoing steps are repeated until all code bits have been operated on.
摘要翻译：一种用于编码信息位以从使用计算机处理器编码的信息位导出循环编码的码位组的方法。生成数据状态序列，其是每个码位与第一生成器字的每个位的一系列异或运算的结果，并且将每个结果位与下一个前一个的结果进行逐位AND 异或运算在最低有效位（“LSB”）的方向上移位，以产生数据状态。本发明涉及以下步骤。首先，提供零的初始数据状态。接下来，代码位的LSB与当前数据状态进行逐位异或运算。接下来，上一步骤的结果与值n进行按位AND，其中n是选择的二进制值2x-1，其中x是任何正整数。接下来，根据前一步骤的结果的x LSB，将当前数据状态改变为下一个顺序数据状态，通过将数据状态改变为2x预定数据状态之一。然后，码位和当前的数据状态都在LSB的方向上移位x位; 并且最后，重复上述步骤的第二到第五，直到所有的码位都被操作为止。

7. 发明授权

US06889320B1 Microprocessor with an instruction immediately next to a branch instruction for adding a constant to a program counter 有权
标题翻译：微处理器具有立即在分支指令旁边的指令，用于将常量添加到程序计数器
公开(公告)号：US06889320B1
公开(公告)日：2005-05-03
申请号：US09702462
申请日：2000-10-31
申请人： Alan L. Davis , Richard H. Scales , Natarajan Seshan , Eric J. Stotzer , Reid E. Tatge
发明人： Alan L. Davis , Richard H. Scales , Natarajan Seshan , Eric J. Stotzer , Reid E. Tatge
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38 , G06F9/42
CPC分类号： G06F9/30054 , G06F9/30072 , G06F9/30079 , G06F9/30178 , G06F9/321 , G06F9/3802 , G06F9/3842 , G06F9/3853
摘要： A data processing system with a microprocessor that has an instruction execution pipeline that includes fetch and decode stages and several functional execution units. Fetch packets contain a plurality of instruction words. Execution packets include a plurality of instruction words that can be executed in parallel by two or more execution units. An execution packet can span two or more fetch packets. An add (k) constant to program counter (ADDKPC) instruction is provided, such that a parameter specified by the ADDKPC instruction is combined with a value provided by a program counter of microprocessor. The ADDKPC instruction can also specify a number of delay slots after a branch instruction to be filled with virtual NOP instructions such that memory is not wasted with useless NOP instructions. An ADDKPC instruction can provide a relative address for use as a return address. A plurality of predicated ADDKPC instructions can provide a return address selected from a plurality of return addresses. A compiler can reorder code with an ADDKPC instruction to absorb useless NOP instructions.
摘要翻译：具有微处理器的数据处理系统具有包括读取和解码级的指令执行流水线以及若干功能执行单元。获取分组包含多个指令字。执行分组包括可由两个或多个执行单元并行执行的多个指令字。执行分组可以跨越两个或更多个获取分组。提供给程序计数器（ADDKPC）指令的add（k）常数，使得由ADDKPC指令指定的参数与由微处理器的程序计数器提供的值组合。 ADDKPC指令还可以指定要在虚拟NOP指令中填充的分支指令之后的多个延迟槽，以使内存不会浪费无用的NOP指令。 ADDKPC指令可以提供用作返回地址的相对地址。多个预测的ADDKPC指令可以提供从多个返回地址中选择的返回地址。编译器可以使用ADDKPC指令重新排序代码，以吸收无用的NOP指令。

8. 发明授权

US6016555A Non-intrusive software breakpoints in a processor instruction execution pipeline 失效
标题翻译：处理器指令执行管道中的非侵入式软件断点
公开(公告)号：US6016555A
公开(公告)日：2000-01-18
申请号：US974744
申请日：1997-11-19
申请人： Douglas E. Deao , Natarajan Seshan
发明人： Douglas E. Deao , Natarajan Seshan
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G06F11/36 , G06F15/78
CPC分类号： G06F9/3005 , G06F11/362 , G06F9/30072 , G06F9/30185 , G06F9/3867
摘要： A data processing system on an integrated circuit 42 with microprocessor 1 and peripheral devices 60-61 is provided with an emulation unit 50 which allows debugging and emulation of integrated circuit 42 when connected to an external test system 51. Microprocessor 1 has in instruction execution pipeline which has several execution phases which involve fetch/decode units 10a-c and functional execution units 12, 14, 16 and 18. The pipeline of microprocessor 1 is unprotected so that memory access latency to data memory 22 and register file 20 can be utilized by system program code which is stored in instruction memory 23. Emulation unit 50 provides means for emulating the unprotected pipeline of microprocessor 1 and for rapidly uploading and downloading memories 22-23. Emulation unit 50 operates in a manner to prevent extraneous operations from occurring which could otherwise affect memories 22-23 or peripheral devices 60-61 during emulation.
摘要翻译：具有微处理器1和外围设备60-61的集成电路42上的数据处理系统设置有仿真单元50，其在连接到外部测试系统51时允许集成电路42的调试和仿真。微处理器1在指令执行管线其具有涉及获取/解码单元10a-c和功能执行单元12,14,16和18的多个执行阶段。微处理器1的流水线是不受保护的，从而可以利用数据存储器22和寄存器文件20的存储器访问等待时间存储在指令存储器23中的系统程序代码。仿真单元50提供用于模拟微处理器1的未受保护流水线并用于快速上载和下载存储器22-23的装置。仿真单元50以防止在仿真期间可能影响存储器22-23或外围设备60-61的外来操作的方式操作。

9. 发明授权

US5841379A Method and apparatus for selectively counting consecutive bits 失效
标题翻译：连续位选择性计数的方法和装置
公开(公告)号：US5841379A
公开(公告)日：1998-11-24
申请号：US788751
申请日：1997-01-24
申请人： Natarajan Seshan , Laurence R. Simar, Jr.
发明人： Natarajan Seshan , Laurence R. Simar, Jr.
IPC分类号： H03M7/46
CPC分类号： H03M7/46
摘要： A method for compression of digital data in a computer having a processor and a memory, wherein a group of consecutive bits having the same binary value is represented by a result number corresponding to the number of the consecutive bits. The method involves the following steps. A block of digital data to be compressed is provided. A bit detect selection parameter determines a bit value to be counted for counting consecutive bits. The processor is instructed to count from a first end of the block of digital data toward a second end of the block of digital data the number of consecutive bits having the bit value determined by the bit detect selection parameter. The number of bits so counted is stored, and the bit detect selection parameter is toggled. The processor is then instructed to count from the last bit counted toward the second end of the block of digital data the number of bits having the bit value determined by the current bit detect selection parameter. The foregoing steps are repeated, with successive numbers being stored representing the number of bits counted in successive counts as successive stored result numbers, until all bits in the block of digital data are counted.
摘要翻译：一种用于在具有处理器和存储器的计算机中压缩数字数据的方法，其中具有相同二进制值的一组连续位由对应于连续位数的结果编号表示。该方法包括以下步骤。提供要压缩的数字数据块。位检测选择参数确定要计数连续位的位值。指示处理器从数字数据块的第一端向数字数据块的第二端计数具有由位检测选择参数确定的位值的连续位的数目。存储如此计数的位数，并且切换位检测选择参数。然后指示处理器从由数字数据块的第二端计数的最后位计数具有由当前位检测选择参数确定的位值的位数。重复上述步骤，连续的数字被存储，表示以连续计数计数的位数作为连续存储的结果编号，直到对数字数据块中的所有位进行计数。

10. 发明授权

US07570646B2 Apparatus and method for an interface unit for data transfer between a host processing unit and a multi-target digital signal processing unit in an asynchronous transfer mode 有权
标题翻译：用于以异步传送模式在主处理单元和多目标数字信号处理单元之间进行数据传送的接口单元的装置和方法
公开(公告)号：US07570646B2
公开(公告)日：2009-08-04
申请号：US09964158
申请日：2001-09-26
申请人： Martin Li , Jay B. Reimer , Shakuntala Anjanaiah , Natarajan Seshan , Patrick J. Smith
发明人： Martin Li , Jay B. Reimer , Shakuntala Anjanaiah , Natarajan Seshan , Patrick J. Smith
IPC分类号： H04L12/28
CPC分类号： G06F13/4004 , G06F1/24 , G06F13/28 , G06F13/385
摘要： A slave interface unit controls the exchange of data between a master processing unit and a plurality of slave processing units operating in the asynchronous transfer mode (ATM) of operation. The ATM slave interface unit has a receive unit and a transmit unit that exchange data cells and control signals with the ATM master processing unit. The receive unit and the transmit unit are coupled to a receive buffer storage unit and a transmit buffer storage unit, respectively. The receive buffer storage unit and the transmit buffer storage unit exchange data and control signals with the direct memory access unit. The ATM slave interface unit includes a configuration interface unit having a register that identifies the location in the data cell where the destination address is located and relates the destination address to the particular processing unit or memory location. The receive buffer unit uses the information in the register to determine the destination of the data cell.
摘要翻译：从接口单元控制主处理单元和以异步传送模式（ATM）操作的多个从属处理单元之间的数据交换。 ATM从接口单元具有接收单元和与ATM主处理单元交换数据信元和控制信号的发送单元。接收单元和发送单元分别耦合到接收缓冲存储单元和发送缓冲存储单元。接收缓冲存储单元和发送缓冲存储单元与直接存储器存取单元交换数据和控制信号。 ATM从接口单元包括配置接口单元，其具有标识目的地址所在的数据单元中的位置的寄存器，并将目的地地址与特定处理单元或存储器位置相关联。接收缓冲器单元使用寄存器中的信息来确定数据单元的目的地。

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