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1. 发明授权

US08391469B2 Methods and apparatus to decode dual-tone signals 有权
标题翻译：解码双音信号的方法和装置
公开(公告)号：US08391469B2
公开(公告)日：2013-03-05
申请号：US12171832
申请日：2008-07-11
申请人： Steven Edward Marum , Kenneth L. Williams
发明人： Steven Edward Marum , Kenneth L. Williams
IPC分类号： H04M1/00 , H04M3/00 , G06F17/10
CPC分类号： H04Q1/4575
摘要： Methods and apparatus to decode dual-tone signals are disclosed. An example receiver to decode a dual-tone signal includes a tone detector to detect a start of a first tone, a first counter to count first cycles of the first tone, a second counter to count second cycles of a system clock while the first counter is counting and the first count is less than a first threshold, state control logic to start the second counter counting third cycles of the clock when a time period elapses, the third count being substantially equal to the second count, the first counter to count fourth cycles of a second tone while the third cycles are counted, and a decoder to compare the fourth count to a second threshold to identify an event represented by the signal.
摘要翻译：公开了解码双音信号的方法和装置。用于解码双音信号的示例性接收机包括用于检测第一音调开始的音调检测器，计数第一音调的第一周期的第一计数器，对第一计数器计数系统时钟的第二周期的第二计数器正在计数并且第一计数小于第一阈值，状态控制逻辑开始第二计数器计数经过时间的时钟的第三周期，第三计数基本上等于第二计数，第一计数器计数第四计数对第三个周期进行计数的第二音调的周期，以及将第四计数与第二阈值进行比较以识别由该信号表示的事件的解码器。

2. 发明授权

US5594700A Sequential memory 失效
标题翻译：顺序记忆
公开(公告)号：US5594700A
公开(公告)日：1997-01-14
申请号：US192755
申请日：1994-02-07
申请人： Morris D. Ward , Kenneth L. Williams
发明人： Morris D. Ward , Kenneth L. Williams
IPC分类号： G06F5/16 , G11C7/10 , G11C7/00 , G11C8/04
CPC分类号： G11C7/1042
摘要： A sequential memory (10) uses interleaved memories (12a-b) with associated output buffers (22a-b) to accomplish high data rates. Data access control circuitry (18) and bank select circuitry (20) control the order in which the memory banks (12a-b) are written to and read from. Output buffer circuits (22a-b) allow a data word to be read instantaneously after it is written to the sequential memory (10).
摘要翻译：顺序存储器（10）使用具有相关输出缓冲器（22a-b）的交错存储器（12a-b）来实现高数据速率。数据访问控制电路（18）和存储体选择电路（20）控制存储体（12a-b）写入和读取的顺序。输出缓冲器电路（22a-b）允许在写入顺序存储器（10）之后立即读取数据字。

3. 发明授权

US5097442A Programmable depth first-in, first-out memory 失效
标题翻译：可编程深度先进先出存储器
公开(公告)号：US5097442A
公开(公告)日：1992-03-17
申请号：US146526
申请日：1988-01-21
申请人： M. Dwayne Ward , Kenneth L. Williams
发明人： M. Dwayne Ward , Kenneth L. Williams
IPC分类号： G06F5/10 , G06F5/12 , G06F5/14 , G11C8/04
CPC分类号： G06F5/14 , G06F5/12 , G11C8/04 , G06F2205/123 , G06F2205/126
摘要： A first-in, first-out memory (10) can store a programmable number of data words at respective address locations within a memory (76). A read address generator (50, 58) generates a read pointer for pointing to a read address location in the memory (76). A depth address generator (42) points to a depth address location in the memory that is displaced from the read address location by a predetermined number of address locations. This depth address generator (42) is incremented to a next read depth address responsive to a read pulse (20) issued from a read/write controller (12). A write address generator (80) points to a write address location within memory (76). A comparator (52) compares the value stored in the write address generator (42) to the read depth address location stored in depth address generator (42) and is operable to generate a FULL memory status flag (24) responsive to their equality. Preferably, the comparator (52) also compares the read address to the write address, and is operable to generate an EMPTY status flag (26) responsive to their equality.
摘要翻译：先入先出存储器（10）可以将可编程数量的数据字存储在存储器（76）内的相应地址位置。读地址生成器（50,58）生成用于指向存储器（76）中的读地址位置的读指针。深度地址生成器（42）指向存储器中的从读取地址位置移位了预定数量的地址位置的深度地址位置。该深度地址发生器（42）响应于从读/写控制器（12）发出的读脉冲（20）而递增到下一读深度地址。写入地址生成器（80）指向存储器（76）内的写入地址位置。比较器（52）将存储在写入地址生成器（42）中的值与存储在深度地址生成器（42）中的读取深度地址位置进行比较，并且可操作以响应于它们的相等而产生FULL存储器状态标志（24）。优选地，比较器（52）还将读取的地址与写入地址进行比较，并且可操作以响应于它们的相等来产生EMPTY状态标志（26）。

4. 发明授权

US5084841A Programmable status flag generator FIFO using gray code 失效
标题翻译：可编程状态标志发生器FIFO使用灰色代码
公开(公告)号：US5084841A
公开(公告)日：1992-01-28
申请号：US393440
申请日：1989-08-14
申请人： Kenneth L. Williams , Morris D. Ward
发明人： Kenneth L. Williams , Morris D. Ward
IPC分类号： G06F3/06 , G06F5/06 , G06F5/10 , G06F5/12 , G06F5/14 , G11C7/00
CPC分类号： G06F5/14 , G06F5/12 , G06F2205/102 , G06F2205/126
摘要： A FIFO 12 has a status flag generator 14. The status flag generator 14 includes a register programmable to "N". It also includes two sets of gray-code counters and a register (22,23,21;26,25,24) that are driven by separate READ and WRITE CLKS. The registers and counters are connected to comparators (31-36) for generating a plurality of signals that are input to output latches (41-43). The status flag generator is capable of generating status signals of FULL, HALF-FULL, EMPTY, FULL-N and EMPTY+N. N is a user-defined number that is programmed into a register 20 that is selectively connected to one or more of the programmable gray-code counters (23,24).
摘要翻译： FIFO12具有状态标志发生器14.状态标志发生器14包括可编程为“N”的寄存器。它还包括两组灰度计数器和一个由独立的READ和WRITE CLKS驱动的寄存器（22,23,21; 26,25,24）。寄存器和计数器连接到比较器（31-36），用于产生输入到输出锁存器（41-43）的多个信号。状态标志发生器能够产生FULL，HALF-FULL，EMPTY，FULL-N和EMPTY + N的状态信号。 N是被编程到寄存器20中的用户定义的数字，其被选择性地连接到一个或多个可编程灰色代码计数器（23,24）。

5. 发明申请

US20080116827A1 METHOD AND CIRCUIT FOR CONTROLLING OPERATION OF A LIGHT-EMITTING DIODE 有权
标题翻译：用于控制发光二极管操作的方法和电路
公开(公告)号：US20080116827A1
公开(公告)日：2008-05-22
申请号：US11941236
申请日：2007-11-16
申请人： Kenneth L. Williams
发明人： Kenneth L. Williams
IPC分类号： H05B37/02
CPC分类号： H05B33/0851 , H05B33/0848
摘要： A light-emitting diode control circuit is provided, that includes: a duration selection circuit for selecting one of a first duration value, a second duration value, a third duration value, or a fourth duration value as a selected duration value based on a selection signal; a control clock generator for generating a control clock signal based on a slow clock signal and the selected duration value; a selection signal generator for generating the selection signal based on the control clock signal; an intensity signal generator for generating a current intensity signal based on a first intensity value, a second intensity value, the control clock signal, and the selection signal; a reference wave generator for generating a reference wave based on a fast clock signal; and a comparator for comparing the current intensity signal and the reference wave to generate a pulse width modulation signal to control the light-emitting diode.
摘要翻译：提供了一种发光二极管控制电路，其包括：持续时间选择电路，用于基于选择来选择第一持续时间值，第二持续时间值，第三持续时间值或第四持续时间值中的一个作为所选择的持续时间值信号; 控制时钟发生器，用于基于慢时钟信号和所选择的持续时间值产生控制时钟信号; 选择信号发生器，用于基于控制时钟信号产生选择信号; 强度信号发生器，用于基于第一强度值，第二强度值，控制时钟信号和选择信号产生电流强度信号; 用于基于快速时钟信号产生参考波的参考波发生器; 以及比较器，用于比较电流强度信号和参考波，以产生用于控制发光二极管的脉宽调制信号。

6. 发明授权

US5365485A Fifo with fast retransmit mode 失效
标题翻译： Fifo具有快速重传模式
公开(公告)号：US5365485A
公开(公告)日：1994-11-15
申请号：US156115
申请日：1993-11-22
申请人： M. Dwayne Ward , Kenneth L. Williams , Kevin J. Craig
发明人： M. Dwayne Ward , Kenneth L. Williams , Kevin J. Craig
IPC分类号： G06F5/06 , G11C7/00 , G11C21/00
CPC分类号： G06F5/06
摘要： A clocked first-in first-out (FIFO) memory includes interleaved dual-port static random access memories (SRAM's) 32 and 36. The FIFO has status flags 44 to indicate empty and full conditions and two programmable flags, almost full and almost empty, to indicate when a selected number of words is stored in memory. In accordance with the present invention, the FIFO has retransmit capability, allowing previously read data to be accessed again. The FIFO is put in retransmit mode by providing a retransmit mode (RTM) input signal. This event causes the current read address stored in the read address registers 52 and 54, the interleave status in toggle circuit 22, the data in the data output latches 18 and 20 and in the pipeline latch 42, and the status flags 44, to be saved in shadow registers 64, 66, 24, (30, 62, 70, 116 and 120. While the FIFO is in the retransmit mode, the occurrence of a Read From Mark input signal initiates the retransmit process, during which the saved read address count, output data and status flags are restored from their respective shadow registers, and the data from this restored starting point is retransmitted on the data out buffer 46. Data may be repeatedly retransmitted from the saved starting position. A new retransmit starting position may be selected after taking the FIFO out of retransmit mode by removing the RTM input signal.
摘要翻译：时钟先进先出（FIFO）存储器包括交织的双端口静态随机存取存储器（SRAM）32和36. FIFO具有状态标志44，以指示空和满状态以及两个可编程标志，几乎为空且几乎为空，以指示所选择的字数何时存储在存储器中。根据本发明，FIFO具有重传能力，允许再次访问先前读取的数据。通过提供重传模式（RTM）输入信号将FIFO置于重传模式。该事件使得存储在读地址寄存器52和54中的当前读地址，触发电路22中的交错状态，数据输出锁存器18和20以及流水线锁存器42中的数据以及状态标志44为保存在影子寄存器64,66,24（30,62,70,116和120）（30,62,70,116和120）中。当FIFO处于重传模式时，读取标记输入信号的发生启动重传过程，在此期间保存的读地址计数，输出数据和状态标志从其各自的影子寄存器恢复，并且来自该恢复的起始点的数据在数据输出缓冲器46上被重新发送。可以从保存的起始位置重复发送数据，新的重发起始位置可以是通过取出RTM输入信号使FIFO退出重发模式后选择。

7. 发明授权

US4839866A Cascadable first-in, first-out memory 失效
标题翻译：先进先出的内存
公开(公告)号：US4839866A
公开(公告)日：1989-06-13
申请号：US55669
申请日：1987-05-29
申请人： Morris D. Ward , Kenneth L. Williams
发明人： Morris D. Ward , Kenneth L. Williams
IPC分类号： G06F5/10
CPC分类号： G06F5/10
摘要： A cascadable first-in, first-out memory unit (11, 12, 13) has a load/unload control (152) for write-addressing and read-addressing selected memory locations within its memory array (82). A write pointer (110, 112, 120) keeps track of the number of write operations that have occurred in the selected memory unit, and a read pointer (130, 132, 142) does the same for the number of read operations. When the number of write operations performed since a last reset pulse (416) equals the number of memory locations in the memory array (82), write control passes to the next succeeding FIFO memory unit by a descending transition of an output control signal (444). Read control is passed to the subsequent FIFO by an ascending transition (470) of the same output control signal. Combination first load, master reset and output control circuitry (54-58, 192) is provided to select the first memory unit (11) for read and write operations, and to disable the outputs (18) of all of the FIFO memory units independent of the master reset signal (55).
摘要翻译：可级联的先入先出存储器单元（11,12,13）具有用于在其存储器阵列（82）内的写寻址和读寻址选择的存储器位置的加载/卸载控制（152）。写指针（110,112,120）跟踪在所选择的存储器单元中已经发生的写入操作的数量，并且读指针（130,132,142）对于读操作的数量执行相同操作。当从上一个复位脉冲（416）执行的写入操作的数量等于存储器阵列（82）中的存储器位置的数量时，通过输出控制信号（444）的下降转换将写入控制传递到下一个后续的FIFO存储器单元）。读控制通过相同输出控制信号的上升跃迁（470）传递到随后的FIFO。提供组合的第一负载，主复位和输出控制电路（54-58,192）以选择用于读和写操作的第一存储器单元（11），并且禁用所有FIFO存储器单元的输出（18）独立的主复位信号（55）。

8. 发明授权

US4829475A Method and apparatus for simultaneous address increment and memory write operations 失效
标题翻译：用于同时地址递增和存储器写入操作的方法和装置
公开(公告)号：US4829475A
公开(公告)日：1989-05-09
申请号：US892228
申请日：1986-08-01
申请人： Morris D. Ward , Kenneth L. Williams
发明人： Morris D. Ward , Kenneth L. Williams
IPC分类号： G06F5/14 , G06F5/06 , G06F5/08 , G06F5/10 , G06F5/12 , G06F13/38 , G11C7/00
CPC分类号： G06F5/12 , G06F2205/123
摘要： A First-In First-Out (FIFO) shift register memory system (10) with a plurality of memory word registers (50) having data inputs connected to a common data-in bus (16), and a plurality of data outputs connected to a common data-out bus (22). A write address ring counter (32) is responsive to first transitions (164, 168) of a write pulses to increment to successive stages (32) therein. A plurality of latches (154) are each responsive to a second transition (166) to latch in a write address bit. The latches (154) are each enabled to write the address bit to a respective memory register (50) upon a successive first transition (168).
摘要翻译：具有连接到公共数据总线（16）的数据输入的多个存储器字寄存器（50）的先进先出（FIFO）移位寄存器存储器系统（10），以及多个数据输出连接到公共数据总线（22）。写地址环计数器（32）响应于写入脉冲的第一转换（164,168），以递增到其中的连续级（32）。多个锁存器（154）各自响应于第二转换（166）以锁存写入地址位。锁存器（154）各自被使能以在连续的第一转换（168）时将地址位写入相应的存储器寄存器（50）。

9. 发明授权

US07701152B2 Method and circuit for controlling operation of a light-emitting diode 有权
标题翻译：用于控制发光二极管的操作的方法和电路
公开(公告)号：US07701152B2
公开(公告)日：2010-04-20
申请号：US11941236
申请日：2007-11-16
申请人： Kenneth L Williams
发明人： Kenneth L Williams
IPC分类号： H05B37/02
CPC分类号： H05B33/0851 , H05B33/0848
摘要： A light-emitting diode control circuit is provided, that includes: a duration selection circuit for selecting one of a first duration value, a second duration value, a third duration value, or a fourth duration value as a selected duration value based on a selection signal; a control clock generator for generating a control clock signal based on a slow clock signal and the selected duration value; a selection signal generator for generating the selection signal based on the control clock signal; an intensity signal generator for generating a current intensity signal based on a first intensity value, a second intensity value, the control clock signal, and the selection signal; a reference wave generator for generating a reference wave based on a fast clock signal; and a comparator for comparing the current intensity signal and the reference wave to generate a pulse width modulation signal to control the light-emitting diode.
摘要翻译：提供了一种发光二极管控制电路，其包括：持续时间选择电路，用于基于选择来选择第一持续时间值，第二持续时间值，第三持续时间值或第四持续时间值中的一个作为所选择的持续时间值信号; 控制时钟发生器，用于基于慢时钟信号和所选择的持续时间值产生控制时钟信号; 选择信号发生器，用于基于控制时钟信号产生选择信号; 强度信号发生器，用于基于第一强度值，第二强度值，控制时钟信号和选择信号产生电流强度信号; 用于基于快速时钟信号产生参考波的参考波发生器; 以及比较器，用于比较电流强度信号和参考波，以产生用于控制发光二极管的脉宽调制信号。

10. 发明授权

US06311234B1 Direct memory access controller with split channel transfer capability and FIFO buffering 有权
标题翻译：直接存储器访问控制器，具有分离的信道传输能力和FIFO缓冲
公开(公告)号：US06311234B1
公开(公告)日：2001-10-30
申请号：US09633998
申请日：2000-08-08
申请人： Natarajan Seshan , Jeffrey R. Quay , Kenneth L. Williams , Michael J. Moody
发明人： Natarajan Seshan , Jeffrey R. Quay , Kenneth L. Williams , Michael J. Moody
IPC分类号： G06F1328
CPC分类号： G06F9/3001 , G06F9/30098 , G06F15/7832
摘要： A microprocessor 1 is described which includes a direct memory access (DMA) circuitry 143. DMA 143 is interconnected with a program memory 23 and a data memory 22 and is operational to transfer data to or from these memories. DMA 143 is interconnected with a peripheral bus 110 and thereby to various peripherals internal to microprocessor 1. DMA 143 is also interconnected with an external memory interface 103 and thereby to various external memory circuits and peripherals external to microprocessor 1. An auxiliary channel control circuitry 160 provides DMA transfers by interacting with a peripheral such as host port 150 which has its own address generation circuitry. DMA 143 provides frame synchronization for triggering a frame transfer, or group of transfers. DMA 143 is auto-initialized through registers. DMA action complete pins DMAC0-3 indicate DMA status to external devices. DMA 143 allows for local variability of transfer rates in a split channel mode of operation by allowing a transmit channel to get ahead of a corresponding receive channel by a preselected number of data words.
摘要翻译：描述了包括直接存储器访问（DMA）电路143的微处理器1.DMA 143与程序存储器23和数据存储器22互连，并且可操作以将数据传送到这些存储器或从这些存储器传送数据。 DMA 143与外围总线110互连，从而与微处理器1内部的各种外围设备互连.DMA 143也与外部存储器接口103互连，从而连接到微处理器1外部的各种外部存储器电路和外围设备。辅助通道控制电路160 通过与诸如具有其自己的地址产生电路的主机端口150的外围设备交互来提供DMA传输。 DMA 143提供用于触发帧传送或传送组的帧同步。 DMA 143通过寄存器自动初始化。 DMA操作完成引脚DMAC0-3指示外部设备的DMA状态。 DMA 143允许通过允许发送信道通过预选数量的数据字而在对应的接收信道之前的分离信道操作模式中的传输速率的局部变化。

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