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11. 发明授权

US08664102B2 Dual sidewall spacer for seam protection of a patterned structure 有权
标题翻译：用于图案化结构的接缝保护的双侧壁间隔件
公开(公告)号：US08664102B2
公开(公告)日：2014-03-04
申请号：US12751891
申请日：2010-03-31
申请人： David L. O'Meara , Anthony Dip , Aelan Mosden , Pao-Hwa Chou , Richard A Conti
发明人： David L. O'Meara , Anthony Dip , Aelan Mosden , Pao-Hwa Chou , Richard A Conti
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L29/4983 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A semiconducting device with a dual sidewall spacer and method of forming are provided. The method includes: depositing a first spacer layer over a patterned structure, the first spacer layer having a seam propagating through a thickness of the first spacer layer near an interface region of a surface of the substrate and a sidewall of the patterned structure, etching the first spacer layer to form a residual spacer at the interface region, where the residual spacer coats less than the entirety of the sidewall of the patterned structure, depositing a second spacer layer on the residual spacer and on the sidewall of the patterned structure not coated by the residual spacer, the second spacer layer being seam-free on the seam of the residual spacer, and etching the second spacer layer to form a second spacer coating the residual spacer and coating the sidewall of the patterned structure not coated by the residual spacer.
摘要翻译：提供了具有双侧壁间隔件和成形方法的半导体器件。该方法包括：在图案化结构上沉积第一间隔层，第一间隔层具有在衬底的表面的界面区附近传播穿过第一间隔层的厚度的接缝和图案化结构的侧壁，蚀刻第一间隔层，以在界面区域处形成残留间隔物，其中残余间隔物涂覆小于图案化结构的侧壁的整体，在剩余间隔物上和在图案化结构的侧壁上沉积第二间隔层，所述剩余间隔物，所述第二间隔层在所述残余间隔物的接缝上是无缝的，并且蚀刻所述第二间隔层以形成涂覆所述剩余间隔物并涂覆未被所述残留间隔物涂覆的所述图案化结构的侧壁的第二间隔物。

12. 发明申请

US20130196505A1 METHOD OF FORMING CONFORMAL METAL SILICIDE FILMS 有权
标题翻译：形成一致的金属硅膜的方法
公开(公告)号：US20130196505A1
公开(公告)日：2013-08-01
申请号：US13427343
申请日：2012-03-22
申请人： Toshio Hasegawa , Kunihiro Tada , Hideaki Yamasaki , David L. O'Meara , Gerrit J. Leusink
发明人： Toshio Hasegawa , Kunihiro Tada , Hideaki Yamasaki , David L. O'Meara , Gerrit J. Leusink
IPC分类号： H01L21/3205
CPC分类号： H01L21/76898 , C23C16/42 , C23C16/45538 , H01L21/28518 , H01L21/28562 , H01L28/91 , H01L29/66181
摘要： A method is provided for forming a metal silicide layer on a substrate. According to one embodiment the method includes providing the substrate in a process chamber, exposing the substrate at a first substrate temperature to a plasma generated from a deposition gas containing a metal precursor, where the plasma exposure forms a conformal metal-containing layer on the substrate in a self-limiting process. The method further includes exposing the metal-containing layer at a second substrate temperature to a reducing gas in the absence of a plasma, where the exposing steps are alternatively performed at least once to form the metal silicide layer, and the deposition gas does not contain the reducing gas. The method provides conformal metal silicide formation in deep trenches with high aspect ratios.
摘要翻译：提供了一种在衬底上形成金属硅化物层的方法。根据一个实施例，该方法包括在处理室中提供衬底，将衬底在第一衬底温度下暴露于由包含金属前体的沉积气体产生的等离子体，其中等离子体暴露在衬底上形成保形的含金属层在一个自限制的过程中。该方法还包括在不存在等离子体的情况下将第二衬底温度下的含金属层暴露于还原气体，其中暴露步骤交替进行一次以形成金属硅化物层，并且沉积气体不含还原气。该方法提供了具有高纵横比的深沟槽中的保形金属硅化物形成。

13. 发明申请

US20110241128A1 MULTILAYER SIDEWALL SPACER FOR SEAM PROTECTION OF A PATTERNED STRUCTURE 有权
标题翻译：用于保护结构的多层平板隔墙
公开(公告)号：US20110241128A1
公开(公告)日：2011-10-06
申请号：US12751926
申请日：2010-03-31
申请人： David L. O'Meara , Anthony Dip , Aelan Mosden , Pao-Hwa Chou , Richard A. Conti
发明人： David L. O'Meara , Anthony Dip , Aelan Mosden , Pao-Hwa Chou , Richard A. Conti
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/28247 , H01L29/6656
摘要： A semiconducting device with a multilayer sidewall spacer and method of forming are described. In one embodiment, the method includes providing a substrate containing a patterned structure on a surface of the substrate and depositing a first spacer layer over the patterned structure at a first substrate temperature, where the first spacer layer contains a first material. The method further includes depositing a second spacer layer over the patterned substrate at a second substrate temperature that is different from the first substrate temperature, where the first and second materials contain the same chemical elements, and the depositing steps are performed in any order. The first and second spacer layers are then etched to form the multilayer sidewall spacer on the patterned structure.
摘要翻译：描述了具有多层侧壁间隔件和形成方法的半导体器件。在一个实施例中，该方法包括在衬底的表面上提供含有图案化结构的衬底，并且在第一衬底温度下在第一衬底温度下沉积在图案化结构上的第一间隔层，其中第一间隔层包含第一材料。该方法还包括在不同于第一衬底温度的第二衬底温度下在图案化衬底上沉积第二间隔层，其中第一和第二材料含有相同的化学元素，并且沉积步骤以任何顺序进行。然后蚀刻第一和第二间隔层以在图案化结构上形成多层侧壁间隔物。

14. 发明授权

US06362071B1 Method for forming a semiconductor device with an opening in a dielectric layer 有权
标题翻译：用于形成在电介质层中具有开口的半导体器件的方法
公开(公告)号：US06362071B1
公开(公告)日：2002-03-26
申请号：US09542706
申请日：2000-04-05
申请人： Bich-Yen Nguyen , William J. Taylor, Jr. , Philip J. Tobin , David L. O'Meara , Percy V. Gilbert , Yeong-Jyh T. Lii , Victor S. Wang
发明人： Bich-Yen Nguyen , William J. Taylor, Jr. , Philip J. Tobin , David L. O'Meara , Percy V. Gilbert , Yeong-Jyh T. Lii , Victor S. Wang
IPC分类号： H01L2176
CPC分类号： H01L21/76232 , H01L21/823481
摘要： In accordance with one embodiment of the present invention, a method is disclosed for forming a semiconductor device having an isolation region (601). A dielectric layer (108) is deposited and etched to form isolation regions (102, 605) having top portions that are narrower than their bottom portions, thereby a tapered isolation region is formed. Active regions (601, 603) are formed using an epitaxial process in the regions between the isolation regions. The resulting active regions (601, 603) have a greater amount of surface area near a top portion, than near a bottom portion. Transistors (721, 723) having opposite polarities are formed within the active areas.
摘要翻译：根据本发明的一个实施例，公开了一种用于形成具有隔离区域（601）的半导体器件的方法。沉积和蚀刻电介质层（108）以形成具有比其底部部分更窄的顶部部分的隔离区域（102,605），从而形成锥形隔离区域。在隔离区域之间的区域中使用外延工艺形成有源区（601,603）。所得活性区域（601,603）在顶部附近具有比在底部附近更大的表面积。在有源区域内形成具有相反极性的晶体管（721,723）。

15. 发明授权

US06320784B1 Memory cell and method for programming thereof 有权
标题翻译：存储单元及其编程方法
公开(公告)号：US06320784B1
公开(公告)日：2001-11-20
申请号：US09524916
申请日：2000-03-14
申请人： Ramachandran Muralidhar , Sucharita Madhukar , Bo Jiang , Bruce E. White , Srikanth B. Samavedam , David L. O'Meara , Michael Alan Sadd
发明人： Ramachandran Muralidhar , Sucharita Madhukar , Bo Jiang , Bruce E. White , Srikanth B. Samavedam , David L. O'Meara , Michael Alan Sadd
IPC分类号： G11C1100
CPC分类号： B82Y10/00 , G11C11/56 , G11C11/5671 , G11C16/0416 , G11C2216/08 , H01L29/7887 , H01L29/7888
摘要： A memory cell (101), its method of formation, and operation are disclosed. In accordance with one embodiment, the memory cell (101) comprises a first and second current carrying electrode (12) a control electrode (19), and doped discontinuous storage elements (17). In accordance with an alternative embodiment, memory cell programming is accomplished by removing or adding an average of approximately at least a first charge (30, 62, 64), which can be electron(s) or hole(s) from each of the doped discontinuous storage elements (17).
摘要翻译：公开了一种存储单元（101），其形成方法和操作。根据一个实施例，存储单元（101）包括第一和第二载流电极（12），控制电极（19）和掺杂的非连续存储元件（17）。根据替代实施例，存储器单元编程通过去除或添加大约至少第一电荷（30,62,64）的平均值来实现，所述第一电荷可以是来自掺杂的每一个的电子或空穴不连续存储元件（17）。

16. 发明授权

US5013690A Method for deposition of silicon films from azidosilane sources 失效
标题翻译：从叠氮硅烷源沉积硅膜的方法
公开(公告)号：US5013690A
公开(公告)日：1991-05-07
申请号：US473546
申请日：1990-02-01
申请人： Arthur K. Hochberg , David L. O'Meara , David A. Roberts
发明人： Arthur K. Hochberg , David L. O'Meara , David A. Roberts
IPC分类号： H01L21/205 , H01L21/314 , H01L21/316 , H01L21/318
CPC分类号： H01L21/3185 , H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/3145 , H01L21/31612 , Y10S148/122 , Y10S438/934
摘要： A low temperature chemical vapor deposition process comprising heating in a chemical vapor depositon reactor a substrate upon which deposition is desired to a temperature of from about 550.degree. C. to about 750.degree. C. in a chemical vapor deposition reactor having a pressure of from about 0.1 torr to approximately atmospheric pressure, introducing into the reactor a silicon-containing feed and optionally an oxygen containing feed, said silicon containing feed consisting essentially of one or more compounds having the general formula ##STR1## wherein: R.sub.1, R.sub.2, R.sub.3 and R.sub.4 are hydrogen, azido or C-2 to C-6 alkyl, aryl or C-7 to C-10 aralkyl groups, at least one but not more than three of R.sub.1, R.sub.2, R.sub.3 and R.sub.4, being azido, and maintaining the temperature and pressure to cause a film of silicon nitride, silicon oxynitride or silicon dioxide to deposit is disclosed.
摘要翻译：一种低温化学气相沉积方法，其包括在化学气相沉积反应器中加热基底，在基底上沉积希望在约550℃至约750℃的温度下在具有约 0.1托至约大气压，将含硅进料和任选的含氧进料引入反应器中，所述含硅进料基本上由一种或多种具有通式为其中的化合物组成：其中：R1，R2，R3和R4 是氢，叠氮基或C-2至C-6烷基，芳基或C-7至C-10芳烷基，R1，R2，R3和R4中至少一个但不多于三个为叠氮基，并保持温度并且公开了使氮化硅，氮氧化硅或二氧化硅的膜沉积的压力。

17. 发明授权

US08809169B2 Multi-layer pattern for alternate ALD processes 有权
标题翻译：用于替代ALD过程的多层模式
公开(公告)号：US08809169B2
公开(公告)日：2014-08-19
申请号：US13250937
申请日：2011-09-30
申请人： David L. O'Meara , Aelan Mosden
发明人： David L. O'Meara , Aelan Mosden
IPC分类号： H01L21/20 , H01L21/033
CPC分类号： H01L21/0337 , H01L21/0338
摘要： A method of patterning a substrate. A sacrificial film is formed over a substrate and a pattern created therein. A first spacer layer is conformally deposited over the patterned sacrificial film and at least one horizontal portion of the first spacer layer is removed while vertical portions of the first spacer layer remain. A second spacer layer is conformally deposited over the patterned sacrificial film and the remaining portions of the first spacer layer. At least one horizontal portion of the second spacer layer is removed while vertical portions of the second spacer layer remain. Conformal deposition of the first and second spacer layers is optionally repeated one or more times. Conformal deposition of the first layer is optionally repeated. Then, one of the first or second spacer layers is removed while substantially leaving the vertical portions of the remaining one of the first or second spacer layers.
摘要翻译：图案化衬底的方法。在衬底上形成牺牲膜，并在其中形成图案。第一间隔层被共形沉积在图案化的牺牲膜上，并且除去第一间隔层的垂直部分的第一间隔层的至少一个水平部分。在图案化的牺牲膜和第一间隔层的剩余部分上共形沉积第二间隔层。除去第二间隔层的至少一个水平部分，同时保留第二间隔层的垂直部分。第一和第二间隔层的共形沉积可选地重复一次或多次。任选地重复第一层的共形沉积。然后，去除第一或第二间隔层中的一个，同时基本上留下第一或第二间隔层中剩余的一个的垂直部分。

18. 发明申请

US20110241085A1 DUAL SIDEWALL SPACER FOR SEAM PROTECTION OF A PATTERNED STRUCTURE 有权
标题翻译：用于保护图案结构的双面隔板
公开(公告)号：US20110241085A1
公开(公告)日：2011-10-06
申请号：US12751891
申请日：2010-03-31
申请人： David L. O'Meara , Anthony Dip , Aelan Mosden , Pao-Hwa Chou , Richard A. Conti
发明人： David L. O'Meara , Anthony Dip , Aelan Mosden , Pao-Hwa Chou , Richard A. Conti
IPC分类号： H01L29/78 , H01L21/311
CPC分类号： H01L29/4983 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A semiconducting device with a dual sidewall spacer and method of forming are provided. The method includes: depositing a first spacer layer over a patterned structure, the first spacer layer having a seam propagating through a thickness of the first spacer layer near an interface region of a surface of the substrate and a sidewall of the patterned structure, etching the first spacer layer to form a residual spacer at the interface region, where the residual spacer coats less than the entirety of the sidewall of the patterned structure, depositing a second spacer layer on the residual spacer and on the sidewall of the patterned structure not coated by the residual spacer, the second spacer layer being seam-free on the seam of the residual spacer, and etching the second spacer layer to form a second spacer coating the residual spacer and coating the sidewall of the patterned structure not coated by the residual spacer.
摘要翻译：提供了具有双侧壁间隔件和成形方法的半导体器件。该方法包括：在图案化结构上沉积第一间隔层，第一间隔层具有在衬底的表面的界面区附近传播穿过第一间隔层的厚度的接缝和图案化结构的侧壁，蚀刻第一间隔层，以在界面区域处形成残留间隔物，其中残余间隔物涂覆小于图案化结构的侧壁的整体，在剩余间隔物上和在图案化结构的侧壁上沉积第二间隔层，所述剩余间隔物，所述第二间隔层在所述残余间隔物的接缝上是无缝的，并且蚀刻所述第二间隔层以形成涂覆所述剩余间隔物并涂覆未被所述残留间隔物涂覆的所述图案化结构的侧壁的第二间隔物。

19. 发明授权

US07509962B2 Method and control system for treating a hafnium-based dielectric processing system 失效
标题翻译：用于处理铪介质处理系统的方法和控制系统
公开(公告)号：US07509962B2
公开(公告)日：2009-03-31
申请号：US11038129
申请日：2005-01-21
申请人： David L. O'Meara , Shingo Maku
发明人： David L. O'Meara , Shingo Maku
IPC分类号： B08B6/00
CPC分类号： C03C17/001 , C03C17/22 , C03C17/23 , C03C2217/228 , C03C2217/258 , C03C2218/31 , C03C2218/33 , C23C16/4405 , Y10S438/905
摘要： A method and control system for treating a hafnium-based dielectric processing system in which a system component of the processing system is exposed to a chlorine-containing gas. A residual hafnium by-product remaining in the processing system after a hafnium removal process is reacted with a chlorine-containing etchant derived from the chlorine-containing gas. A chlorinated hafnium product is volatilized for exhaustion from the processing system. The control system can utilize a computer readable medium to introduce a chlorine-containing gas to the processing system, to adjust at least one of a temperature and a pressure in the processing system to produce from the chlorine-containing gas a chlorine-containing etchant for dissolution of a residual hafnium by-product remaining in the processing system after a hafnium silicate, hafnium oxide, or hafnium oxynitride removal process, and to exhaust a chlorinated hafnium product from the processing system.
摘要翻译：一种用于处理其中处理系统的系统组件暴露于含氯气体的铪基介质处理系统的方法和控制系统。在除去铪之后残留在处理系统中的残余铪副产物与来自含氯气体的含氯蚀刻剂反应。氯化铪产品从处理系统中挥发以用尽。控制系统可利用计算机可读介质向处理系统引入含氯气体，以调节处理系统中的温度和压力中的至少一个，以从含氯气体中产生含氯气体的含氯蚀刻剂在硅酸铪，氧化铪或氮氧化铪去除工艺之后残留在处理系统中的残余铪副产物的溶解，并从处理系统中排出氯化铪产物。

20. 发明授权

US06686633B1 Semiconductor device, memory cell, and processes for forming them 有权
标题翻译：半导体器件，存储单元及其形成工艺
公开(公告)号：US06686633B1
公开(公告)日：2004-02-03
申请号：US09653338
申请日：2000-08-31
申请人： Craig S. Lage , Mousumi Bhat , Yeong-Jyh Tom Lii , Andrew G. Nagy , Larry E. Frisa , Stanley M. Filipiak , David L. O'Meara , T. P. Ong , Michael P. Woo , Terry G. Sparks , Carol M. Gelatos
发明人： Craig S. Lage , Mousumi Bhat , Yeong-Jyh Tom Lii , Andrew G. Nagy , Larry E. Frisa , Stanley M. Filipiak , David L. O'Meara , T. P. Ong , Michael P. Woo , Terry G. Sparks , Carol M. Gelatos
IPC分类号： H01L2976
CPC分类号： H01L27/11 , H01L21/76801 , H01L21/76832 , H01L21/76834 , H01L21/76895 , H01L21/76897 , H01L27/1104
摘要： A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at least three typically seen with SRAM cells. The SRAM cells include many features that allow its dimensions to be scaled to very small dimensions (less than 0.25 microns and possible down to 0.1 microns or even smaller). A unique process integration scheme allows formation of local interconnects (522 and 524), wherein each local interconnect (522, 524) cross couples the inverters of the SRAM and is formed within a single opening (70). Also, interconnect portions (104) of word lines are laterally offset from silicon portions (36) of the same word line, so that the interconnect portions do not interfere with bit line connections.
摘要翻译：半导体器件包括静态随机存取存储器单元的存储器阵列。使用与逻辑型器件更紧密相关联的工艺流程来形成SRAM单元。 SRAM单元使用一个半导体层形成，与至少三个SRAM单元相似。 SRAM单元包括许多特征，允许其尺寸缩放到非常小的尺寸（小于0.25微米，并且可能低至0.1微米甚至更小）。独特的过程集成方案允许形成局部互连（522和524），其中每个局部互连（522,524）交叉耦合SRAM的反相器并形成在单个开口（70）内。此外，字线的互连部分（104）横向偏离同一字线的硅部分（36），使得互连部分不干扰位线连接。

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