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1. 发明授权

US06320784B1 Memory cell and method for programming thereof 有权
标题翻译：存储单元及其编程方法
公开(公告)号：US06320784B1
公开(公告)日：2001-11-20
申请号：US09524916
申请日：2000-03-14
申请人： Ramachandran Muralidhar , Sucharita Madhukar , Bo Jiang , Bruce E. White , Srikanth B. Samavedam , David L. O'Meara , Michael Alan Sadd
发明人： Ramachandran Muralidhar , Sucharita Madhukar , Bo Jiang , Bruce E. White , Srikanth B. Samavedam , David L. O'Meara , Michael Alan Sadd
IPC分类号： G11C1100
CPC分类号： B82Y10/00 , G11C11/56 , G11C11/5671 , G11C16/0416 , G11C2216/08 , H01L29/7887 , H01L29/7888
摘要： A memory cell (101), its method of formation, and operation are disclosed. In accordance with one embodiment, the memory cell (101) comprises a first and second current carrying electrode (12) a control electrode (19), and doped discontinuous storage elements (17). In accordance with an alternative embodiment, memory cell programming is accomplished by removing or adding an average of approximately at least a first charge (30, 62, 64), which can be electron(s) or hole(s) from each of the doped discontinuous storage elements (17).
摘要翻译：公开了一种存储单元（101），其形成方法和操作。根据一个实施例，存储单元（101）包括第一和第二载流电极（12），控制电极（19）和掺杂的非连续存储元件（17）。根据替代实施例，存储器单元编程通过去除或添加大约至少第一电荷（30,62,64）的平均值来实现，所述第一电荷可以是来自掺杂的每一个的电子或空穴不连续存储元件（17）。

2. 发明授权

US06297095B1 Memory device that includes passivated nanoclusters and method for manufacture 有权
标题翻译：包含钝化纳米簇的记忆体装置及其制造方法
公开(公告)号：US06297095B1
公开(公告)日：2001-10-02
申请号：US09596399
申请日：2000-06-16
申请人： Ramachandran Muralidhar , Chitra K. Subramanian , Sucharita Madhukar , Bruce E. White , Michael A. Sadd , Sufi Zafar , David L. O'Meara , Bich-Yen Nguyen
发明人： Ramachandran Muralidhar , Chitra K. Subramanian , Sucharita Madhukar , Bruce E. White , Michael A. Sadd , Sufi Zafar , David L. O'Meara , Bich-Yen Nguyen
IPC分类号： H01L21336
CPC分类号： H01L21/28282 , B82Y10/00 , H01L21/28273 , H01L29/66439 , H01L29/7888
摘要： A semiconductor memory device with a floating gate that includes a plurality of nanoclusters (21) and techniques useful in the manufacturing of such a device are presented. The device is formed by first providing a semiconductor substrate (12) upon which a tunnel dielectric layer (14) is formed. A plurality of nanoclusters (19) is then grown on the tunnel dielectric layer (14). After growth of the nanoclusters (21), a control dielectric layer (20) is formed over the nanoclusters (21). In order to prevent oxidation of the formed nanoclusters (21), the nanoclusters (21) may be encapsulated using various techniques prior to formation of the control dielectric layer (20). A gate electrode (24) is then formed over the control dielectric (20), and portions of the control dielectric, the plurality of nanoclusters, and the gate dielectric that do not underlie the gate electrode are selectively removed. After formation of spacers (35), source and drain regions (32, 34) are then formed by implantation in the semiconductor layer (12) such that a channel region is formed between the source and drain regions (32, 34) underlying the gate electrode (24).
摘要翻译：提出了一种具有浮动栅极的半导体存储器件，其包括多个纳米团簇（21）和用于制造这种器件的技术。该器件通过首先提供其上形成有隧道介电层（14）的半导体衬底（12）形成。然后在隧道介电层（14）上生长多个纳米团簇（19）。在纳米团簇（21）生长之后，在纳米团簇（21）上形成控制电介质层（20）。为了防止形成的纳米团簇（21）的氧化，可以在形成控制电介质层（20）之前使用各种技术将纳米团簇（21）进行封装。然后在控制电介质（20）上形成栅极（24），并且选择性地去除不在栅电极下面的控制电介质，多个纳米团簇和栅极电介质的部分。在形成间隔物（35）之后，然后通过注入在半导体层（12）中形成源极和漏极区域（32,34），使得沟道区域形成在栅极下面的源极和漏极区域（32,34）之间电极（24）。

3. 发明授权

US06344403B1 Memory device and method for manufacture 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US06344403B1
公开(公告)日：2002-02-05
申请号：US09595735
申请日：2000-06-16
申请人： Sucharita Madhukar , Ramachandran Muralidhar , David L. O'Meara , Kristen C. Smith , Bich-Yen Nguyen
发明人： Sucharita Madhukar , Ramachandran Muralidhar , David L. O'Meara , Kristen C. Smith , Bich-Yen Nguyen
IPC分类号： H01L2120
CPC分类号： H01L21/28273 , B82Y10/00 , H01L21/02381 , H01L21/02532 , H01L21/0259 , H01L21/0262 , H01L21/3105 , H01L21/3144 , H01L21/3145 , H01L29/42332 , H01L29/66825
摘要： A semiconductor memory device with a floating gate that includes a plurality of nanoclusters (21) and techniques useful in the manufacturing of such a device are presented. The device is formed by first providing a semiconductor substrate (12) upon which a tunnel dielectric layer (14) is formed. A plurality of nanoclusters (19) is then grown on the tunnel dielectric layer (14). The growth of the nanoclusters (19) may be accomplished using low pressure chemical vapor deposition (LPCVD) or ultra high vacuum chemical vapor deposition (UHCVD) processes. Such growth may be facilitated by formation of a nitrogen-containing layer (502) overlying the tunnel dielectric layer (14). After growth of the nanoclusters (21), a control dielectric layer (20) is formed over the nanoclusters (21). In order to prevent oxidation of the formed nanoclusters (21), the nanoclusters (21) may be encapsulated using various techniques prior to formation of the control dielectric layer (20). A gate electrode (24) is then formed over the control dielectric (20), and portions of the control dielectric, the plurality of nanoclusters, and the gate dielectric that do not underlie the gate electrode are selectively removed. After formation of spacers (35), source and drain regions (32, 34) are then formed by implantation in the semiconductor layer (12) such that a channel region is formed between the source and drain regions (32, 34) underlying the gate electrode (24).
摘要翻译：提出了一种具有浮动栅极的半导体存储器件，其包括多个纳米团簇（21）和用于制造这种器件的技术。该器件通过首先提供其上形成有隧道介电层（14）的半导体衬底（12）形成。然后在隧道介电层（14）上生长多个纳米团簇（19）。纳米团簇（19）的生长可以使用低压化学气相沉积（LPCVD）或超高真空化学气相沉积（UHCVD）工艺来实现。可以通过形成覆盖在隧道介电层（14）上的含氮层（502）来促进这种生长。在纳米团簇（21）生长之后，在纳米团簇（21）上形成控制电介质层（20）。为了防止形成的纳米团簇（21）的氧化，可以在形成控制电介质层（20）之前使用各种技术将纳米团簇（21）进行封装。然后在控制电介质（20）上形成栅极（24），并且选择性地去除不在栅电极下面的控制电介质，多个纳米团簇和栅极电介质的部分。在形成间隔物（35）之后，然后通过注入在半导体层（12）中形成源极和漏极区域（32,34），使得沟道区域形成在栅极下面的源极和漏极区域（32,34）之间电极（24）。

4. 发明授权

US06307782B1 Process for operating a semiconductor device 有权
标题翻译：用于操作半导体器件的工艺
公开(公告)号：US06307782B1
公开(公告)日：2001-10-23
申请号：US09542017
申请日：2000-04-03
申请人： Michael Alan Sadd , Bruce E. White , Ramachandran Muralidhar
发明人： Michael Alan Sadd , Bruce E. White , Ramachandran Muralidhar
IPC分类号： G11C1307
CPC分类号： B82Y10/00 , G11C16/0416 , G11C16/10 , G11C2216/06
摘要： Programmable cells (22, 24, 26, 28) may have discontinuous storage elements (228, 248, 268, 288) as opposed to a continuous floating gate. Each cell further includes first and second current carry electrodes (222, 226, 242, 246, 262, 266, 282, 286) and a control gate electrode (224, 244, 264, 284). In one embodiment, potentials for programming can be selected to program a programmable cell relatively quickly without the need for relatively high potentials. Alternatively, programming can be achieved by flowing current in one direction and then in the opposite direction. In some embodiments, time-variant signals can used during an operation. Embodiments of the present invention can be used with different types of programmable cells including those used in memory arrays and in field programmable gate arrays.
摘要翻译：可编程单元（22,24,26,28）可以具有与连续浮动栅极相对的不连续存储元件（228,248,268,288）。每个单元还包括第一和第二电流携带电极（222,226,242,246,262,266,282,286）和控制栅电极（224,244,264,284）。在一个实施例中，可以选择用于编程的电位来相对快速地编程可编程单元，而不需要相对高的电位。或者，可以通过在一个方向上流动电流然后在相反方向上流动来实现编程。在一些实施例中，可以在操作期间使用时变信号。本发明的实施例可以与不同类型的可编程单元一起使用，包括在存储器阵列和现场可编程门阵列中使用的可编程单元。

5. 发明授权

US06172905B2 Method of operating a semiconductor device 失效
公开(公告)号：US06172905B2
公开(公告)日：2001-01-09
申请号：US09495354
申请日：2000-02-01
申请人： Bruce E. White , Bo Jiang , Ramachandran Muralidhar
发明人： Bruce E. White , Bo Jiang , Ramachandran Muralidhar
IPC分类号： G11C1604
CPC分类号： G11C16/0475 , G11C11/5621 , G11C11/5628 , G11C11/5671 , G11C16/0458 , G11C16/10 , G11C16/3418 , H01L29/7887
摘要： A method of operating a semiconductor device that includes a first memory cell with discontinuous storage elements or dots (108) in lieu of a conventional floating gate can be programmed to at least one of three different states. The different states are possible because the read current for the memory cell is different when the dots are programmed near the source region or near the drain region. Embodiments may use two different potentials for power supplies or three different potentials. The two-potential embodiment simplifies the design, whereas the three-potential embodiment has a reduced risk of disturb problems in adjacent unselected memory cells (100B, 100C, and 100D).

6. 发明授权

US06330184B1 Method of operating a semiconductor device 有权
标题翻译：操作半导体器件的方法
公开(公告)号：US06330184B1
公开(公告)日：2001-12-11
申请号：US09659105
申请日：2000-09-11
申请人： Bruce E. White , Bo Jiang , Ramachandran Muralidhar
发明人： Bruce E. White , Bo Jiang , Ramachandran Muralidhar
IPC分类号： G11C1604
CPC分类号： G11C16/0475 , G11C11/5621 , G11C11/5628 , G11C11/5671 , G11C16/0458 , G11C16/10 , G11C16/3418 , H01L29/7887
摘要： A method of operating a semiconductor device that includes a first memory cell with discontinuous storage elements or dots (108) in lieu of a conventional floating gate can be programmed to at least one of three different states. The different states are possible because the read current for the memory cell is different when the dots are programmed near the source region or near the drain region. Embodiments may use two different potentials for power supplies or three different potentials. The two-potential embodiment simplifies the design, whereas the three-potential embodiment has a reduced risk of disturb problems in adjacent unselected memory cells (100B, 100C, and 100D).
摘要翻译：一种操作包括具有不连续存储元件的第一存储单元或代替常规浮动栅极的点的半导体器件的方法可被编程为三种不同状态中的至少一种。不同的状态是可能的，因为当点被编程在源极区域附近或靠近漏极区域时，存储器单元的读取电流是不同的。实施例可以使用两种不同的电源或三种不同的电位。双电位实施例简化了设计，而三电位实施例降低了相邻未选择的存储单元（100B，100C和100D）中的干扰问题的风险。

7. 发明授权

US06413819B1 Memory device and method for using prefabricated isolated storage elements 有权
标题翻译：使用预制隔离存储元件的存储器件和方法
公开(公告)号：US06413819B1
公开(公告)日：2002-07-02
申请号：US09595821
申请日：2000-06-16
申请人： Sufi Zafar , Ramachandran Muralidhar , Bich-Yen Nguyen , Sucharita Madhukar , Daniel T. Pham , Michael A. Sadd , Chitra K. Subramanian
发明人： Sufi Zafar , Ramachandran Muralidhar , Bich-Yen Nguyen , Sucharita Madhukar , Daniel T. Pham , Michael A. Sadd , Chitra K. Subramanian
IPC分类号： H01L21336
CPC分类号： B82Y10/00 , H01L21/28273 , H01L29/7883 , H01L29/7888
摘要： A semiconductor device that includes a floating gate made up of a plurality of pre-formed isolated storage elements (18) and a method for making such a device is presented. The device is formed by first providing a semiconductor layer (12) upon which a first gate insulator (14) is formed. A plurality of pre-fabricated isolated storage elements (18) is then deposited on the first gate insulator (14). This deposition step may be accomplished by immersion in a colloidal solution (16) that includes a solvent and pre-fabricated isolated storage elements (18). Once deposited, the solvent of the solution (16) can be removed, leaving the pre-fabricated isolated storage elements (18) deposited on the first gate insulator (14). After depositing the pre-fabricated isolated storage elements (18), a second gate insulator (20) is formed over the pre-fabricated isolated storage elements (18). A gate electrode (24) is then formed over the second gate insulator (20), and portions the first and second gate insulators and the plurality of pre-fabricated isolated storage elements that do not underlie the gate electrode are selectively removed. A source region (32) and a drain region (34) are then formed in the semiconductor layer (12) such that a channel region is formed between underlying the gate electrode (24).
摘要翻译：提供了一种半导体器件，其包括由多个预先形成的隔离存储元件（18）构成的浮动栅极和用于制造这种器件的方法。该器件通过首先提供形成第一栅极绝缘体（14）的半导体层（12）形成。然后，多个预制隔离存储元件（18）沉积在第一栅极绝缘体（14）上。该沉积步骤可以通过浸入包括溶剂和预制隔离存储元件（18）的胶体溶液（16）中来实现。一旦沉积，可以除去溶液（16）的溶剂，留下沉积在第一栅极绝缘体（14）上的预制隔离存储元件（18）。在沉积预制隔离存储元件（18）之后，在预制隔离存储元件（18）上形成第二栅极绝缘体（20）。然后，在第二栅极绝缘体（20）之上形成栅电极（24），并且选择性地去除不在栅电极下面的第一和第二栅极绝缘体和多个预制隔离存储元件的部分。然后在半导体层（12）中形成源极区（32）和漏极区（34），使得在栅电极（24）下方形成沟道区。

8. 发明申请

US20080121966A1 Nanocrystal non-volatile memory cell and method therefor 有权
标题翻译：纳米晶体非挥发性记忆体及其方法
公开(公告)号：US20080121966A1
公开(公告)日：2008-05-29
申请号：US11530053
申请日：2006-09-08
申请人： Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Bruce E. White
发明人： Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Bruce E. White
IPC分类号： H01L29/78 , H01L21/3205
CPC分类号： H01L29/42332 , B82Y10/00 , H01L21/28273 , H01L29/513 , H01L29/7881 , Y10S977/773
摘要： A method of forming a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, thermally oxidizing the plurality of discrete storage elements to form a second dielectrics over the plurality of discrete storage elements, and forming a gate electrode over the second dielectric layer, wherein a significant portion of the gate electrode is between pairs of the plurality of discrete storage elements. In one embodiment, portions of the gate electrode is in the spaces between the discrete storage elements and extends to more than half of the depth of the spaces.
摘要翻译：一种形成半导体器件的方法包括在半导体衬底上形成第一电介质层，在第一介电层上形成多个离散存储元件，热氧化多个离散的存储元件，以在多个离散存储器上形成第二电介质元件，并且在所述第二介电层上形成栅电极，其中所述栅电极的重要部分位于所述多个离散存储元件的对之间。在一个实施例中，栅电极的部分位于离散存储元件之间的空间中并且延伸到空间深度的一半以上。

9. 发明授权

US07800164B2 Nanocrystal non-volatile memory cell and method therefor 有权
标题翻译：纳米晶体非挥发性记忆体及其方法
公开(公告)号：US07800164B2
公开(公告)日：2010-09-21
申请号：US12397849
申请日：2009-03-04
申请人： Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Bruce E. White
发明人： Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Bruce E. White
IPC分类号： H01L29/792
CPC分类号： H01L29/42332 , B82Y10/00 , H01L21/28273 , H01L29/513 , H01L29/7881 , Y10S977/773
摘要： A method of forming a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, thermally oxidizing the plurality of discrete storage elements to form a second dielectrics over the plurality of discrete storage elements, and forming a gate electrode over the second dielectric layer, wherein a significant portion of the gate electrode is between pairs of the plurality of discrete storage elements. In one embodiment, portions of the gate electrode is in the spaces between the discrete storage elements and extends to more than half of the depth of the spaces.
摘要翻译：一种形成半导体器件的方法包括在半导体衬底上形成第一电介质层，在第一介电层上形成多个离散存储元件，热氧化多个离散的存储元件，以在多个离散存储器上形成第二电介质元件，并且在所述第二介电层上形成栅电极，其中所述栅电极的重要部分位于所述多个离散存储元件的对之间。在一个实施例中，栅电极的部分位于离散存储元件之间的空间中并且延伸到空间深度的一半以上。

10. 发明授权

US07820491B2 Light erasable memory and method therefor 有权
标题翻译：光可擦除记忆及其方法
公开(公告)号：US07820491B2
公开(公告)日：2010-10-26
申请号：US11620075
申请日：2007-01-05
申请人： Rajesh A. Rao , Leo Mathew , Ramachandran Muralidhar , Bruce E. White
发明人： Rajesh A. Rao , Leo Mathew , Ramachandran Muralidhar , Bruce E. White
IPC分类号： H01L21/82 , G11C16/04
CPC分类号： H01L27/105 , H01L21/84 , H01L27/112 , H01L27/11206 , H01L27/11517 , H01L27/1203 , H01L27/15 , H01L29/66825 , H01L29/788
摘要： A semiconductor device has a semiconductor substrate that in turn has a top semiconductor layer portion and a major supporting portion under the top semiconductor layer portion. An interconnect layer is over the semiconductor layer. A memory array is in a portion of the top semiconductor layer portion and a portion of the interconnect layer. The memory is erased by removing at least a portion of the major supporting portion and, after the step of removing, applying light to the memory array from a side opposite the interconnect layer. The result is that the memory array receives light from the backside and is erased.
摘要翻译：半导体器件具有半导体衬底，其又具有顶部半导体层部分和顶部半导体层部分下方的主要支撑部分。互连层在半导体层之上。存储器阵列位于顶部半导体层部分和互连层的一部分中。通过去除主要支撑部分的至少一部分并且在移除步骤之后，从与互连层相对的一侧将光施加到存储器阵列来擦除存储器。结果是存储器阵列从背面接收光并被擦除。

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