专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US07611589B2 Methods of spin-on wafer cleaning 有权
标题翻译：旋转晶圆清洗方法
公开(公告)号：US07611589B2
公开(公告)日：2009-11-03
申请号：US11072114
申请日：2005-03-04
申请人： Jun Wu , Dong-Xuan Lu , Shih-Chi Lin , Wen-Long Lee , Yi-An Jian , Guang-Cheng Wang , Shiu-Ko JangJian , Chyi-Tsong Ni , Szu-An Wu , Ying-Lang Wang
发明人： Jun Wu , Dong-Xuan Lu , Shih-Chi Lin , Wen-Long Lee , Yi-An Jian , Guang-Cheng Wang , Shiu-Ko JangJian , Chyi-Tsong Ni , Szu-An Wu , Ying-Lang Wang
IPC分类号： B08B3/02 , B08B1/04
CPC分类号： B08B1/04 , B08B3/02 , H01L21/67051
摘要： A method for spin-on wafer cleaning. The method comprises controlling spin speed and vertical water jet pressure. The vertical jet pressure and the spin speed are substantially maintained in inverse proportion. Wafer spin speed is between 50 to 1200 rpm. Vertical wafer jet pressure is between 0.05 to 100 KPa.
摘要翻译：旋转晶片清洗的方法。该方法包括控制旋转速度和垂直喷水压力。垂直喷射压力和旋转速度基本保持成反比例。晶圆转速在50至1200rpm之间。垂直晶片喷射压力为0.05至100KPa。

12. 发明授权

US06479098B1 Method to solve particle performance of FSG layer by using UFU season film for FSG process 有权
标题翻译：通过使用UFU季膜对FSG过程解决FSG层的粒子性能的方法
公开(公告)号：US06479098B1
公开(公告)日：2002-11-12
申请号：US09747135
申请日：2000-12-26
申请人： Ming-Hwa Yoo , Yi-Lung Cheng , Szu-An Wu , Ying-Lang Wang
发明人： Ming-Hwa Yoo , Yi-Lung Cheng , Szu-An Wu , Ying-Lang Wang
IPC分类号： C23C1640
CPC分类号： H01J37/32477 , C23C16/4404 , Y10T428/2495 , Y10T428/265
摘要： A method for reducing contaminants in a processing chamber 10 having chamber plasma processing region components comprising the following steps. The chamber plasma processing region components are cleaned. The chamber is then seasoned as follows. A first USG layer is formed over the chamber plasma processing region components. An FSG layer is formed over the first USG layer. A second USG layer is formed over the FSG layer. Wherein the USG, FSG, and second USG layers comprise a UFU season film. A UFU season film coating the chamber plasma processing region components of a processing chamber comprises: an inner USG layer over the chamber plasma processing region components; an FSG layer over the inner USG layer; and an outer USG layer over the FSG layer.
摘要翻译：一种用于减少具有室等离子体处理区域部件的处理室10中的污染物的方法，包括以下步骤。腔室等离子体处理区域部件被清洁。然后如下调节室。在室等离子体处理区域部件上形成第一USG层。在第一USG层上形成FSG层。在FSG层上形成第二个USG层。其中USG，FSG和第二USG层包括UFU季电影。 UFU季涂膜处理室的室等离子体处理区域部件包括：室上的内部USG层等离子体处理区域部件; 内部USG层上的FSG层; 以及FSG层上的外部USG层。

13. 发明授权

US06436791B1 Method of manufacturing a very deep STI (shallow trench isolation) 有权
标题翻译：制造非常深的STI（浅沟槽隔离）的方法
公开(公告)号：US06436791B1
公开(公告)日：2002-08-20
申请号：US09880259
申请日：2001-06-14
申请人： Shih-Chi Lin , Szu-An Wu , Ying-Lang Wang , Guey-Bao Huang
发明人： Shih-Chi Lin , Szu-An Wu , Ying-Lang Wang , Guey-Bao Huang
IPC分类号： H01L21302
CPC分类号： H01L21/76224
摘要： A method of forming a shallow trench isolation structure comprising the following steps. A substrate having an upper surface is provided. A pad oxide layer is formed upon the substrate. A nitride layer is formed over the pad oxide layer. The nitride layer having an upper surface. A trench is formed by etching the nitride layer, pad oxide layer and a portion of the substrate. The trench having a bottom and side walls. An oxide film is deposited upon the etched nitride layer surface, and the bottom and side walls of trench. The oxide film is removed from over the etched nitride layer surface, and the bottom of the trench to expose a portion of substrate within the trench. The removal of oxide film leaving oxide spacers over the trench side walls. Epitaxial silicon is selectively deposited over the exposed portion of substrate, filling the trench. A thermal oxide layer is formed over the epitaxial silicon, annealing the interface between the epitaxial silicon and the oxide spacers. The etched nitride layer and the oxide layer from over the etched substrate; and a portion of the oxide spacers extending above the surface of the etched substrate are removed, whereby the shallow trench isolation structure is formed within the trench.
摘要翻译：一种形成浅沟槽隔离结构的方法，包括以下步骤。提供具有上表面的基板。衬底氧化层形成在衬底上。在衬垫氧化物层上形成氮化物层。氮化物层具有上表面。通过蚀刻氮化物层，衬垫氧化物层和衬底的一部分来形成沟槽。沟槽具有底部和侧壁。在蚀刻的氮化物层表面和沟槽的底部和侧壁上沉积氧化物膜。从蚀刻的氮化物层表面上方的氧化膜和沟槽的底部去除氧化膜，以露出沟槽内的衬底的一部分。去除在沟槽侧壁上留下氧化物间隔物的氧化物膜。外延硅被选择性地沉积在衬底的暴露部分上，填充沟槽。在外延硅上形成热氧化层，退火外延硅与氧化物间隔物之间的界面。蚀刻的氮化物层和来自蚀刻的衬底上的氧化物层; 并且去除在蚀刻的衬底的表面上方延伸的氧化物间隔物的一部分，由此在沟槽内形成浅沟槽隔离结构。

14. 发明授权

US09224773B2 Metal shielding layer in backside illumination image sensor chips and methods for forming the same 有权
标题翻译：背面照明图像传感器芯片中的金属屏蔽层及其形成方法
公开(公告)号：US09224773B2
公开(公告)日：2015-12-29
申请号：US13420279
申请日：2012-03-14
申请人： Shih-Chieh Chang , Jian-Shin Tsai , Chih-Chang Huang , Ing-Ju Lee , Ching-Yao Sun , Jyun-Ru Wu , Ching-Che Huang , Szu-An Wu , Ying-Lang Wang
发明人： Shih-Chieh Chang , Jian-Shin Tsai , Chih-Chang Huang , Ing-Ju Lee , Ching-Yao Sun , Jyun-Ru Wu , Ching-Che Huang , Szu-An Wu , Ying-Lang Wang
IPC分类号： H01L27/146
CPC分类号： H01L27/1464 , H01L27/1462 , H01L27/14623 , H01L27/14636 , H01L27/14643 , H01L27/14683 , H01L27/14685
摘要： A device includes a semiconductor substrate having a front side and a backside. A photo-sensitive device is disposed at a surface of the semiconductor substrate, wherein the photo-sensitive device is configured to receive a light signal from the backside of the semiconductor substrate, and convert the light signal to an electrical signal. An amorphous-like adhesion layer is disposed on the backside of the semiconductor substrate. The amorphous-like adhesion layer includes a compound of nitrogen and a metal. A metal shielding layer is disposed on the backside of the semiconductor substrate and contacting the amorphous-like adhesion layer.
摘要翻译：一种器件包括具有正面和背面的半导体衬底。光敏器件设置在半导体衬底的表面处，其中光敏器件被配置为从半导体衬底的背面接收光信号，并将光信号转换为电信号。在半导体衬底的背面设有非晶态粘接层。非晶态粘合层包括氮和金属的化合物。金属屏蔽层设置在半导体衬底的背面并与非晶态粘合层接触。

15. 发明申请

US20060196526A1 Methods of spin-on wafer cleaning 有权
公开(公告)号：US20060196526A1
公开(公告)日：2006-09-07
申请号：US11072114
申请日：2005-03-04
申请人： Jun Wu , Dong-Xuan Lu , Shih-Chi Lin , Wen-Long Lee , Yi-An Jian , Guang-Cheng Wang , Shiu-Ko JangJian , Chyi-Tsong Ni , Szu-An Wu , Ying-Lang Wang
发明人： Jun Wu , Dong-Xuan Lu , Shih-Chi Lin , Wen-Long Lee , Yi-An Jian , Guang-Cheng Wang , Shiu-Ko JangJian , Chyi-Tsong Ni , Szu-An Wu , Ying-Lang Wang
IPC分类号： C23G1/00 , B08B7/00 , B08B3/00
CPC分类号： B08B1/04 , B08B3/02 , H01L21/67051
摘要： A method for spin-on wafer cleaning. The method comprises controlling spin speed and vertical water jet pressure. The vertical jet pressure and the spin speed are substantially maintained in inverse proportion. Wafer spin speed is between 50 to 1200 rpm. Vertical wafer jet pressure is between 0.05 to 100 KPa.

16. 发明授权

US06281146B1 Plasma enhanced chemical vapor deposition (PECVD) method for forming microelectronic layer with enhanced film thickness uniformity 有权
标题翻译：用于形成具有增强的膜厚度均匀性的微电子层的等离子体增强化学气相沉积（PECVD）方法
公开(公告)号：US06281146B1
公开(公告)日：2001-08-28
申请号：US09396517
申请日：1999-09-15
申请人： Ying-Lang Wang , Hui-Ling Wang , Jowei Dun , Szu-An Wu
发明人： Ying-Lang Wang , Hui-Ling Wang , Jowei Dun , Szu-An Wu
IPC分类号： H01L2131
CPC分类号： H01L21/02164 , C23C16/402 , C23C16/5096 , H01L21/02211 , H01L21/02274 , H01L21/31612
摘要： A method for forming a microelectronic layer. There is first provided a substrate. There is then formed over the substrate the microelectronic layer while employing a plasma enhanced chemical vapor deposition (PECVD) method employing a source material gas and a carrier gas, wherein there is employed a sufficiently low plasma power, a sufficiently low source material gas:carrier gas flow rate ratio and a sufficiently high carrier gas atomic mass such that the microelectronic layer is formed with enhanced film thickness uniformity. The method may be employed for forming ion implant screen layers, such as silicon oxide ion implant screen layers, with enhanced film thickness uniformity.
摘要翻译：一种形成微电子层的方法。首先提供基板。然后在采用使用源材料气体和载气的等离子体增强化学气相沉积（PECVD）方法的基板上形成微电子层，其中采用足够低的等离子体功率，足够低的源材料气体：载体气体流量比和足够高的载气原子质量，使得微电子层形成为具有增强的膜厚均匀性。该方法可用于形成具有增强的膜厚度均匀性的离子注入屏幕层，例如氧化硅离子注入屏幕层。

17. 发明授权

US08470390B2 Oxidation-free copper metallization process using in-situ baking 有权
标题翻译：无氧化铜金属化工艺采用原位烘烤
公开(公告)号：US08470390B2
公开(公告)日：2013-06-25
申请号：US11972785
申请日：2008-01-11
申请人： Yu-Sheng Wang , Shih-Ho Lin , Kei-Wei Chen , Szu-An Wu , Ying-Lang Wang
发明人： Yu-Sheng Wang , Shih-Ho Lin , Kei-Wei Chen , Szu-An Wu , Ying-Lang Wang
IPC分类号： B05D5/12 , C23C14/00
CPC分类号： H01L21/76814 , H01L21/02063 , H01L21/76828 , H01L21/76843
摘要： A method of forming an integrated circuit structure includes providing a substrate; forming a metal feature over the substrate; forming a dielectric layer over the metal feature; and forming an opening in the dielectric layer. At least a portion of the metal feature is exposed through the opening. An oxide layer is accordingly formed on an exposed portion of the metal feature. The method further includes, in a production tool having a vacuum environment, performing an oxide-removal process to remove the oxide layer. Between the step of forming the opening and the oxide-removal process, no additional oxide-removal process is performed to the metal feature outside the production tool. The method further includes, in the production tool, forming a diffusion barrier layer in the opening, and forming a seed layer on the diffusion barrier layer.
摘要翻译：形成集成电路结构的方法包括提供基板; 在衬底上形成金属特征; 在金属特征上形成介电层; 并在介电层中形成开口。金属特征的至少一部分通过开口露出。相应地，在金属特征的暴露部分上形成氧化物层。该方法还包括在具有真空环境的生产工具中进行氧化物去除工艺以去除氧化物层。在形成开口的步骤和氧化物去除工艺之间，对生产工具外部的金属特征没有进行额外的氧化物去除处理。该方法还包括在生产工具中在开口中形成扩散阻挡层，并在扩散阻挡层上形成种子层。

18. 发明申请

US20090181164A1 Oxidation-Free Copper Metallization Process Using In-situ Baking 有权
标题翻译：使用原位烘烤的无氧铜金属化工艺
公开(公告)号：US20090181164A1
公开(公告)日：2009-07-16
申请号：US11972785
申请日：2008-01-11
申请人： Yu-Sheng Wang , Shih-Ho Lin , Kei-Wei Chen , Szu-An Wu , Ying-Lang Wang
发明人： Yu-Sheng Wang , Shih-Ho Lin , Kei-Wei Chen , Szu-An Wu , Ying-Lang Wang
IPC分类号： H05K3/46
CPC分类号： H01L21/76814 , H01L21/02063 , H01L21/76828 , H01L21/76843
摘要： A method of forming an integrated circuit structure includes providing a substrate; forming a metal feature over the substrate; forming a dielectric layer over the metal feature; and forming an opening in the dielectric layer. At least a portion of the metal feature is exposed through the opening. An oxide layer is accordingly formed on an exposed portion of the metal feature. The method further includes, in a production tool having a vacuum environment, performing an oxide-removal process to remove the oxide layer. Between the step of forming the opening and the oxide-removal process, no additional oxide-removal process is performed to the metal feature outside the production tool. The method further includes, in the production tool, forming a diffusion barrier layer in the opening, and forming a seed layer on the diffusion barrier layer
摘要翻译：形成集成电路结构的方法包括提供基板; 在衬底上形成金属特征; 在金属特征上形成介电层; 并在介电层中形成开口。金属特征的至少一部分通过开口露出。相应地，在金属特征的暴露部分上形成氧化物层。该方法还包括在具有真空环境的生产工具中进行氧化物去除工艺以去除氧化物层。在形成开口的步骤和氧化物去除工艺之间，对生产工具外部的金属特征没有进行额外的氧化物去除处理。该方法还包括在生产工具中在开口中形成扩散阻挡层，并在扩散阻挡层上形成种子层

19. 发明授权

US6136680A Methods to improve copper-fluorinated silica glass interconnects 有权
标题翻译：改善铜氟化石英玻璃互连的方法
公开(公告)号：US6136680A
公开(公告)日：2000-10-24
申请号：US489498
申请日：2000-01-21
申请人： Jane-Bai Lai , Chung-Shi Liu , Tien-I Bao , Syun-Ming Jang , Chung-Long Chang , Hui-Ling Wang , Szu-An Wu , Wen-Kung Cheng , Chun-Ching Tsan , Ying-Lang Wang
发明人： Jane-Bai Lai , Chung-Shi Liu , Tien-I Bao , Syun-Ming Jang , Chung-Long Chang , Hui-Ling Wang , Szu-An Wu , Wen-Kung Cheng , Chun-Ching Tsan , Ying-Lang Wang
IPC分类号： H01L21/02 , H01L21/3105 , H01L21/321 , H01L21/768 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/76825 , H01L21/02074 , H01L21/3105 , H01L21/3212 , H01L21/76826 , H01L21/76834 , H01L21/7684 , H01L21/76883
摘要： A method of forming an interconnect, comprising the following steps. A semiconductor structure is provided that has an exposed first metal contact and a dielectric layer formed thereover. An FSG layer having a predetermined thickness is then formed over the dielectric layer. A trench, having a predetermined width, is formed within the FSG layer and the dielectric layer exposing the first metal contact. A barrier layer, having a predetermined thickness, may be formed over the FSG layer and lining the trench side walls and bottom. A metal, preferably copper, is then deposited on the barrier layer to form a copper layer, having a predetermined thickness, over said barrier layer covered FSG layer, filling the lined trench and blanket filling the barrier layer covered FSG layer. The copper layer, and the barrier layer on said upper surface of said FSG layer, are planarized, exposing the upper surface of the FSG layer and forming a planarized copper filled trench. The FSG layer and planarized copper filled trench are then processed by either: (1) annealing from about 400 to 450.degree. C. for about one hour, then either NH.sub.3 or H.sub.2 plasma treating; or (2) Ar.sup.+ sputtering to ion implant Ar.sup.+ to a depth of less than about 300 .ANG. in the fluorinated silica glass layer, whereby any formed Si--OH bonds and copper oxide (metal oxide) are removed. A dielectric cap layer, having a predetermined thickness, is then formed over the processed FSG layer and the planarized copper filled trench.
摘要翻译：一种形成互连的方法，包括以下步骤。提供一种半导体结构，其具有暴露的第一金属触点和形成在其上的电介质层。然后在电介质层上形成具有预定厚度的FSG层。具有预定宽度的沟槽形成在FSG层内，并且介电层露出第一金属接触。具有预定厚度的阻挡层可以形成在FSG层之上并且衬在沟槽侧壁和底部。然后将一种金属，优选铜沉积在阻挡层上，以形成具有预定厚度的铜层，超过所述阻挡层覆盖的FSG层，填充衬里的沟槽和覆盖填充阻挡层覆盖的FSG层的毯子。所述FSG层的所述上表面上的铜层和阻挡层被平坦化，暴露出FSG层的上表面并形成平坦化的铜填充沟槽。然后通过以下步骤之一处理FSG层和平坦化的铜填充沟槽：（1）从约400至450℃的退火约1小时，然后进行NH 3或H 2等离子体处理; 或者（2）在氟化石英玻璃层中，离子注入Ar +溅射至小于约300的深度，由此除去任何形成的Si-OH键和氧化铜（金属氧化物）。然后在经处理的FSG层和平坦化的铜填充沟槽上形成具有预定厚度的电介质盖层。

20. 发明授权

US08847286B2 Image sensor and method of manufacturing 有权
标题翻译：图像传感器及制造方法
公开(公告)号：US08847286B2
公开(公告)日：2014-09-30
申请号：US13349221
申请日：2012-01-12
申请人： Shiu-Ko Jangjian , Kei-Wei Chen , Szu-An Wu , Ying-Lang Wang
发明人： Shiu-Ko Jangjian , Kei-Wei Chen , Szu-An Wu , Ying-Lang Wang
IPC分类号： H01L27/148
CPC分类号： H01L27/14621 , H01L27/14623 , H01L27/1464
摘要： An image sensor includes a substrate having opposite first and second sides, a multilayer structure on the first side of the substrate, and a photo-sensitive element on the second side of the substrate. The photo-sensitive element is configured to receive light that is incident upon the first side and transmitted through the multilayer structure and the substrate. The multilayer structure includes first and second light transmitting layers. The first light transmitting layer is sandwiched between the substrate and the second light transmitting layer. The first light transmitting layer has a refractive index that is from 60% to 90% of a refractive index of the substrate. The second light transmitting layer has a refractive index that is lower than the refractive index of the first light transmitting layer and is from 40% to 70% of the refractive index of the substrate.
摘要翻译：图像传感器包括具有相对的第一和第二侧的基板，在基板的第一侧上的多层结构和在基板的第二侧上的感光元件。光敏元件被配置为接收入射在第一侧并透过多层结构和基板的光。多层结构包括第一和第二透光层。第一透光层夹在基板和第二透光层之间。第一透光层的折射率为基板折射率的60％至90％。第二透光层的折射率低于第一透光层的折射率，为基板的折射率的40％〜70％。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式