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1. 发明授权

US07208415B2 Plasma treatment method for electromigration reduction 有权
标题翻译：用于电迁移减少的等离子体处理方法
公开(公告)号：US07208415B2
公开(公告)日：2007-04-24
申请号：US10882069
申请日：2004-06-30
申请人： Jane-Bai Lai , Yi-Lung Cheng
发明人： Jane-Bai Lai , Yi-Lung Cheng
IPC分类号： H01L21/44
CPC分类号： H01L21/321 , H01L21/76877
摘要： A plasma treatment method which is capable of extending the MTF (mean-time-to-failure) of metal interconnects fabricated on a semiconductor wafer substrate, is disclosed. The invention includes providing a trench typically in a dielectric layer on a substrate; depositing a metal in the trench; and exposing the metal to a nitrogen-based plasma. The plasma-treatment step accelerates grain growth and re-orients the grains in the metal to a closely-packed crystal orientation texture which approaches or approximates the crystal orientation texture of copper.
摘要翻译：公开了一种等离子体处理方法，其能够延长制造在半导体晶片衬底上的金属互连的MTF（平均故障时间）。本发明包括提供通常在基底上的电介质层中的沟槽; 在沟槽中沉积金属; 并将金属暴露于氮基等离子体。等离子体处理步骤加速晶粒生长并将金属中的晶粒重新定位成接近或接近铜的<111>晶体取向纹理的紧密堆积的晶体取向纹理。

2. 发明申请

US20060003486A1 Plasma treatment method for electromigration reduction 有权
标题翻译：用于电迁移减少的等离子体处理方法
公开(公告)号：US20060003486A1
公开(公告)日：2006-01-05
申请号：US10882069
申请日：2004-06-30
申请人： Jane-Bai Lai , Yi-Lung Cheng
发明人： Jane-Bai Lai , Yi-Lung Cheng
IPC分类号： H01L21/00
CPC分类号： H01L21/321 , H01L21/76877
摘要： A plasma treatment method which is capable of extending the MTF (mean-time-to-failure) of metal interconnects fabricated on a semiconductor wafer substrate, is disclosed. The invention includes providing a trench typically in a dielectric layer on a substrate; depositing a metal in the trench; and exposing the metal to a nitrogen-based plasma. The plasma-treatment step accelerates grain growth and re-orients the grains in the metal to a closely-packed crystal orientation texture which approaches or approximates the crystal orientation texture of copper.
摘要翻译：公开了一种等离子体处理方法，其能够延长制造在半导体晶片衬底上的金属互连的MTF（平均故障时间）。本发明包括提供通常在基底上的电介质层中的沟槽; 在沟槽中沉积金属; 并将金属暴露于氮基等离子体。等离子体处理步骤加速晶粒生长并将金属中的晶粒重新定位成接近或接近铜的<111>晶体取向纹理的紧密堆积的晶体取向纹理。

3. 发明授权

US6083829A Use of a low resistivity Cu.sub.3 Ge interlayer as an adhesion promoter between copper and tin layers 失效
标题翻译：使用低电阻率Cu3Ge中间层作为铜和锡层之间的粘合促进剂
公开(公告)号：US6083829A
公开(公告)日：2000-07-04
申请号：US083419
申请日：1998-05-22
申请人： Jane-Bai Lai , Lih-Juann Chen , Chung-Shi Liu , Chen-Hua Douglas Yu
发明人： Jane-Bai Lai , Lih-Juann Chen , Chung-Shi Liu , Chen-Hua Douglas Yu
IPC分类号： C23C16/56 , C23C26/00 , C23C28/00 , H01L21/288 , H01L21/321 , H01L21/768 , H01L23/532 , H01L21/4763
CPC分类号： H01L21/76873 , C23C16/56 , C23C26/00 , C23C28/00 , H01L21/2885 , H01L21/321 , H01L21/76841 , H01L21/76843 , H01L21/76855 , H01L23/53238 , H01L2924/0002
摘要： A method for fabricating a copper interconnect structure, using a low resistivity Cu.sub.3 Ge intermetallic layer, as an adhesive layer, has been developed. Following an in situ, CVD of a titanium nitride barrier layer, a germanium layer, and a copper layer, an anneal procedure is used to form the Cu.sub.3 Ge intermetallic layer, with the intermetallic layer, located between the underlying titanium nitride barrier layer, and the overlying copper layer. The Cu.sub.3 Ge intermetallic layer can also be formed in situ, during deposition, if the deposition temperature exceeds 150.degree. C. Cu.sub.3 Ge layer exhibits a resistivity of about 5E-6 ohm - cm. A second iteration of this invention allows a thick copper layer to be plated on a thin copper seed layer, only on the top surface of a semiconductor substrate. This iteration, also incorporating the low resistivity, Cu.sub.3 Ge intermetallic, and the adhesive layer, prevents copper from being plated on the beveled edge of the semiconductor substrate.
摘要翻译：已经开发了使用低电阻率Cu 3 Ge金属间化合物作为粘合剂层的铜互连结构的制造方法。在原位，氮化钛阻挡层，锗层和铜层的CVD之后，使用退火程序形成Cu 3 Ge金属间化合物层，金属间层位于下面的氮化钛阻挡层和上覆铜层。如果沉积温度超过150℃，Cu3Ge金属间化合物层也可以在沉积过程中原位形成。Cu3Ge层的电阻率约为5E-6欧姆 - 厘米。本发明的第二次迭代允许厚铜层仅在半导体衬底的顶表面上镀覆在薄铜籽晶层上。也包含低电阻率Cu3Ge金属间化合物和粘合剂层的这种迭代防止铜电镀在半导体衬底的斜边上。

4. 发明授权

US06780783B2 Method of wet etching low dielectric constant materials 失效
标题翻译：湿法蚀刻低介电常数材料的方法
公开(公告)号：US06780783B2
公开(公告)日：2004-08-24
申请号：US09941356
申请日：2001-08-29
申请人： Jane-Bai Lai , Pei-Fen Chou
发明人： Jane-Bai Lai , Pei-Fen Chou
IPC分类号： H01L21302
CPC分类号： H01L21/31133
摘要： A method of etching a low dielectric constant material with an aqueous solution of hydrofluoric acid and hydrochloric acid. The etching solution is particularly useful on low dielectric constant materials that are water repulsive or hydrophobic. The weight ratio of hydrofluoric acid to hydrochloric acid in the aqueous solution ranges from 1:3 to 4:1.
摘要翻译：一种用氢氟酸和盐酸水溶液蚀刻低介电常数材料的方法。蚀刻溶液在具有排斥性或疏水性的低介电常数材料上特别有用。水溶液中氢氟酸与盐酸的重量比为1：3〜4：1。

5. 发明授权

US06660655B2 Method and solution for preparing SEM samples for low-K materials 有权
标题翻译：制备低K材料的SEM样品的方法和解决方案
公开(公告)号：US06660655B2
公开(公告)日：2003-12-09
申请号：US10389786
申请日：2003-03-17
申请人： Jane-Bai Lai
发明人： Jane-Bai Lai
IPC分类号： H01L21302
CPC分类号： C23F1/16 , H01L21/31111
摘要： A method and a solution for preparing SEM samples comprising low-K dielectric materials. The process begins by providing a SEM sample comprising low-K dielectric material and silicon oxide material. A solution is formed for preparing (staining and etching) the SEM sample by adding NH4F (s) to a solution comprising CH3COOH having a concentration of about 98% at a ratio of about 1 g NH4F (s):20 ml CH3COOH, then stirring until the NH4F (s) is thoroughly dissolved. Alternatively, the NH4F (s) can be added to a solution comprising HNO3 having a concentration of about 70% and CH3COOH having a concentration of about 98%, with a volume ratio of about 15 ml HNO3:20 ml CH3COOH. The NH4F (s) is added at a ratio of about 1 g NH4F (s):35 ml CH3COOH and HNO3, and stirred until the NH4F (s) is thoroughly dissolved. The SEM sample is then etched in this solution for about 3 seconds, whereby the low-K dielectric material and silicon oxide material have similar etch rates with good selectivity to metals.
摘要翻译：一种制备包含低K电介质材料的SEM样品的方法和解决方案。该方法开始于提供包含低K电介质材料和氧化硅材料的SEM样品。通过以约1g NH4F（20ml）CH 3 COOH的比例，将NH 4 F（s）加入到含有约98％浓度的CH 3 COOH的溶液中，然后搅拌，形成用于制备（染色和蚀刻）SEM样品的溶液直到NH4F完全溶解。或者，可以将NH 4 F加入到浓度为约70％的HNO 3和浓度为约98％的CH 3 COOH，体积比为约15ml HNO 3：20ml CH 3 COOH的溶液中。 NH 4 F以约1g NH 4 F（s）：35ml CH 3 COOH和HNO 3的比例加入，并搅拌直到NH 4 F完全溶解。然后将SEM样品在该溶液中蚀刻约3秒钟，由此低K电介质材料和氧化硅材料具有相似的蚀刻速率并且对金属具有良好的选择性。

6. 发明授权

US6136680A Methods to improve copper-fluorinated silica glass interconnects 有权
标题翻译：改善铜氟化石英玻璃互连的方法
公开(公告)号：US6136680A
公开(公告)日：2000-10-24
申请号：US489498
申请日：2000-01-21
申请人： Jane-Bai Lai , Chung-Shi Liu , Tien-I Bao , Syun-Ming Jang , Chung-Long Chang , Hui-Ling Wang , Szu-An Wu , Wen-Kung Cheng , Chun-Ching Tsan , Ying-Lang Wang
发明人： Jane-Bai Lai , Chung-Shi Liu , Tien-I Bao , Syun-Ming Jang , Chung-Long Chang , Hui-Ling Wang , Szu-An Wu , Wen-Kung Cheng , Chun-Ching Tsan , Ying-Lang Wang
IPC分类号： H01L21/02 , H01L21/3105 , H01L21/321 , H01L21/768 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/76825 , H01L21/02074 , H01L21/3105 , H01L21/3212 , H01L21/76826 , H01L21/76834 , H01L21/7684 , H01L21/76883
摘要： A method of forming an interconnect, comprising the following steps. A semiconductor structure is provided that has an exposed first metal contact and a dielectric layer formed thereover. An FSG layer having a predetermined thickness is then formed over the dielectric layer. A trench, having a predetermined width, is formed within the FSG layer and the dielectric layer exposing the first metal contact. A barrier layer, having a predetermined thickness, may be formed over the FSG layer and lining the trench side walls and bottom. A metal, preferably copper, is then deposited on the barrier layer to form a copper layer, having a predetermined thickness, over said barrier layer covered FSG layer, filling the lined trench and blanket filling the barrier layer covered FSG layer. The copper layer, and the barrier layer on said upper surface of said FSG layer, are planarized, exposing the upper surface of the FSG layer and forming a planarized copper filled trench. The FSG layer and planarized copper filled trench are then processed by either: (1) annealing from about 400 to 450.degree. C. for about one hour, then either NH.sub.3 or H.sub.2 plasma treating; or (2) Ar.sup.+ sputtering to ion implant Ar.sup.+ to a depth of less than about 300 .ANG. in the fluorinated silica glass layer, whereby any formed Si--OH bonds and copper oxide (metal oxide) are removed. A dielectric cap layer, having a predetermined thickness, is then formed over the processed FSG layer and the planarized copper filled trench.
摘要翻译：一种形成互连的方法，包括以下步骤。提供一种半导体结构，其具有暴露的第一金属触点和形成在其上的电介质层。然后在电介质层上形成具有预定厚度的FSG层。具有预定宽度的沟槽形成在FSG层内，并且介电层露出第一金属接触。具有预定厚度的阻挡层可以形成在FSG层之上并且衬在沟槽侧壁和底部。然后将一种金属，优选铜沉积在阻挡层上，以形成具有预定厚度的铜层，超过所述阻挡层覆盖的FSG层，填充衬里的沟槽和覆盖填充阻挡层覆盖的FSG层的毯子。所述FSG层的所述上表面上的铜层和阻挡层被平坦化，暴露出FSG层的上表面并形成平坦化的铜填充沟槽。然后通过以下步骤之一处理FSG层和平坦化的铜填充沟槽：（1）从约400至450℃的退火约1小时，然后进行NH 3或H 2等离子体处理; 或者（2）在氟化石英玻璃层中，离子注入Ar +溅射至小于约300的深度，由此除去任何形成的Si-OH键和氧化铜（金属氧化物）。然后在经处理的FSG层和平坦化的铜填充沟槽上形成具有预定厚度的电介质盖层。

7. 发明授权

US06753259B2 Method of improving the bondability between Au wires and Cu bonding pads 失效
标题翻译：提高Au线和Cu焊盘之间的粘接性的方法
公开(公告)号：US06753259B2
公开(公告)日：2004-06-22
申请号：US09972492
申请日：2001-10-05
申请人： Syun-Ming Jang , Mong-Song Liang , Chen-Hua Yu , Chung-Shi Liu , Jane-Bai Lai
发明人： Syun-Ming Jang , Mong-Song Liang , Chen-Hua Yu , Chung-Shi Liu , Jane-Bai Lai
IPC分类号： H01L21302
CPC分类号： H01L24/05 , H01L23/53238 , H01L24/03 , H01L24/11 , H01L24/45 , H01L24/48 , H01L2224/0401 , H01L2224/04042 , H01L2224/05001 , H01L2224/05006 , H01L2224/05083 , H01L2224/05147 , H01L2224/05624 , H01L2224/05647 , H01L2224/13099 , H01L2224/45124 , H01L2224/45144 , H01L2224/48624 , H01L2224/48647 , H01L2224/48699 , H01L2224/48724 , H01L2224/48747 , H01L2924/01007 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/181 , H01L2924/00014 , H01L2924/00
摘要： Cu, for its rather low resistivity, will be widely used in sub-quarter micron meter ULSI devices. However, it is well known that Cu is easy to be corroded as exposed in air. In packaging of chips the bonding pads making of Cu will thus oxides. In addition, the reaction between Au-ball and Cu pads is very poor. On the other hand, a native AlOx layer, about 3-4 nm in thickness, will form as Al exposes in air; the formed layer is inert and is capable of protecting Al from corrosion. Furthermore, the reaction between Au-ball and Al was very well. Therefore, with the methods of the present invention, Al or AlCu as a glue and protection layer is implemented on Cu bonding pads for successful Au wiring.
摘要翻译：因为其较低的电阻率，铜将被广泛应用于二分之一微米级ULSI器件。然而，众所周知，Cu在空气中容易被腐蚀。在芯片的封装中，由此制成Cu的焊盘将氧化。此外，Au球和Cu垫之间的反应非常差。另一方面，厚度约3-4nm的天然AlOx层将在Al中暴露于空气中形成; 形成的层是惰性的并且能够保护Al免于腐蚀。此外，Au球和Al之间的反应非常好。因此，利用本发明的方法，在用于成功的Au布线的Cu焊盘上实施作为胶水和保护层的Al或AlCu。

8. 发明授权

US6015749A Method to improve adhesion between copper and titanium nitride, for copper interconnect structures, via the use of an ion implantation procedure 失效
标题翻译：通过使用离子注入程序来改善铜互连结构的铜和氮化钛之间的附着力的方法
公开(公告)号：US6015749A
公开(公告)日：2000-01-18
申请号：US72004
申请日：1998-05-04
申请人： Chung-Shi Liu , Chen-Hua Douglas Yu , Jane-Bai Lai , Lih-Juann Chen
发明人： Chung-Shi Liu , Chen-Hua Douglas Yu , Jane-Bai Lai , Lih-Juann Chen
IPC分类号： H01L21/768 , H01L23/532 , H01L21/4763
CPC分类号： H01L21/76873 , H01L21/76843 , H01L21/76855 , H01L21/76858 , H01L21/76859 , H01L21/76877 , H01L23/53238 , H01L2924/0002
摘要： A method for fabricating a copper interconnect structure, using a Cu.sub.3 Ge intermetallic layer, as an adhesive layer, has been developed. Following the deposition of a copper seed layer, an ion implantation procedure is performed, placing germanium ions in a copper seed layer. After deposition of a thick copper layer, an anneal cycle, performed before or after deposition of the thick copper layer, is used to create a Cu.sub.3 Ge intermetallic layer at the interface between a copper seed layer and a titanium nitride barrier layer. A second embodiment of this invention uses a tilted, germanium ion implantation procedure, used to avoid the placement of germanium ions in a copper seed layer, at the bottom of a contact hole, thus avoiding possible implantation damage, to active device regions, exposed in the bottom of the contact hole.
摘要翻译：已经开发了使用Cu 3 Ge金属间化合物作为粘合剂层的铜互连结构的制造方法。在沉积铜籽晶层之后，进行离子注入程序，将锗离子放置在铜籽晶层中。在沉积厚铜层之后，在沉积厚铜层之前或之后执行的退火循环用于在铜籽晶层和氮化钛阻挡层之间的界面处产生Cu 3 Ge金属间化合物层。本发明的第二实施例使用倾斜的锗离子注入程序，用于避免将锗离子放置在铜种子层中，在接触孔的底部，从而避免可能的植入损伤，暴露于有源器件区域接触孔的底部。

9. 发明授权

US06423625B1 Method of improving the bondability between Au wires and Cu bonding pads 有权
标题翻译：提高Au线和Cu焊盘之间的粘接性的方法
公开(公告)号：US06423625B1
公开(公告)日：2002-07-23
申请号：US09385754
申请日：1999-08-30
申请人： Syun-Ming Jang , Mong-Song Liang , Chen-Hua Yu , Chung-Shi Liu , Jane-Bai Lai
发明人： Syun-Ming Jang , Mong-Song Liang , Chen-Hua Yu , Chung-Shi Liu , Jane-Bai Lai
IPC分类号： H01L2160
CPC分类号： H01L24/05 , H01L23/53238 , H01L24/03 , H01L24/11 , H01L24/45 , H01L24/48 , H01L2224/0401 , H01L2224/04042 , H01L2224/05001 , H01L2224/05006 , H01L2224/05083 , H01L2224/05147 , H01L2224/05624 , H01L2224/05647 , H01L2224/13099 , H01L2224/45124 , H01L2224/45144 , H01L2224/48624 , H01L2224/48647 , H01L2224/48699 , H01L2224/48724 , H01L2224/48747 , H01L2924/01007 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/181 , H01L2924/00014 , H01L2924/00
摘要： Cu, for its rather loe resistivity, will be widely used in sub-quarter micron meter ULSI devices. However, it is well known that Cu is easy to be corroded as exposed in air. In packaging of chips the bonding pads making of Cu will thus oxides. In addition, the reaction between Au-ball and Cu pads is very poor. On the other hand, a native AlOx layer, about 3-4 nm in thickness, will form as Al exposes in air; the formed layer is inert and is capable of protecting Al from corrosion. Furthermore, the reaction between Au-ball and Al was very well. Therefore, with the methods of the present invention, Al or AlCu as a glue and protection layer is implemented on Cu bonding pads for successful Au wiring.
摘要翻译：铜，因其相当的电阻率，将广泛应用于二分之一微米级ULSI器件。然而，众所周知，Cu在空气中容易被腐蚀。在芯片的封装中，由此制成Cu的焊盘将氧化。此外，Au球和Cu垫之间的反应非常差。另一方面，厚度约3-4nm的天然AlOx层将在Al中暴露于空气中形成; 形成的层是惰性的并且能够保护Al免于腐蚀。此外，Au球和Al之间的反应非常好。因此，利用本发明的方法，在用于成功的Au布线的Cu焊盘上实施作为胶水和保护层的Al或AlCu。

10. 发明授权

US06399487B1 Method of reducing phase transition temperature by using silicon-germanium alloys 有权
标题翻译：使用硅锗合金降低相变温度的方法
公开(公告)号：US06399487B1
公开(公告)日：2002-06-04
申请号：US09222269
申请日：1998-12-28
申请人： Jane-Bai Lai , Lih-Juan Chen , Chung-Shi Liu , Chen-Hua Yu
发明人： Jane-Bai Lai , Lih-Juan Chen , Chung-Shi Liu , Chen-Hua Yu
IPC分类号： H01L2144
CPC分类号： H01L29/41783 , H01L21/28052 , H01L21/28518 , H01L29/665
摘要： An improved SALICIDE process is described wherein the transformation temperature to a lower resistivity suicide structure is reduced by first coating with a layer of a silicon-germanium alloy prior to the deposition of the titanium layer. Provided there is at least 40 atomic percent of germanium in the alloy a second RTA at a temperature no higher than about 650° C. may be effectively used. The resulting ternary alloy has a resistivity of about 15-20 microhm cm which corresponds to a sheet resistance of about 3-3.5 ohms per square. The ability to achieve low sheet resistance after annealing at such a low temperature becomes increasingly more important as device dimensions decrease since the second RTA becomes increasingly more likely to result in agglomeration of the silicidelayer.
摘要翻译：描述了改进的SALICIDE方法，其中通过在沉积钛层之前首先用一层硅 - 锗合金涂层来降低到较低电阻率硅化物结构的转变温度。如果在合金中存在至少40原子％的锗，则可以有效地使用不高于约650℃的温度的第二RTA。得到的三元合金具有约15-20微米厘米的电阻率，其对应于约3-3.5欧姆/平方的薄层电阻。在这样低的温度下退火之后实现低的薄层电阻的能力变得越来越重要，因为器件尺寸减小，因为第二RTA变得越来越多地导致硅化物层的聚集。

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