专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08470390B2 Oxidation-free copper metallization process using in-situ baking 有权
标题翻译：无氧化铜金属化工艺采用原位烘烤
公开(公告)号：US08470390B2
公开(公告)日：2013-06-25
申请号：US11972785
申请日：2008-01-11
申请人： Yu-Sheng Wang , Shih-Ho Lin , Kei-Wei Chen , Szu-An Wu , Ying-Lang Wang
发明人： Yu-Sheng Wang , Shih-Ho Lin , Kei-Wei Chen , Szu-An Wu , Ying-Lang Wang
IPC分类号： B05D5/12 , C23C14/00
CPC分类号： H01L21/76814 , H01L21/02063 , H01L21/76828 , H01L21/76843
摘要： A method of forming an integrated circuit structure includes providing a substrate; forming a metal feature over the substrate; forming a dielectric layer over the metal feature; and forming an opening in the dielectric layer. At least a portion of the metal feature is exposed through the opening. An oxide layer is accordingly formed on an exposed portion of the metal feature. The method further includes, in a production tool having a vacuum environment, performing an oxide-removal process to remove the oxide layer. Between the step of forming the opening and the oxide-removal process, no additional oxide-removal process is performed to the metal feature outside the production tool. The method further includes, in the production tool, forming a diffusion barrier layer in the opening, and forming a seed layer on the diffusion barrier layer.
摘要翻译：形成集成电路结构的方法包括提供基板; 在衬底上形成金属特征; 在金属特征上形成介电层; 并在介电层中形成开口。金属特征的至少一部分通过开口露出。相应地，在金属特征的暴露部分上形成氧化物层。该方法还包括在具有真空环境的生产工具中进行氧化物去除工艺以去除氧化物层。在形成开口的步骤和氧化物去除工艺之间，对生产工具外部的金属特征没有进行额外的氧化物去除处理。该方法还包括在生产工具中在开口中形成扩散阻挡层，并在扩散阻挡层上形成种子层。

2. 发明申请

US20090181164A1 Oxidation-Free Copper Metallization Process Using In-situ Baking 有权
标题翻译：使用原位烘烤的无氧铜金属化工艺
公开(公告)号：US20090181164A1
公开(公告)日：2009-07-16
申请号：US11972785
申请日：2008-01-11
申请人： Yu-Sheng Wang , Shih-Ho Lin , Kei-Wei Chen , Szu-An Wu , Ying-Lang Wang
发明人： Yu-Sheng Wang , Shih-Ho Lin , Kei-Wei Chen , Szu-An Wu , Ying-Lang Wang
IPC分类号： H05K3/46
CPC分类号： H01L21/76814 , H01L21/02063 , H01L21/76828 , H01L21/76843
摘要： A method of forming an integrated circuit structure includes providing a substrate; forming a metal feature over the substrate; forming a dielectric layer over the metal feature; and forming an opening in the dielectric layer. At least a portion of the metal feature is exposed through the opening. An oxide layer is accordingly formed on an exposed portion of the metal feature. The method further includes, in a production tool having a vacuum environment, performing an oxide-removal process to remove the oxide layer. Between the step of forming the opening and the oxide-removal process, no additional oxide-removal process is performed to the metal feature outside the production tool. The method further includes, in the production tool, forming a diffusion barrier layer in the opening, and forming a seed layer on the diffusion barrier layer
摘要翻译：形成集成电路结构的方法包括提供基板; 在衬底上形成金属特征; 在金属特征上形成介电层; 并在介电层中形成开口。金属特征的至少一部分通过开口露出。相应地，在金属特征的暴露部分上形成氧化物层。该方法还包括在具有真空环境的生产工具中进行氧化物去除工艺以去除氧化物层。在形成开口的步骤和氧化物去除工艺之间，对生产工具外部的金属特征没有进行额外的氧化物去除处理。该方法还包括在生产工具中在开口中形成扩散阻挡层，并在扩散阻挡层上形成种子层

3. 发明申请

US20090127097A1 Forming Seed Layer in Nano-Trench Structure Using Net Deposition and Net Etch 审中-公开
标题翻译：使用净沉积和净蚀刻在纳米沟槽结构中形成种子层
公开(公告)号：US20090127097A1
公开(公告)日：2009-05-21
申请号：US11941435
申请日：2007-11-16
申请人： Kei-Wei Chen , Shih-Ho Lin , Yu-Sheng Wang , Szu-An Wu , Ying-Lang Wang
发明人： Kei-Wei Chen , Shih-Ho Lin , Yu-Sheng Wang , Szu-An Wu , Ying-Lang Wang
IPC分类号： C23C14/00
CPC分类号： C23C14/345 , C23C14/046 , H01L21/76862 , H01L21/76873
摘要： A method of forming an integrated circuit structure includes forming a dielectric layer; forming an opening in the dielectric layer; performing a net deposition step to form a seed layer having a portion in the opening, wherein the net deposition step comprises a first deposition and a first etching; performing a net etch step to the seed layer, wherein the net etch step comprises a first etching and a first deposition, wherein a portion of the seed layer remains after the net etch step; and growing a conductive material on the seed layer to fill a remaining portion of the opening.
摘要翻译：形成集成电路结构的方法包括形成电介质层; 在介电层中形成开口; 执行净沉积步骤以形成具有在开口中的一部分的种子层，其中所述净沉积步骤包括第一沉积和第一蚀刻; 对所述种子层进行净蚀刻步骤，其中所述净蚀刻步骤包括第一蚀刻和第一沉积，其中所述种子层的一部分在所述净蚀刻步骤之后保留; 以及在种子层上生长导电材料以填充开口的剩余部分。

4. 发明授权

US08847286B2 Image sensor and method of manufacturing 有权
标题翻译：图像传感器及制造方法
公开(公告)号：US08847286B2
公开(公告)日：2014-09-30
申请号：US13349221
申请日：2012-01-12
申请人： Shiu-Ko Jangjian , Kei-Wei Chen , Szu-An Wu , Ying-Lang Wang
发明人： Shiu-Ko Jangjian , Kei-Wei Chen , Szu-An Wu , Ying-Lang Wang
IPC分类号： H01L27/148
CPC分类号： H01L27/14621 , H01L27/14623 , H01L27/1464
摘要： An image sensor includes a substrate having opposite first and second sides, a multilayer structure on the first side of the substrate, and a photo-sensitive element on the second side of the substrate. The photo-sensitive element is configured to receive light that is incident upon the first side and transmitted through the multilayer structure and the substrate. The multilayer structure includes first and second light transmitting layers. The first light transmitting layer is sandwiched between the substrate and the second light transmitting layer. The first light transmitting layer has a refractive index that is from 60% to 90% of a refractive index of the substrate. The second light transmitting layer has a refractive index that is lower than the refractive index of the first light transmitting layer and is from 40% to 70% of the refractive index of the substrate.
摘要翻译：图像传感器包括具有相对的第一和第二侧的基板，在基板的第一侧上的多层结构和在基板的第二侧上的感光元件。光敏元件被配置为接收入射在第一侧并透过多层结构和基板的光。多层结构包括第一和第二透光层。第一透光层夹在基板和第二透光层之间。第一透光层的折射率为基板折射率的60％至90％。第二透光层的折射率低于第一透光层的折射率，为基板的折射率的40％〜70％。

5. 发明申请

US20130134541A1 Metal Shielding Layer in Backside Illumination Image Sensor Chips and Methods for Forming the Same 有权
标题翻译：金属屏蔽层背面照明图像传感器芯片及其形成方法
公开(公告)号：US20130134541A1
公开(公告)日：2013-05-30
申请号：US13420279
申请日：2012-03-14
申请人： Shih-Chieh Chang , Jian-Shin Tsai , Chih-Chang Huang , Ing-Ju Lee , Ching-Yao Sun , Jyun-Ru Wu , Ching-Che Huang , Szu-An Wu , Ying-Lang Wang
发明人： Shih-Chieh Chang , Jian-Shin Tsai , Chih-Chang Huang , Ing-Ju Lee , Ching-Yao Sun , Jyun-Ru Wu , Ching-Che Huang , Szu-An Wu , Ying-Lang Wang
IPC分类号： H01L27/146 , H01L31/18
CPC分类号： H01L27/1464 , H01L27/1462 , H01L27/14623 , H01L27/14636 , H01L27/14643 , H01L27/14683 , H01L27/14685
摘要： A device includes a semiconductor substrate having a front side and a backside. A photo-sensitive device is disposed at a surface of the semiconductor substrate, wherein the photo-sensitive device is configured to receive a light signal from the backside of the semiconductor substrate, and convert the light signal to an electrical signal. An amorphous-like adhesion layer is disposed on the backside of the semiconductor substrate. The amorphous-like adhesion layer includes a compound of nitrogen and a metal. A metal shielding layer is disposed on the backside of the semiconductor substrate and contacting the amorphous-like adhesion layer.
摘要翻译：一种器件包括具有正面和背面的半导体衬底。光敏器件设置在半导体衬底的表面处，其中光敏器件被配置为从半导体衬底的背面接收光信号，并将光信号转换为电信号。在半导体衬底的背面设有非晶态粘接层。非晶态粘合层包括氮和金属的化合物。金属屏蔽层设置在半导体衬底的背面并与非晶态粘合层接触。

6. 发明授权

US07611589B2 Methods of spin-on wafer cleaning 有权
标题翻译：旋转晶圆清洗方法
公开(公告)号：US07611589B2
公开(公告)日：2009-11-03
申请号：US11072114
申请日：2005-03-04
申请人： Jun Wu , Dong-Xuan Lu , Shih-Chi Lin , Wen-Long Lee , Yi-An Jian , Guang-Cheng Wang , Shiu-Ko JangJian , Chyi-Tsong Ni , Szu-An Wu , Ying-Lang Wang
发明人： Jun Wu , Dong-Xuan Lu , Shih-Chi Lin , Wen-Long Lee , Yi-An Jian , Guang-Cheng Wang , Shiu-Ko JangJian , Chyi-Tsong Ni , Szu-An Wu , Ying-Lang Wang
IPC分类号： B08B3/02 , B08B1/04
CPC分类号： B08B1/04 , B08B3/02 , H01L21/67051
摘要： A method for spin-on wafer cleaning. The method comprises controlling spin speed and vertical water jet pressure. The vertical jet pressure and the spin speed are substantially maintained in inverse proportion. Wafer spin speed is between 50 to 1200 rpm. Vertical wafer jet pressure is between 0.05 to 100 KPa.
摘要翻译：旋转晶片清洗的方法。该方法包括控制旋转速度和垂直喷水压力。垂直喷射压力和旋转速度基本保持成反比例。晶圆转速在50至1200rpm之间。垂直晶片喷射压力为0.05至100KPa。

7. 发明授权

US06479098B1 Method to solve particle performance of FSG layer by using UFU season film for FSG process 有权
标题翻译：通过使用UFU季膜对FSG过程解决FSG层的粒子性能的方法
公开(公告)号：US06479098B1
公开(公告)日：2002-11-12
申请号：US09747135
申请日：2000-12-26
申请人： Ming-Hwa Yoo , Yi-Lung Cheng , Szu-An Wu , Ying-Lang Wang
发明人： Ming-Hwa Yoo , Yi-Lung Cheng , Szu-An Wu , Ying-Lang Wang
IPC分类号： C23C1640
CPC分类号： H01J37/32477 , C23C16/4404 , Y10T428/2495 , Y10T428/265
摘要： A method for reducing contaminants in a processing chamber 10 having chamber plasma processing region components comprising the following steps. The chamber plasma processing region components are cleaned. The chamber is then seasoned as follows. A first USG layer is formed over the chamber plasma processing region components. An FSG layer is formed over the first USG layer. A second USG layer is formed over the FSG layer. Wherein the USG, FSG, and second USG layers comprise a UFU season film. A UFU season film coating the chamber plasma processing region components of a processing chamber comprises: an inner USG layer over the chamber plasma processing region components; an FSG layer over the inner USG layer; and an outer USG layer over the FSG layer.
摘要翻译：一种用于减少具有室等离子体处理区域部件的处理室10中的污染物的方法，包括以下步骤。腔室等离子体处理区域部件被清洁。然后如下调节室。在室等离子体处理区域部件上形成第一USG层。在第一USG层上形成FSG层。在FSG层上形成第二个USG层。其中USG，FSG和第二USG层包括UFU季电影。 UFU季涂膜处理室的室等离子体处理区域部件包括：室上的内部USG层等离子体处理区域部件; 内部USG层上的FSG层; 以及FSG层上的外部USG层。

8. 发明授权

US06436791B1 Method of manufacturing a very deep STI (shallow trench isolation) 有权
标题翻译：制造非常深的STI（浅沟槽隔离）的方法
公开(公告)号：US06436791B1
公开(公告)日：2002-08-20
申请号：US09880259
申请日：2001-06-14
申请人： Shih-Chi Lin , Szu-An Wu , Ying-Lang Wang , Guey-Bao Huang
发明人： Shih-Chi Lin , Szu-An Wu , Ying-Lang Wang , Guey-Bao Huang
IPC分类号： H01L21302
CPC分类号： H01L21/76224
摘要： A method of forming a shallow trench isolation structure comprising the following steps. A substrate having an upper surface is provided. A pad oxide layer is formed upon the substrate. A nitride layer is formed over the pad oxide layer. The nitride layer having an upper surface. A trench is formed by etching the nitride layer, pad oxide layer and a portion of the substrate. The trench having a bottom and side walls. An oxide film is deposited upon the etched nitride layer surface, and the bottom and side walls of trench. The oxide film is removed from over the etched nitride layer surface, and the bottom of the trench to expose a portion of substrate within the trench. The removal of oxide film leaving oxide spacers over the trench side walls. Epitaxial silicon is selectively deposited over the exposed portion of substrate, filling the trench. A thermal oxide layer is formed over the epitaxial silicon, annealing the interface between the epitaxial silicon and the oxide spacers. The etched nitride layer and the oxide layer from over the etched substrate; and a portion of the oxide spacers extending above the surface of the etched substrate are removed, whereby the shallow trench isolation structure is formed within the trench.
摘要翻译：一种形成浅沟槽隔离结构的方法，包括以下步骤。提供具有上表面的基板。衬底氧化层形成在衬底上。在衬垫氧化物层上形成氮化物层。氮化物层具有上表面。通过蚀刻氮化物层，衬垫氧化物层和衬底的一部分来形成沟槽。沟槽具有底部和侧壁。在蚀刻的氮化物层表面和沟槽的底部和侧壁上沉积氧化物膜。从蚀刻的氮化物层表面上方的氧化膜和沟槽的底部去除氧化膜，以露出沟槽内的衬底的一部分。去除在沟槽侧壁上留下氧化物间隔物的氧化物膜。外延硅被选择性地沉积在衬底的暴露部分上，填充沟槽。在外延硅上形成热氧化层，退火外延硅与氧化物间隔物之间的界面。蚀刻的氮化物层和来自蚀刻的衬底上的氧化物层; 并且去除在蚀刻的衬底的表面上方延伸的氧化物间隔物的一部分，由此在沟槽内形成浅沟槽隔离结构。

9. 发明申请

US20130075831A1 METAL GATE STACK HAVING TIALN BLOCKING/WETTING LAYER 审中-公开
标题翻译：金属门盖有天然气阻塞/湿润层
公开(公告)号：US20130075831A1
公开(公告)日：2013-03-28
申请号：US13244355
申请日：2011-09-24
申请人： Shiu-Ko JangJian , Szu-An Wu , Ying-Lang Wang , Chi-Wen Liu
发明人： Shiu-Ko JangJian , Szu-An Wu , Ying-Lang Wang , Chi-Wen Liu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545
摘要： A metal gate stack having a TiAlN blocking/wetting layer, and methods of manufacturing the same, are disclosed. In an example, an integrated circuit device includes a semiconductor substrate and a gate stack disposed over the semiconductor substrate. The gate stack includes a gate dielectric layer disposed over the semiconductor substrate; a work function layer disposed over the gate dielectric layer; a multi-function wetting/blocking layer disposed over the work function layer, wherein the multi-function wetting/blocking layer is a titanium aluminum nitride layer; and a conductive layer disposed over the multi-function wetting/blocking layer.
摘要翻译：公开了具有TiAlN阻挡/润湿层的金属栅极堆叠及其制造方法。在一个示例中，集成电路器件包括设置在半导体衬底上的半导体衬底和栅极堆叠。栅极堆叠包括设置在半导体衬底上的栅介质层; 设置在所述栅极介电层上的功函数层; 设置在所述功函数层上的多功能润湿/阻挡层，其中所述多功能润湿/阻挡层是氮化铝钛层; 以及设置在多功能润湿/阻挡层上的导电层。

10. 发明申请

US20050009367A1 Novel method to increase fluorine stability to improve gap fill ability and reduce k value of fluorine silicate glass (FSG) film 审中-公开
标题翻译：提高氟稳定性以提高间隙填充能力和降低氟硅酸盐玻璃（FSG）膜的k值的新方法
公开(公告)号：US20050009367A1
公开(公告)日：2005-01-13
申请号：US10615744
申请日：2003-07-09
申请人： Yi-Lung Cheng , Ming-Hwa Yoo , Szu-An Wu , Ying-Lang Wang , Pei-Fen Chou
发明人： Yi-Lung Cheng , Ming-Hwa Yoo , Szu-An Wu , Ying-Lang Wang , Pei-Fen Chou
IPC分类号： C23C16/40 , H01L21/316 , H01L21/768 , H01L21/76 , H01L21/31 , H01L21/469
CPC分类号： H01L21/02131 , C23C16/401 , H01L21/02211 , H01L21/02274 , H01L21/31629 , H01L21/76837
摘要： A method of forming an FSG film comprising the following steps. A structure is provided. An FSG film is formed over the structure by an HDP-CVD process under the following conditions: no Argon (Ar)—side sputter; SiF4 flow: from about 53 to 63 sccm; an N2 flow: from about 25 to 35 sccm; and an RF power to provide a uniform plasma density.
摘要翻译：一种形成FSG膜的方法，包括以下步骤。提供了一种结构。在以下条件下通过HDP-CVD工艺在该结构上形成FSG膜：无氩（Ar）侧溅射; SiF4流量：约53至63sccm; N2流量：约25至35sccm; 和RF功率以提供均匀的等离子体密度。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式