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1. 发明授权

US06586347B1 Method and structure to improve the reliability of multilayer structures of FSG (F-doped SiO2) dielectric layers and metal layers in semiconductor integrated circuits 有权
标题翻译：提高半导体集成电路中FSG（F掺杂SiO2）电介质层和金属层多层结构可靠性的方法和结构
公开(公告)号：US06586347B1
公开(公告)日：2003-07-01
申请号：US09978229
申请日：2001-10-16
申请人： Chung-Shi Liu , Hui-Ling Wang , Szu-An Wu , Chun-Ching Tsan , Ying Lang Wang , Tong Hua Kuan
发明人： Chung-Shi Liu , Hui-Ling Wang , Szu-An Wu , Chun-Ching Tsan , Ying Lang Wang , Tong Hua Kuan
IPC分类号： H01L2131
CPC分类号： H01L21/76801 , H01L21/76832
摘要： An improved composite dielectric structure and method of forming thereof which prevents delamination of FSG (F-doped SiO2) and allows FSG to be used as the interlevel dielectric between successive conducting interconnection patterns in multilevel integrated circuit structures has been developed. The composite dielectric structure comprises FSG, undoped silicon oxide (optional), silicon-rich silicon oxide and silicon nitride. The silicon-rich silicon oxide layer having a thickness between about 1000 and 2000 Angstroms prevents reaction of F atoms from the FSG layer with the silicon nitride layer during subsequent manufacturing heat treatment cycles and prevents the deleterious formation of delamination bubbles which cause peeling of the FSG layer.
摘要翻译：已经开发了一种改进的复合电介质结构及其形成方法，其防止FSG（F掺杂SiO 2）的分层并且允许FSG用作多电平集成电路结构中的连续导电互连图案之间的层间电介质。复合电介质结构包括FSG，未掺杂的氧化硅（可选），富硅氧化硅和氮化硅。厚度在约1000和2000埃之间的富含硅的氧化硅层防止了F原子与氮化硅层在随后的制造热处理循环中的反应，并且防止了导致FSG剥离的分层气泡的有害形成层。

2. 发明授权

US06584987B1 Method for improved cleaning in HDP-CVD process with reduced NF3 usage 有权
标题翻译：改善HDP-CVD工艺清洗方法，减少NF3使用的方法
公开(公告)号：US06584987B1
公开(公告)日：2003-07-01
申请号：US09808929
申请日：2001-03-16
申请人： Yi-Lung Cheng , Chun-Ching Tsan , Wen-Kung Cheng , Yin-Lang Wang
发明人： Yi-Lung Cheng , Chun-Ching Tsan , Wen-Kung Cheng , Yin-Lang Wang
IPC分类号： B08B704
CPC分类号： H01J37/32862 , B08B7/0035 , C23C16/4405 , Y10S438/905
摘要： A method for cleaning residual material from a chemical vapor deposition (CVD) apparatus in situ employing dry etching. There is first employed a high density plasma chemical vapor deposition (HDP-CVD) method to deposit layers of silicon oxide material upon substrates within a chemical vapor deposition reactor apparatus. After removal of substrates, the reactor chamber is closed off. The interior of the reactor is then filled with a gas and a plasma formed therewithin, to which oxygen is added and the reactor allowed to come to an increased temperature and bake for a period of time. The reactor power is then turned off and the reactor evacuated. There is then carried out a normal cleaning step within the reactor chamber employing a reactive gas such as NF3, with greater cleaning efficiency due to the increased temperature caused by the baking step.
摘要翻译：一种从化学气相沉积（CVD）装置中原位采用干法蚀刻来清除残余物质的方法。首先采用高密度等离子体化学气相沉积（HDP-CVD）方法在化学气相沉积反应器装置中的衬底上沉积氧化硅材料层。在移除基板之后，关闭反应室。然后将反应器的内部填充有在其中形成的气体和等离子体，向其中加入氧并使反应器升温并烘烤一段时间。然后关闭反应堆功率，反应器排空。然后，使用反应气体如NF3在反应器室内进行正常的清洗步骤，由于烘烤步骤引起的温度升高，清洗效率更高。

3. 发明授权

US06268274B1 Low temperature process for forming inter-metal gap-filling insulating layers in silicon wafer integrated circuitry 有权
标题翻译：用于在硅晶片集成电路中形成金属间间隙填充绝缘层的低温工艺
公开(公告)号：US06268274B1
公开(公告)日：2001-07-31
申请号：US09418032
申请日：1999-10-14
申请人： Ying-Lang Wang , Chun-Ching Tsan , Jowei Dun , Hung-Ju Chien
发明人： Ying-Lang Wang , Chun-Ching Tsan , Jowei Dun , Hung-Ju Chien
IPC分类号： H01L2100
CPC分类号： H01L21/76801 , H01L21/31612 , H01L21/76837 , Y10S438/937
摘要： This invention provides an in situ low temperature, two step deposition HDP-CVD process separated by a cooldown period, for forming an inter-metal dielectric passivation layer for an integrated circuit structure. Said process mitigating metal line defects such as distortion or warping caused by excessive heat generated during the etching/deposition process.
摘要翻译：本发明提供了一种在冷却期间分离的原位低温两步沉积HDP-CVD工艺，用于形成用于集成电路结构的金属间介电钝化层。所述方法减轻金属线缺陷，例如在蚀刻/沉积工艺期间产生的过多热引起的变形或翘曲。

4. 发明授权

US6136680A Methods to improve copper-fluorinated silica glass interconnects 有权
标题翻译：改善铜氟化石英玻璃互连的方法
公开(公告)号：US6136680A
公开(公告)日：2000-10-24
申请号：US489498
申请日：2000-01-21
申请人： Jane-Bai Lai , Chung-Shi Liu , Tien-I Bao , Syun-Ming Jang , Chung-Long Chang , Hui-Ling Wang , Szu-An Wu , Wen-Kung Cheng , Chun-Ching Tsan , Ying-Lang Wang
发明人： Jane-Bai Lai , Chung-Shi Liu , Tien-I Bao , Syun-Ming Jang , Chung-Long Chang , Hui-Ling Wang , Szu-An Wu , Wen-Kung Cheng , Chun-Ching Tsan , Ying-Lang Wang
IPC分类号： H01L21/02 , H01L21/3105 , H01L21/321 , H01L21/768 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/76825 , H01L21/02074 , H01L21/3105 , H01L21/3212 , H01L21/76826 , H01L21/76834 , H01L21/7684 , H01L21/76883
摘要： A method of forming an interconnect, comprising the following steps. A semiconductor structure is provided that has an exposed first metal contact and a dielectric layer formed thereover. An FSG layer having a predetermined thickness is then formed over the dielectric layer. A trench, having a predetermined width, is formed within the FSG layer and the dielectric layer exposing the first metal contact. A barrier layer, having a predetermined thickness, may be formed over the FSG layer and lining the trench side walls and bottom. A metal, preferably copper, is then deposited on the barrier layer to form a copper layer, having a predetermined thickness, over said barrier layer covered FSG layer, filling the lined trench and blanket filling the barrier layer covered FSG layer. The copper layer, and the barrier layer on said upper surface of said FSG layer, are planarized, exposing the upper surface of the FSG layer and forming a planarized copper filled trench. The FSG layer and planarized copper filled trench are then processed by either: (1) annealing from about 400 to 450.degree. C. for about one hour, then either NH.sub.3 or H.sub.2 plasma treating; or (2) Ar.sup.+ sputtering to ion implant Ar.sup.+ to a depth of less than about 300 .ANG. in the fluorinated silica glass layer, whereby any formed Si--OH bonds and copper oxide (metal oxide) are removed. A dielectric cap layer, having a predetermined thickness, is then formed over the processed FSG layer and the planarized copper filled trench.
摘要翻译：一种形成互连的方法，包括以下步骤。提供一种半导体结构，其具有暴露的第一金属触点和形成在其上的电介质层。然后在电介质层上形成具有预定厚度的FSG层。具有预定宽度的沟槽形成在FSG层内，并且介电层露出第一金属接触。具有预定厚度的阻挡层可以形成在FSG层之上并且衬在沟槽侧壁和底部。然后将一种金属，优选铜沉积在阻挡层上，以形成具有预定厚度的铜层，超过所述阻挡层覆盖的FSG层，填充衬里的沟槽和覆盖填充阻挡层覆盖的FSG层的毯子。所述FSG层的所述上表面上的铜层和阻挡层被平坦化，暴露出FSG层的上表面并形成平坦化的铜填充沟槽。然后通过以下步骤之一处理FSG层和平坦化的铜填充沟槽：（1）从约400至450℃的退火约1小时，然后进行NH 3或H 2等离子体处理; 或者（2）在氟化石英玻璃层中，离子注入Ar +溅射至小于约300的深度，由此除去任何形成的Si-OH键和氧化铜（金属氧化物）。然后在经处理的FSG层和平坦化的铜填充沟槽上形成具有预定厚度的电介质盖层。

5. 发明授权

US06479881B2 Low temperature process for forming intermetal gap-filling insulating layers in silicon wafer integrated circuitry 有权
标题翻译：在硅晶片集成电路中形成金属间隙填充绝缘层的低温工艺
公开(公告)号：US06479881B2
公开(公告)日：2002-11-12
申请号：US09882678
申请日：2001-06-18
申请人： Ying-Lang Wang , Chun-Ching Tsan , Jowei Dun , Hung-Ju Chien
发明人： Ying-Lang Wang , Chun-Ching Tsan , Jowei Dun , Hung-Ju Chien
IPC分类号： H01L2900
CPC分类号： H01L21/76801 , H01L21/31612 , H01L21/76837 , Y10S438/937
摘要： A semiconductor wafer having a double inter-metal dielectric layer formed in the gaps of and on closely. spaced metal interconnection circuitry. The double dielectric layer is formed by an in situ low temperature two step deposition HDP-CVD process separated by a cool-down period. The low temperature process mitigates metal line defects such as distortion or warping caused by heat generated during the process of filling gaps having aspect ratios greater than 2. The double dielectric layer is composed of Group IV materials, silicon being the preferred material. These double layers may be individually doped. Titanium nitride layers, present as by-products of seeding and anti-reflective coatings serve to reduce electro-migration of the metal circuitry.
摘要翻译：一种半导体晶片，其具有形成在间隙中并紧密地形成的双金属介电层。间隔金属互连电路。双电介质层通过在冷却期间分离的原位低温两步沉积HDP-CVD工艺形成。低温处理减轻了金属线缺陷，例如在填充具有大于2的纵横比的间隙的过程中产生的热引起的变形或翘曲。双电介质层由第IV族材料组成，硅是优选的材料。这些双层可以单独掺杂。作为接种和抗反射涂层的副产物存在的氮化钛层用于减少金属电路的电迁移。

6. 发明授权

US06407007B1 Method to solve the delamination of a silicon nitride layer from an underlying spin on glass layer 有权
标题翻译：解决氮化硅层从玻璃层上的底层旋转分层的方法
公开(公告)号：US06407007B1
公开(公告)日：2002-06-18
申请号：US09193669
申请日：1998-11-17
申请人： Chun-Ching Tsan , Ying-Lang Wang , Hui-Ling Wang , Chin Kun Lan
发明人： Chun-Ching Tsan , Ying-Lang Wang , Hui-Ling Wang , Chin Kun Lan
IPC分类号： H01L21324
CPC分类号： H01L21/3185 , H01L21/316 , H01L21/76826
摘要： A method for improving the adhesion of a thick silicon nitride layer, to an underlying spin on glass, (SOG), layer, has been developed. After applying, baking and curing of a SOG layer, plasma treatment of the SOG layer, is performed in a deposition tool, using a nitrous oxide plasma. The plasma treatment prepares the exposed SOG surface for an in situ deposition of a thick silicon nitride layer, by improving the adhesion of thick silicon nitride to the underlying SOG layer, and by decreasing the possibility of silicon nitride delamination, that can occur with counterparts, fabricated without the nitrous oxide plasma treatment of the SOG layer.
摘要翻译：已经开发了用于改善厚氮化硅层与玻璃上的底层旋涂（SOG）层的粘附性的方法。施加，烘烤和固化SOG层之后，使用一氧化二氮等离子体在沉积工具中进行SOG层的等离子体处理。等离子体处理通过改善厚氮化硅与下面的SOG层的粘附性以及通过降低可能与对应物发生的氮化硅分层的可能性来制备暴露的SOG表面，用于原位沉积厚的氮化硅层，在没有氧化亚氮等离子体处理SOG层的情况下制造。

7. 发明授权

US06399522B1 PE-silane oxide particle performance improvement 失效
标题翻译： PE-硅烷氧化物颗粒性能改善
公开(公告)号：US06399522B1
公开(公告)日：2002-06-04
申请号：US09075115
申请日：1998-05-11
申请人： Chun-Ching Tsan , Hung-Ju Chien , Chun-Chang Chen , Ying-Lang Wang
发明人： Chun-Ching Tsan , Hung-Ju Chien , Chun-Chang Chen , Ying-Lang Wang
IPC分类号： H01L2131
CPC分类号： H01L21/02164 , C23C16/02 , C23C16/402 , H01L21/02211 , H01L21/02274 , H01L21/02312 , H01L21/31612
摘要： A method of forming a PE-silane oxide layer with a greatly reduced particle count is described. A semiconductor substrate is provided over which a silicon oxide film is to be formed. The silicon oxide film is formed by the steps of: 1) pre-flowing a non-silane gas into a deposition chamber for at least two seconds whereby the pre-flowing step prevents formation of particles on the silicon oxide film, and 2) thereafter depositing a silicon oxide film by chemical vapor deposition by flowing a silane gas into the deposition chamber to complete formation of a silicon oxide film using plasma-enhanced chemical vapor deposition in the fabrication of an integrated circuit.
摘要翻译：描述了形成具有大大降低的粒子数的PE-硅烷氧化物层的方法。提供半导体衬底，在其上形成氧化硅膜。氧化硅膜是通过以下步骤形成的：1）将非硅烷气体预先流入沉积室至少两秒钟，由此预流步骤防止在氧化硅膜上形成颗粒，2）之后通过将硅烷气体流入沉积室中，通过化学气相沉积来沉积氧化硅膜，以在集成电路的制造中使用等离子体增强化学气相沉积来形成氧化硅膜。

8. 发明授权

US06323141B1 Method for forming anti-reflective coating layer with enhanced film thickness uniformity 有权
标题翻译：用于形成具有增强的膜厚均匀性的抗反射涂层的方法
公开(公告)号：US06323141B1
公开(公告)日：2001-11-27
申请号：US09541485
申请日：2000-04-03
申请人： Szu-Au Wu , Chun-Ching Tsan , Wen-Kung Cheng , Ying-Lang Wang
发明人： Szu-Au Wu , Chun-Ching Tsan , Wen-Kung Cheng , Ying-Lang Wang
IPC分类号： H01L2131
CPC分类号： H01L21/3145 , C23C16/24 , C23C16/402 , H01L21/02164 , H01L21/02211 , H01L21/02274 , H01L21/0276 , H01L21/28123 , H01L21/31612 , H01L21/32137 , H01L21/32139
摘要： A method for forming a patterned reflective layer first employs a substrate. There is then formed over the substrate a blanket reflective layer. There is then formed upon the blanket reflective layer an anti-reflective coating (ARC) layer formed employing a plasma enhanced chemical vapor deposition (PECVD) method employing a deposition gas composition comprising silane, nitrous oxide and argon. There is then formed upon the blanket anti-reflective coating (ARC) layer a blanket photoresist layer. There is then photoexposed and developed the blanket photoresist layer to form a patterned photoresist layer. There is then etched, while employing a first etch method, the blanket anti-reflective coating (ARC) layer to form a patterned anti-reflective coating (ARC) layer while employing the patterned photoresist layer as a first etch mask layer. Finally, there is then etched, while employing a second etch method, the blanket reflective layer to form the patterned reflective layer while employing at least the patterned anti-reflective coating (ARC) layer as a second etch mask layer.
摘要翻译：用于形成图案化反射层的方法首先采用基板。然后在衬底上形成覆盖层反射层。然后在毯反射层上形成使用采用包含硅烷，一氧化二氮和氩的沉积气体组合物的等离子体增强化学气相沉积（PECVD）方法形成的抗反射涂层（ARC）层。然后在橡皮布抗反射涂层（ARC）层上形成覆盖光致抗蚀剂层。然后，将曝光的光刻胶照射并显影，以形成图案化的光致抗蚀剂层。然后，在采用第一蚀刻方法的情况下，使用覆盖层抗反射涂层（ARC）层，同时使用图案化的光致抗蚀剂层作为第一蚀刻掩模层，来形成图案化的抗反射涂层（ARC）层。最后，在采用第二蚀刻方法的同时，使用至少图案化的抗反射涂层（ARC）层作为第二蚀刻掩模层，同时使用第二蚀刻方法来蚀刻，以形成图案化的反射层。

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