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11. 发明授权

US06627514B1 Semiconductor device having a Y-shaped isolation layer and simplified method for manufacturing the Y-shaped isolation layer to prevent divot formation 失效
标题翻译：具有Y形隔离层的半导体器件和用于制造Y形隔离层的简化方法以防止形成树脂
公开(公告)号：US06627514B1
公开(公告)日：2003-09-30
申请号：US09710225
申请日：2000-11-10
申请人： Tai-su Park , Kyung-won Park , Sung-jin Kim
发明人： Tai-su Park , Kyung-won Park , Sung-jin Kim
IPC分类号： H01L2176
CPC分类号： H01L21/76232
摘要： A semiconductor device having a Y-shaped isolation layer and a method for manufacturing the same are provided. The semiconductor device includes a Y-shaped isolation layer, which comprises side walls characterized by first and second slopes on the sides of the isolation layer. The method for manufacturing the isolation layer includes the step of forming a trench in a semiconductor substrate using a photoresist pattern as an etching mask. Next, a thermal oxide film is formed on the surface of the semiconductor substrate, and then a thin nitride liner is formed on the thermal oxide film. The nitride liner prevents oxidation of the side wall of the trench and also acts as a planarization stop layer. Thereafter, a gap-filling isolation layer is formed to fill the trench such that the nitride liner is separated or thinner at the upper corners of the trench. Next, the gap-filling isolation layer is planarized using the nitride liner as a planarization stop layer. The nitride liner used as the planarization stop layer is removed. According to the present invention, formation of a divot at the boundary between an isolation region and an active region can be prevented.
摘要翻译：提供了具有Y形隔离层的半导体器件及其制造方法。该半导体器件包括Y形隔离层，其包括以隔离层侧面上的第一和第二斜面为特征的侧壁。用于制造隔离层的方法包括使用光致抗蚀剂图案作为蚀刻掩模在半导体衬底中形成沟槽的步骤。接下来，在半导体衬底的表面上形成热氧化膜，然后在热氧化膜上形成薄氮化物衬垫。氮化物衬垫防止沟槽的侧壁的氧化并且还用作平坦化停止层。此后，形成间隙填充隔离层以填充沟槽，使得氮化物衬垫在沟槽的上角分离或更薄。接下来，使用氮化物衬垫作为平坦化停止层来平坦化间隙填充隔离层。用作平坦化停止层的氮化物衬垫被去除。根据本发明，可以防止在隔离区域和有源区域之间的边界处形成边界。

12. 发明授权

US06617662B2 Semiconductor device having a trench isolation structure 失效
标题翻译：具有沟槽隔离结构的半导体器件
公开(公告)号：US06617662B2
公开(公告)日：2003-09-09
申请号：US09964906
申请日：2001-09-27
申请人： Tai-Su Park
发明人： Tai-Su Park
IPC分类号： H01L2900
CPC分类号： H01L21/76229
摘要： A device isolation structure in a semiconductor device and a method for fabricating the same are disclosed. A trench is formed in a semiconductor substrate to confine a plurality of active regions, an insulating material is deposited to fill the trench and the insulating material having a portion extending from the trench to above the semiconductor substrate, and a trench oxidation preventive film is formed on the insulating material. The semiconductor device preferably further includes a gate line extending in one direction on the semiconductor substrate having the trench oxidation-preventive film, and a sidewall spacer formed a sidewall of the gate line, wherein the trench oxidation-preventive film is disposed on the insulating material and disposed under the gate line and the sidewall spacer.
摘要翻译：公开了一种半导体器件中的器件隔离结构及其制造方法。在半导体衬底中形成沟槽以限制多个有源区，沉积绝缘材料以填充沟槽，并且绝缘材料具有从沟槽延伸到半导体衬底之上的部分，并且形成沟槽氧化防止膜在绝缘材料上。半导体器件优选还包括在具有沟槽防氧化膜的半导体衬底上的一个方向上延伸的栅极线和形成栅极线的侧壁的侧壁间隔，其中沟槽氧化防止膜设置在绝缘材料上并设置在栅极线和侧壁间隔物下。

13. 发明授权

US06465866B2 Trench isolation regions having trench liners with recessed ends 有权
标题翻译：具有凹槽端的沟槽衬套的沟槽隔离区
公开(公告)号：US06465866B2
公开(公告)日：2002-10-15
申请号：US09911096
申请日：2001-07-23
申请人： Tai-su Park , Moon-han Park , Kyung-won Park , Han-sin Lee
发明人： Tai-su Park , Moon-han Park , Kyung-won Park , Han-sin Lee
IPC分类号： H01L2176
CPC分类号： H01L21/76235
摘要： A trench isolation structure which prevents a hump phenomenon and an inverse narrow width effect of transistors by rounding the top edges of a trench and increasing the amount of oxidation at the top edges of a trench, a semiconductor device having the trench isolation structure, and a trench isolation method are provided. In this trench isolation method, a trench is formed in non-active regions of a semiconductor substrate. An inner wall oxide film having a thickness of 10 to 150 Å is formed on the inner wall of the trench. A liner is formed on the surface of the inner wall oxide film. The trench is filled with a dielectric film. Part of the liner is etched so that the top ends of the silicon nitride liner are recessed from the surface of the semiconductor substrate.
摘要翻译：一种沟槽隔离结构，其通过对沟槽的顶部边缘进行舍入并增加在沟槽的顶部边缘处的氧化量，具有沟槽隔离结构的半导体器件和防止沟槽隔离结构的半导体器件，从而防止晶体管的隆起现象和反向窄宽度效应提供沟槽隔离方法。在这种沟槽隔离方法中，在半导体衬底的非有源区中形成沟槽。在沟槽的内壁上形成厚度为10至150埃的内壁氧化膜。在内壁氧化膜的表面上形成衬垫。沟槽填充有电介质膜。蚀刻衬垫的一部分，使得氮化硅衬垫的顶端从半导体衬底的表面凹陷。

14. 发明授权

US6107143A Method for forming a trench isolation structure in an integrated circuit 有权
标题翻译：在集成电路中形成沟槽隔离结构的方法
公开(公告)号：US6107143A
公开(公告)日：2000-08-22
申请号：US150668
申请日：1998-09-10
申请人： Tai-Su Park , Han-Sin Lee , Yu-Gyun Shin
发明人： Tai-Su Park , Han-Sin Lee , Yu-Gyun Shin
IPC分类号： H01L21/76 , H01L21/762 , H01L27/08
CPC分类号： H01L21/76232
摘要： A method is provided for forming a trench isolation structure in an integrated circuit that has a better reliability and an acceptable time-dependent dielectric breakdown over a greater range of production. The manufacturing method involves etching a trench in a semiconductor substrate, forming a sidewall-insulating layer along the sidewall and bottom of the trench, and depositing a trench-insulating layer in the trench and over the semiconductor substrate. The sidewall-insulating layer is formed to have a lower etch rate than the trench-insulating layer. As a result of this difference in etch rates, the sidewall-insulating layer is not damaged too much during wet etching processes that take place during the later part of manufacture. This makes the interface between the substrate, sidewall-insulating layer, and gate oxide more reliable. The difference in etching rate can be obtained by keeping an annealing process used in later processing below a threshold temperature so that the etch rate of the trench-isolating layer does fall too low. The difference in etching rate can also be obtained by using different materials for the sidewall-isolating layer and the trench-isolating layer, or by using multiple annealing processes.
摘要翻译：提供了一种用于在集成电路中形成沟槽隔离结构的方法，该集成电路在更大的生产范围内具有更好的可靠性和可接受的时间依赖介电击穿。该制造方法包括蚀刻半导体衬底中的沟槽，沿着沟槽的侧壁和底部形成侧壁绝缘层，并且在沟槽中和半导体衬底上沉积沟槽绝缘层。侧壁绝缘层形成为具有比沟槽绝缘层低的蚀刻速率。由于这种蚀刻速率的差异，在制造后期部分的湿式蚀刻工艺期间，侧壁绝缘层不会受到太大损害。这使得衬底，侧壁绝缘层和栅极氧化物之间的界面更可靠。通过将后续处理中使用的退火处理保持在阈值温度以下，使得沟槽隔离层的蚀刻速率确实降低，可以获得蚀刻速率的差异。也可以通过使用用于侧壁隔离层和沟槽隔离层的不同材料或通过使用多个退火工艺来获得蚀刻速率的差异。

15. 发明授权

US6083808A Method for forming a trench isolation in a semiconductor device 有权
标题翻译：在半导体器件中形成沟槽隔离的方法
公开(公告)号：US6083808A
公开(公告)日：2000-07-04
申请号：US160094
申请日：1998-09-25
申请人： Yu-Gyun Shin , Han-Sin Lee , Tai-su Park , Moon-Han Park
发明人： Yu-Gyun Shin , Han-Sin Lee , Tai-su Park , Moon-Han Park
IPC分类号： H01L21/76 , H01L21/28 , H01L21/762
CPC分类号： H01L21/76224 , Y10S148/05
摘要： A method for forming a trench isolation in a semiconductor device is provided in which a first heat treatment process is conducted on a thermal oxide layer previously formed in a trench at temperature range from about 1000.degree. C. to 1200.degree. C. for about 1 to 8 hours so as to remove defects in a semiconductor substrate and oxygen impurities within the semiconductor substrate resulting from a step of forming the trench in the semiconductor substrate. As a result, a subsequent second heat treatment process for densifying a trench filling material such as a CVD oxide layer can be performed at lower temperature of about 1000.degree. C. to 1050.degree. C., as compared with the temperature of the first annealing of the thermal oxide layer, thereby reducing distortions of the semiconductor substrate and reducing current leakages.
摘要翻译：提供了一种在半导体器件中形成沟槽隔离的方法，其中对预先形成在沟槽中的热氧化层进行第一热处理工艺，温度范围为约1000℃至1200℃，约1至 8小时，以便从半导体衬底中形成沟槽的步骤得到半导体衬底中的缺陷和半导体衬底内的氧杂质。结果，与在第一次退火温度相比，可以在约1000℃至1050℃的较低温度下进行用于致密化CVD氧化物层的沟槽填充材料的随后的第二热处理工艺热氧化层，从而减少半导体衬底的变形并减少电流泄漏。

16. 发明授权

US5966614A Silicon nitride-free isolation methods for integrated circuits 失效
标题翻译：集成电路无氮化物隔离方法
公开(公告)号：US5966614A
公开(公告)日：1999-10-12
申请号：US934241
申请日：1997-09-19
申请人： Tai-su Park , Ho-kyu Kang
发明人： Tai-su Park , Ho-kyu Kang
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L21/76232 , Y10S438/959
摘要： Trench isolation methods for integrated circuit substrates may be simplified by eliminating the steps of forming a silicon nitride layer, etching the silicon nitride layer and removing the silicon nitride layer. In particular, a silicon nitride-free mask pattern, such as a photoresist mask pattern, may be formed on a silicon nitride-free integrated circuit substrate. The silicon nitride-free integrated circuit substrate is etched through the silicon nitride-free mask pattern to form a trench in the substrate. An insulating layer is formed in the trench and is chemical-mechanical polished to form a trench isolating layer. By eliminating the silicon nitride layer, simplified processing and improved performance may be obtained.
摘要翻译：通过消除形成氮化硅层的步骤，蚀刻氮化硅层和去除氮化硅层，可以简化用于集成电路基板的沟槽隔离方法。特别地，不含氮化硅的掩模图案，例如光致抗蚀剂掩模图案，可以形成在无氮化硅的集成电路基板上。通过无氮化硅的掩模图案蚀刻无氮化硅的集成电路衬底，以在衬底中形成沟槽。在沟槽中形成绝缘层，并进行化学机械抛光以形成沟槽隔离层。通过消除氮化硅层，可以获得简化的处理和改进的性能。

17. 发明授权

US5902127A Methods for forming isolation trenches including doped silicon oxide 失效
标题翻译：用于形成包括掺杂氧化硅的隔离沟槽的方法
公开(公告)号：US5902127A
公开(公告)日：1999-05-11
申请号：US742950
申请日：1996-10-31
申请人： Tai-su Park
发明人： Tai-su Park
IPC分类号： H01L21/76 , H01L21/265 , H01L21/762
CPC分类号： H01L21/76232 , Y10S148/05
摘要： A method for forming a microelectronic structure includes the steps of forming a trench in a substrate and forming an insulating layer which fills the trench and covers the substrate. Ions can be implanted into the insulating layer which decrease an etch rate of the insulating layer, and portions of the insulating layer on the substrate can be removed while maintaining the insulating layer in the trench. In addition, the step of forming the insulating layer can include forming an undoped oxide layer on the substrate and forming a doped oxide layer on the undoped oxide layer wherein a void is formed in the doped oxide layer. The void can thus be reduced by reflowing the doped oxide layer.
摘要翻译：一种形成微电子结构的方法包括以下步骤：在衬底中形成沟槽并形成填充沟槽并覆盖衬底的绝缘层。可以将离子注入到绝缘层中，这降低了绝缘层的蚀刻速率，并且可以在保持沟槽中的绝缘层的同时去除衬底上的绝缘层的部分。此外，形成绝缘层的步骤可以包括在衬底上形成未掺杂的氧化物层，并且在未掺杂的氧化物层上形成掺杂的氧化物层，其中在掺杂氧化物层中形成空隙。因此可以通过回流掺杂的氧化物层来减小空隙。

18. 发明授权

US5858858A Annealing methods for forming isolation trenches 失效
标题翻译：用于形成隔离沟的退火方法
公开(公告)号：US5858858A
公开(公告)日：1999-01-12
申请号：US729453
申请日：1996-10-11
申请人： Tai-su Park , Moon-han Park , Yu-gyun Shin , Han-sin Lee
发明人： Tai-su Park , Moon-han Park , Yu-gyun Shin , Han-sin Lee
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L21/76224
摘要： A method for forming a microelectronic structure includes the steps of forming a mask layer on a substrate, forming a trench in the exposed portion of the substrate, forming a layer of an insulating material which fills the trench and covers the mask layer, and annealing the insulating material at a temperature of at least about 1,150.degree. C. The annealing step can be performed for a period of time of about .5 hours to about 8 hours, and the annealing step can be performed in an inert atmosphere.
摘要翻译：一种形成微电子结构的方法包括以下步骤：在衬底上形成掩模层，在衬底的暴露部分形成沟槽，形成填充沟槽并覆盖掩模层的绝缘材料层，并退火绝缘材料在至少约1150℃的温度下进行。退火步骤可以进行约0.5小时至约8小时的时间，退火步骤可以在惰性气氛中进行。

19. 发明授权

US08691649B2 Methods of forming recessed channel array transistors and methods of manufacturing semiconductor devices 有权
标题翻译：形成凹槽阵列晶体管的方法和制造半导体器件的方法
公开(公告)号：US08691649B2
公开(公告)日：2014-04-08
申请号：US13151494
申请日：2011-06-02
申请人： Tai-Su Park , Jung-Sup Oh , Gun-Joong Lee , Jung-Soo An , Dong-Kyu Lee , Jung-Geun Park , Jeong-Do Ryu , Dong-Chan Kim , Seong-Hoon Jeong , Si-Young Choi , Yu-Gyun Shin , Jong-Ryeol Yoo , Jong-Hoon Kang
发明人： Tai-Su Park , Jung-Sup Oh , Gun-Joong Lee , Jung-Soo An , Dong-Kyu Lee , Jung-Geun Park , Jeong-Do Ryu , Dong-Chan Kim , Seong-Hoon Jeong , Si-Young Choi , Yu-Gyun Shin , Jong-Ryeol Yoo , Jong-Hoon Kang
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L21/28211 , H01L21/823412 , H01L27/105 , H01L27/10876 , H01L27/10879 , H01L27/11 , H01L29/4236 , H01L29/51 , H01L29/66621 , H01L29/7851
摘要： In methods of manufacturing a recessed channel array transistor, a recess may be formed in an active region of a substrate. A plasma oxidation process may be performed on the substrate to form a preliminary gate oxide layer on an inner surface of the recess and an upper surface of the substrate. Moistures may be absorbed in a surface of the preliminary gate oxide layer to form a gate oxide layer. A gate electrode may be formed on the gate oxide layer to fill up the recess. Source/drain regions may be formed in an upper surface of the substrate at both sides of the gate electrode. Thus, the oxide layer may have a uniform thickness distribution and a dense structure.
摘要翻译：在制造凹陷通道阵列晶体管的方法中，可以在衬底的有源区中形成凹部。可以在衬底上进行等离子体氧化处理，以在凹槽的内表面和衬底的上表面上形成预备栅氧化层。可以在预选择栅极氧化物层的表面吸收水分以形成栅极氧化物层。可以在栅极氧化物层上形成栅电极以填充凹部。源极/漏极区域可以形成在栅电极的两侧的衬底的上表面中。因此，氧化物层可以具有均匀的厚度分布和致密结构。

20. 发明授权

US07807543B2 Methods of manufacturing trench isolation structures using selective plasma ion immersion implantation and deposition (PIIID) 有权
标题翻译：使用选择性等离子体离子浸入和沉积（PIIID）制造沟槽隔离结构的方法
公开(公告)号：US07807543B2
公开(公告)日：2010-10-05
申请号：US12134760
申请日：2008-06-06
申请人： Dong-woon Shin , Tai-su Park , Si-young Choi , Soo-jin Hong , Mi-jin Kim
发明人： Dong-woon Shin , Tai-su Park , Si-young Choi , Soo-jin Hong , Mi-jin Kim
IPC分类号： H01L21/76
CPC分类号： H01L21/823481 , H01L21/76229 , H01L21/823456 , H01L27/0921 , H01L27/105
摘要： A semiconductor device is manufactured by forming trenches in a substrate and selectively performing Plasma Ion Immersion Implantation and Deposition (PIIID) on a subset of the trenches in the substrate. The PIIID may be performed on only a portion of a surface of at least one of the trenches in the substrate. Semiconductor devices can include a semiconductor substrate having first, second and third trenches therein, and an oxide liner layer that fully lines the first trenches, that does not line the second trenches and that partially lines the third trenches.
摘要翻译：通过在衬底中形成沟槽并且在衬底中的沟槽的子集上选择性地执行等离子体离子注入植入和沉积（PIIID）来制造半导体器件。 PIIID可以仅在衬底中的至少一个沟槽的表面的一部分上进行。半导体器件可以包括其中具有第一，第二和第三沟槽的半导体衬底以及不对第一沟槽进行线条化的氧化物衬层，其不线性化第二沟槽并且部分地对第三沟槽进行排列。

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