专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US5296755A High speed BI CMOS logic circuit and a semiconductor integrated circuit device using same 失效
标题翻译：高速BI CMOS逻辑电路和使用其的半导体集成电路器件
公开(公告)号：US5296755A
公开(公告)日：1994-03-22
申请号：US799327
申请日：1991-11-27
申请人： Kazuhisa Miyamoto , Mitsugu Kusunoki , Masanori Odaka , Mitsuo Usami
发明人： Kazuhisa Miyamoto , Mitsugu Kusunoki , Masanori Odaka , Mitsuo Usami
IPC分类号： H01L27/06 , G11C11/418 , H01L21/8249 , H03K19/013 , H03K19/08 , H03K19/0944 , H03K17/04
CPC分类号： H03K19/09448 , G11C11/418 , H03K19/013
摘要： Herein disclosed is a logic circuit which has an input bipolar transistor for receiving an input signal at its base; variable impedance circuit having at least a first P-channel MOSFET connected between a first supply voltage and the collector of the input bipolar transistor; a second N-channel MOSFET connected between the emitter of the input bipolar transistor and a second supply voltage; an output bipolar transistor connected between the first supply voltage and the output terminal of the circuit for receiving the collector potential of the input bipolar transistor at its base; and a third, pull-down MOSFET connected between the output terminal and the second or third supply voltage.
摘要翻译：这里公开了一种逻辑电路，其具有用于在其基极处接收输入信号的输入双极晶体管; 可变阻抗电路具有连接在第一电源电压和输入双极晶体管的集电极之间的至少第一P沟道MOSFET; 连接在输入双极晶体管的发射极和第二电源电压之间的第二N沟道MOSFET; 连接在电路的第一电源电压和输出端之间的输出双极晶体管，用于接收输入双极晶体管的基极的集电极电位; 以及连接在输出端子和第二或第三电源电压之间的第三个下拉MOSFET。

12. 发明授权

US08528414B2 Apparatus for measuring a mechanical quantity 有权
标题翻译：用于测量机械量的装置
公开(公告)号：US08528414B2
公开(公告)日：2013-09-10
申请号：US13180603
申请日：2011-07-12
申请人： Kentaro Miyajima , Mitsugu Kusunoki
发明人： Kentaro Miyajima , Mitsugu Kusunoki
IPC分类号： G01B7/16 , G01L1/00
CPC分类号： G01L1/2281 , G01L1/2293
摘要： Because of stress occurring due to a change in temperature, and presence of heat distribution on a semiconductor substrate, and a dopant dosage gradient, an offset output occurs to a Wheatstone bridge circuit intended for detection of strain, posing a problem. To solve the problem, diffusion resistors are disposed in the form of a matrix, and bridge resistors Rv1, Rv2 each are formed by selectively connecting diffusion resistors disposed in each odd column, in series with each other, while Rh1, Rh2 each are formed by selectively connecting diffusion resistors disposed in each even column, in series with each other.
摘要翻译：由于温度变化引起的应力和半导体衬底上的热分布的存在以及掺杂剂剂量梯度，偏移输出发生在用于检测应变的惠斯通电桥电路中，造成问题。为了解决这个问题，扩散电阻器以矩阵的形式设置，桥式电阻器Rv1，Rv2分别通过选择性地连接设置在每个奇数列中的扩散电阻器彼此串联而形成，而Rh1，Rh2分别由选择性地连接设置在每个偶数列中的扩散电阻器彼此串联。

13. 发明授权

US08497791B2 Operational amplifier 有权
标题翻译：运算放大器
公开(公告)号：US08497791B2
公开(公告)日：2013-07-30
申请号：US13468126
申请日：2012-05-10
申请人： Atsushi Okumura , Ryusuke Sahara , Mitsugu Kusunoki
发明人： Atsushi Okumura , Ryusuke Sahara , Mitsugu Kusunoki
IPC分类号： H03M1/10
CPC分类号： H03F3/45475 , H03F3/45928 , H03F2200/447 , H03F2203/45522 , H03F2203/45528 , H03F2203/45534 , H03F2203/45591 , H03F2203/45594 , H03F2203/45616
摘要： A temperature dependence adjustable operational amplifier circuit which suppresses a change in a gain caused by a change in an input voltage is provided. In an operational amplifier including a first input terminal and an output terminal, an operational amplifier having an inverting input terminal and a non-inverting input terminal, an input resistance circuit, and a feedback resistance circuit, each of the input and feedback resistor circuits has a resistor and a trimming resistor, which are different in temperature coefficient from each other, connected in series with each other, and a source-drain path of a MOS transistor included in the trimming resistor circuit is disposed between resistance and an inverting input terminal, and a substrate potential thereof is set to a potential of the inverting input terminal of the operational amplifier.
摘要翻译：提供了抑制由输入电压变化引起的增益变化的温度依赖性可调运算放大器电路。在包括第一输入端子和输出端子的运算放大器中，具有反相输入端子和非反相输入端子的运算放大器，输入电阻电路和反馈电阻电路，每个输入和反馈电阻电路具有电阻和微调电阻彼此串联连接的温度系数彼此不同，并且包括在微调电阻电路中的MOS晶体管的源极 - 漏极路径被设置在电阻和反相输入端之间，并且其衬底电位被设置为运算放大器的反相输入端的电位。

14. 发明申请

US20100072821A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20100072821A1
公开(公告)日：2010-03-25
申请号：US12507660
申请日：2009-07-22
申请人： Kenichiro YAMAGUCHI , Atsushi Okumura , Mitsugu Kusunoki , Tomoo Murata
发明人： Kenichiro YAMAGUCHI , Atsushi Okumura , Mitsugu Kusunoki , Tomoo Murata
IPC分类号： H02J3/00
CPC分类号： H03M1/0643 , H01L27/0203 , H03M1/687 , H03M1/745 , H03M1/785 , Y10T307/696
摘要： Operating speed as well as output accuracy of a D-A converter is enhanced. With a semiconductor device including unit current sources, and unit current source switches, plural current source elements constituting each of the unit current sources are disposed so as to be evenly dispersed, thereby reducing errors of the current source element, dependent on distance while the unit current source switches are concentratedly disposed in a small region, thereby mitigating delay in operation, attributable to parasitic capacitance. In addition, with the semiconductor device including R2R resistance ladders, the R2R resistance ladder is provided on the positive and the negative of each of the unit current source switches, and the respective R2R resistance ladders are shorted with each other at respective nodes on a unit current source switch-by-unit current source switch basis, are rendered identical in length, thereby cancelling out a nonlinearity error attributable to wiring parasitic resistance.
摘要翻译：提高了D-A转换器的工作速度和输出精度。利用包括单位电流源和单位电流源开关的半导体器件，构成每个单位电流源的多个电流源元件被布置成均匀分散，从而根据距离减小电流源元件的误差，而单元电流源开关集中地设置在较小的区域中，从而减轻了由寄生电容引起的工作延迟。另外，对于包含R2R电阻梯的半导体装置，在每个单位电流源开关的正极和负极上设置R2R电阻梯，并且相应的R2R电阻梯在单元的相应节点处相互短路电流源逐个电流源开关基础的长度相同，从而消除归因于布线寄生电阻的非线性误差。

15. 发明授权

US07629669B2 Semiconductor apparatus 失效
标题翻译：半导体装置
公开(公告)号：US07629669B2
公开(公告)日：2009-12-08
申请号：US11411096
申请日：2006-04-26
申请人： Koji Ishikawa , Kazutaka Mori , Hiroshige Kogayu , Tamotsu Miyake , Mitsugu Kusunoki
发明人： Koji Ishikawa , Kazutaka Mori , Hiroshige Kogayu , Tamotsu Miyake , Mitsugu Kusunoki
IPC分类号： H01L27/102
CPC分类号： H01L23/5252 , H01L27/0823 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor apparatus includes a first transistor having a first emitter electrode, a first base electrode, and a first collector electrode in a region over a first region. Base lead-out polysilicon connecting the first base electrode and a first base region passes over a second region provided out of the first region and a resistor element is added. A writing voltage is reduced in an antifuse using two bipolar transistors.
摘要翻译：半导体装置包括在第一区域的区域中具有第一发射极，第一基极和第一集电极的第一晶体管。连接第一基极和第一基极区域的基极引出多晶硅通过在第一区域外提供的第二区域，并且添加电阻元件。使用两个双极晶体管在反熔丝中减小写入电压。

16. 发明授权

US07522083B2 Semiconductor device having D/A conversion portion 有权
标题翻译：具有D / A转换部分的半导体器件
公开(公告)号：US07522083B2
公开(公告)日：2009-04-21
申请号：US11877561
申请日：2007-10-23
申请人： Ryusuke Sahara , Mitsugu Kusunoki , Kazutaka Mori , Hiroshige Kogayu
发明人： Ryusuke Sahara , Mitsugu Kusunoki , Kazutaka Mori , Hiroshige Kogayu
IPC分类号： H03M1/78
CPC分类号： H03M1/1061 , H03M1/687 , H03M1/785 , H03M1/808
摘要： A DAC having a memory mat including a plurality of first memory cells, and a plurality of output lines connected to the plurality of first memory cells. Each of the plurality of memory cells has a first memory portion including bipolar transistors and storing information in non-volatility based on whether a junction of the bipolar transistors is destroyed or not, and a second memory portion connected to the first memory portion and for outputting information to corresponding one of the plurality of output lines. The DAC has a first mode in which information is transferred from the first memory portions to the second memory portions when the information is written into the second memory portions, and a second mode in which the second memory portions are specified externally and information is written into the second memory portions. Thus, the performance of a D/A converter can be improved.
摘要翻译：具有包括多个第一存储单元的存储器垫的DAC和连接到多个第一存储单元的多个输出线。多个存储单元中的每一个具有包括双极晶体管的第一存储器部分，并且基于双极晶体管的结是否被破坏来存储非易失性的信息，以及连接到第一存储器部分并用于输出的第二存储器部分信息到多个输出行中的相应一个。 DAC具有第一模式，其中当信息被写入第二存储器部分时，信息从第一存储器部分传送到第二存储器部分，以及第二模式，其中第二存储器部分被外部指定并且信息被写入第二存储器部分。因此，可以提高D / A转换器的性能。

17. 发明授权

US06621352B2 Semiconductor integrated circuit device 失效
公开(公告)号：US06621352B2
公开(公告)日：2003-09-16
申请号：US09983968
申请日：2001-10-26
申请人： Takashi Matsumoto , Hikaru Suzuki , Mitsugu Kusunoki
发明人： Takashi Matsumoto , Hikaru Suzuki , Mitsugu Kusunoki
IPC分类号： H03L700
CPC分类号： G01R31/31709 , G01R31/31725 , G11C29/14 , H03K2005/00058 , H03L7/06 , H03L7/0814 , H03L7/095 , Y10S331/02
摘要： There is provided a semiconductor integrated circuit device for realizing in the higher accuracy the verification of a plurality of operations of a clock generation circuit to form an internal clock signal and enabling verification for various performances of the internal clock signal generation circuit while simplifying the structure thereof. In such semiconductor integrated circuit device, a measuring circuit for conducting at least two kinds of measurements among the measurements of lock time until the predetermined internal clock signal corresponding to the input clock signal can be obtained, the maximum frequency of the internal clock signal and jitter of the internal clock signal is provided to the clock generation circuit to form the internal clock signal corresponding to the input clock signal inputted from an external terminal. Thereby, operations of the clock generation circuit can be verified with higher accuracy within the semiconductor integrated circuit device.

18. 发明授权

US06191990B1 Semiconductor integrated circuit device having stabilizing capacitors connected between power lines of main amplifiers 有权
标题翻译：半导体集成电路器件具有连接在主放大器的电源线之间的稳定电容器
公开(公告)号：US06191990B1
公开(公告)日：2001-02-20
申请号：US09507785
申请日：2000-02-22
申请人： Nobutaka Itoh , Shuichi Miyaoka , Yuji Yokoyama , Michiaki Nakayama , Mitsugu Kusunoki , Kazumasa Takashima , Hideki Sakakibara , Toru Kobayashi
发明人： Nobutaka Itoh , Shuichi Miyaoka , Yuji Yokoyama , Michiaki Nakayama , Mitsugu Kusunoki , Kazumasa Takashima , Hideki Sakakibara , Toru Kobayashi
IPC分类号： G11C702
CPC分类号： G11C7/18 , H01L27/0207 , H01L27/10814 , H01L27/10897 , H01L27/11 , H01L28/75
摘要： A semiconductor integrated circuit device has a memory array which includes amplifying MOSFETs of sense amplifiers which amplify small voltages read out of dynamic memory cells onto bit lines and column switch MOSFETs which select bit lines, a read/write section which includes main amplifiers for reading out stored data from memory cells selected by the column switch, and a logic circuit which implements the input/output operation of data with the read/write section. Two capacitors each having a first electrode which corresponds to a plate electrode with the same structure as that of storage capacitors of dynamic memory cells and a second electrode which is multiple commonly-connected storage nodes of the storage capacitors are arranged in serial connection, disposed contiguously to the read/write section, and connected between operation voltage lines of the read/write section.
摘要翻译：一种半导体集成电路器件具有存储器阵列，该存储器阵列包括将读出放大器中的动态存储单元读出的小电压放大到位线和选择位线的列开关MOSFET的读出放大器的MOSFET，包括用于读出的主放大器的读/写部分来自由列开关选择的存储器单元的存储数据，以及实现与读/写部分的数据的输入/输出操作的逻辑电路。两个电容器具有第一电极，其对应于具有与动态存储单元的存储电容器相同结构的平板电极的第一电极和作为存储电容器的多个共同连接的存储节点的第二电极串联连接设置到读/写部分，并连接在读/写部分的操作电压线之间。

19. 发明授权

US5291445A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5291445A
公开(公告)日：1994-03-01
申请号：US589515
申请日：1990-09-28
申请人： Shuuichi Miyaoka , Kazuhisa Miyamoto , Masanori Odaka , Hideo Sawamoto , Michiaki Nakayama , Mitsugu Kusunoki , Masato Ikeda , Takashi Ogata , Kouji Kobayashi , Masao Kato , Tsutomu Sumimoto
发明人： Shuuichi Miyaoka , Kazuhisa Miyamoto , Masanori Odaka , Hideo Sawamoto , Michiaki Nakayama , Mitsugu Kusunoki , Masato Ikeda , Takashi Ogata , Kouji Kobayashi , Masao Kato , Tsutomu Sumimoto
IPC分类号： H03K19/0175 , H03K19/0944 , G11C7/00
CPC分类号： H03K19/017527 , H03K19/017518 , H03K19/09448
摘要： A semiconductor integrated circuit device such as a memory device with logic function comprises a plurality of RAM macrocells and gate arrays. The RAM macrocells are constituted by bipolar CMOS RAMs having a total memory capacity of at least 100 kilobits, and the gate arrays contain at least 4000 gates. The logic circuits in the memory device with logic function or the like are constructed by selectively combining CMOS, bipolar CMOS or ECL gate circuits depending on the output load capacity, transmission characteristic requirement, power dissipation and required layout area. The level of signals at various circuits is set to the ECL level or MOS level depending on the local circuit configuration and other factors. The memory device further incorporates sequence control circuits required to be installed downstream of buffer storages of computers.
摘要翻译：诸如具有逻辑功能的存储器件的半导体集成电路器件包括多个RAM宏单元和门阵列。 RAM宏单元由具有至少100千位的总存储器容量的双极性CMOS RAM构成，并且门阵列包含至少4000个栅极。具有逻辑功能等的存储器件中的逻辑电路通过根据输出负载能力，传输特性要求，功耗和所需布局面积选择性地组合CMOS，双极CMOS或ECL门电路而构成。各种电路的信号电平根据本地电路配置和其他因素设置为ECL电平或MOS电平。存储器装置还包括需要安装在计算机的缓冲存储器下游的顺序控制电路。

20. 发明授权

US07078928B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US07078928B2
公开(公告)日：2006-07-18
申请号：US10736673
申请日：2003-12-17
申请人： Ryusuke Sahara , Kozaburo Kurita , Yuuji Suzuki , Mitsugu Kusunoki , Hideki Sakakibara
发明人： Ryusuke Sahara , Kozaburo Kurita , Yuuji Suzuki , Mitsugu Kusunoki , Hideki Sakakibara
IPC分类号： H03K19/00 , G01R31/28 , H03H11/26
CPC分类号： G01R31/318577
摘要： The present invention provides a semiconductor integrated circuit device equipped with at least one pulse generator which generates a pulse of a pulse with shorter than a rising time up to the full amplitude of a transfer signal.A first signal and a second signal supplied from outside through a first signal path and a second signal path are respectively transferred to the pulse generator. When a rising time up to the full amplitude at any one of buffers in the first signal path and the second signal path is longer than a pulse width of a pulse to be formed by the pulse generator, the difference in phase between the first signal and the second signal is caused to correspond to a pulse width of a first pulse.
摘要翻译：本发明提供一种配备有至少一个脉冲发生器的半导体集成电路器件，该脉冲发生器产生的脉冲脉冲短于传输信号的全幅度的上升时间。通过第一信号路径和第二信号路径从外部提供的第一信号和第二信号分别传送到脉冲发生器。当在第一信号路径和第二信号路径中的任何一个缓冲器上的上升时间达到全幅度时，脉冲发生器将形成的脉冲的脉冲宽度大于第一信号与第二信号路径之间的相位差使第二信号对应于第一脉冲的脉冲宽度。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式