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101. 发明授权

US06764908B1 Narrow width CMOS devices fabricated on strained lattice semiconductor substrates with maximized NMOS and PMOS drive currents 有权
标题翻译：窄带CMOS器件制造在具有最大NMOS和PMOS驱动电流的应变晶格半导体衬底上
公开(公告)号：US06764908B1
公开(公告)日：2004-07-20
申请号：US10173770
申请日：2002-06-19
申请人： Daniel Kadosh , Derick J. Wristers , Qi Xiang , Bin Yu
发明人： Daniel Kadosh , Derick J. Wristers , Qi Xiang , Bin Yu
IPC分类号： H01L21336
CPC分类号： H01L29/1054 , H01L21/823807
摘要： A method of manufacturing a semiconductor device comprises steps of: (a) providing a semiconductor substrate comprising an upper, tensilely strained lattice semiconductor layer and a lower, unstressed semiconductor layer; and (b) forming at least one MOS transistor on or within the tensilely strained lattice semiconductor layer, wherein the forming comprises a step of regulating the drive current of the at least one MOS transistor by adjusting the thickness of the tensilely strained lattice semiconductor layer. Embodiments include CMOS devices formed in substrates including a strained Si layer lattice-matched to a graded composition Si—Ge layer, wherein the thickness of the strained Si layer of each of the PMOS and NMOS transistors is adjusted to provide each transistor type with maximum drive current.
摘要翻译：一种制造半导体器件的方法包括以下步骤：（a）提供包括上部，拉伸应变晶格半导体层和下部未应力半导体层的半导体衬底; 和（b）在拉伸应变晶格半导体层上或其内形成至少一个MOS晶体管，其中所述形成包括通过调整拉伸应变晶格半导体层的厚度来调节所述至少一个MOS晶体管的驱动电流的步骤。实施例包括形成在包括与渐变组合物Si-Ge层晶格匹配的应变Si层的衬底中的CMOS器件，其中调节每个PMOS晶体管和NMOS晶体管的应变Si层的厚度以提供每个晶体管类型的最大驱动当前。

102. 发明授权

US06762483B1 Narrow fin FinFET 有权
标题翻译：窄鳍FinFET
公开(公告)号：US06762483B1
公开(公告)日：2004-07-13
申请号：US10348910
申请日：2003-01-23
申请人： Zoran Krivokapic , Judy Xilin An , Srikanteswara Dakshina-Murthy , Haihong Wang , Bin Yu
发明人： Zoran Krivokapic , Judy Xilin An , Srikanteswara Dakshina-Murthy , Haihong Wang , Bin Yu
IPC分类号： H01L2906
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66818 , H01L29/78687
摘要： A method of forming fins for a double-gate fin field effect transistor (FinFET) includes forming a second layer of semi-conducting material over a first layer of semi-conducting material and forming double caps in the second layer of semi-conducting material. The method further includes forming spacers adjacent sides of each of the double caps and forming double fins in the first semi-conducting material beneath the double caps. The method also includes thinning the double fins to produce narrow double fins.
摘要翻译：一种形成双栅极鳍效应晶体管（FinFET）的鳍片的方法包括在第一半导体材料层上形成第二半导电材料层，并在第二半导体材料层中形成双重盖子。该方法还包括在每个双盖的侧面上形成间隔物，并在双盖下方的第一半导体材料中形成双翅片。该方法还包括使双翅片变薄以产生窄的双翅片。

103. 发明授权

US06756643B1 Dual silicon layer for chemical mechanical polishing planarization 有权
标题翻译：双层硅化学机械抛光平面化
公开(公告)号：US06756643B1
公开(公告)日：2004-06-29
申请号：US10459579
申请日：2003-06-12
申请人： Krishnashree Achuthan , Shibly S. Ahmed , Haihong Wang , Bin Yu
发明人： Krishnashree Achuthan , Shibly S. Ahmed , Haihong Wang , Bin Yu
IPC分类号： H01L2976
CPC分类号： H01L29/785 , H01L21/3212 , H01L29/4908 , H01L29/66795 , H01L29/6681
摘要： A FinFET-type semiconductor device includes a fin structure on which a relatively thin amorphous silicon layer and then an undoped polysilicon layer is formed. The semiconductor device may be planarized using a chemical mechanical polishing (CMP) in which the amorphous silicon layer acts as a stop layer to prevent damage to the fin structure.
摘要翻译： FinFET型半导体器件包括翅片结构，其上形成相对薄的非晶硅层，然后形成未掺杂的多晶硅层。半导体器件可以使用化学机械抛光（CMP）进行平面化，其中非晶硅层用作阻挡层以防止损坏鳍结构。

104. 发明授权

US06746926B1 MOS transistor with highly localized super halo implant 有权
标题翻译：具有高度局部化超级晕轮植入物的MOS晶体管
公开(公告)号：US06746926B1
公开(公告)日：2004-06-08
申请号：US09844752
申请日：2001-04-27
申请人： Bin Yu
发明人： Bin Yu
IPC分类号： H01L21336
CPC分类号： H01L29/66492 , H01L21/823807 , H01L29/1045 , H01L29/665 , H01L29/66628 , H01L29/7834
摘要： A method for improving the channel doping profile of deep-submicron field effect transistors and MOSFETs. The method involves a highly localized halo implant formed in the channel region but not in the source/drain junction. The halo implant is performed through a gap formed by removal of a temporary spacer. The MOSFET is then further completed.
摘要翻译：一种改进深亚微米场效应晶体管和MOSFET的沟道掺杂分布的方法。该方法包括形成在沟道区域中而不是在源极/漏极结中的高度局部化的卤素注入。通过移除临时间隔物形成的间隙进行晕轮植入。然后，MOSFET进一步完成。

105. 发明授权

US06680250B1 Formation of deep amorphous region to separate junction from end-of-range defects 有权
标题翻译：形成深非晶区域以将结点与端范围缺陷分离
公开(公告)号：US06680250B1
公开(公告)日：2004-01-20
申请号：US10145740
申请日：2002-05-16
申请人： Eric N. Paton , Robert B. Ogle , Cyrus E. Tabery , Qi Xiang , Bin Yu
发明人： Eric N. Paton , Robert B. Ogle , Cyrus E. Tabery , Qi Xiang , Bin Yu
IPC分类号： H01L2144
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/26513 , H01L21/268
摘要： A method of manufacturing a MOSFET semiconductor device includes forming a gate electrode over a substrate and a gate oxide between the gate electrode and the substrate. Inert dopants are then implanted within the substrate to form amorphized source/drain regions in the substrate extending to a first depth significantly greater than the intended junction depth. The amorphized source/drain regions are implanted with source/drain dopants such that the dopants extend into the substrate to a second depth less than the first depth, above and spaced apart from the end-of-range defect region created at the first depth by the amorphization process. Laser thermal annealing recrystallizes the amorphous regions, activates the source/drain regions and forms source/drain junctions. Because the recrystallization front velocity towards the substrate main surface is greater than the dopant atom velocity in the liquid substrate during laser thermal annealing, the junctions are not pushed down to the amorphous/crystalline silicon interface. Thus, end-of-range defects are located in a region below and spaced apart from the junctions, and the defects are not located in the activated source/drain regions. Junction leakage as a result of the end-of-range defects is thereby reduced.
摘要翻译：一种制造MOSFET半导体器件的方法包括：在栅极电极和衬底之间在衬底上形成栅极电极和栅极氧化物。然后将惰性掺杂剂注入衬底内以在衬底中形成非晶化的源极/漏极区域，延伸到明显大于预期结点深度的第一深度。非晶化源极/漏极区域注入源极/漏极掺杂剂，使得掺杂剂延伸到衬底中的第二深度小于第一深度的第二深度，在第一深度之上，并且与在第一深度处产生的端部范围缺陷区域间隔开非晶化过程。激光热退火使非晶区再结晶，激活源极/漏极区并形成源极/漏极结。因为朝向衬底主表面的再结晶前向速度大于激光热退火期间液体衬底中的掺杂剂原子速度，所以接合点不被推到非晶/硅晶界面。因此，距离范围缺陷位于与接合点下方和间隔开的区域中，并且缺陷不位于活化的源极/漏极区域中。因此，由于距离范围缺陷导致的结漏电减少。

106. 发明授权

US06664146B1 Integration of fully depleted and partially depleted field effect transistors formed in SOI technology 失效
标题翻译：在SOI技术中形成的完全耗尽和部分耗尽的场效应晶体管的集成
公开(公告)号：US06664146B1
公开(公告)日：2003-12-16
申请号：US09873170
申请日：2001-06-01
申请人： Bin Yu
发明人： Bin Yu
IPC分类号： H01L2184
CPC分类号： H01L21/76264 , H01L21/76267 , H01L21/76283 , H01L21/84 , H01L27/1203
摘要： For fabricating field effect transistors with a semiconductor substrate in SOI (semiconductor on insulator) technology, a first hardmask is formed on a first area of the semiconductor substrate, and a first dielectric forming dopant is implanted into a second area of the semiconductor substrate that is not covered by the first hardmask. The first hardmask is removed from the first area of the semiconductor substrate. A second hardmask is formed on the second area of the semiconductor substrate, and a second dielectric forming dopant is implanted into the first area of the semiconductor substrate that is not covered by the second hardmask. A thermal anneal is performed to form a first buried insulating structure from the second dielectric forming dopant reacting within the first area of the semiconductor substrate and to form a second buried insulating structure from the first dielectric forming dopant reacting within the second area of the semiconductor substrate. A first semiconductor structure remains on top of the first buried insulating structure and has a different thickness from a second semiconductor structure remaining on top of the second buried insulating structure.
摘要翻译：为了在SOI（绝缘体上半导体）技术中制造具有半导体衬底的场效应晶体管，在半导体衬底的第一区域上形成第一硬掩模，并且将第一电介质形成掺杂剂注入到半导体衬底的第二区域没有被第一个硬掩模覆盖。第一硬掩模从半导体衬底的第一区域去除。第二硬掩模形成在半导体衬底的第二区域上，并且第二电介质形成掺杂剂注入到半导体衬底的未被第二硬掩模覆盖的第一区域中。进行热退火，以形成第一掩埋绝缘结构，从第二电介质形成掺杂剂在半导体衬底的第一区域内反应，并形成第二掩埋绝缘结构，从第一电介质形成掺杂剂在半导体衬底的第二区域内反应。第一半导体结构保留在第一掩埋绝缘结构的顶部，并且具有与保留在第二掩埋绝缘结构的顶部上的第二半导体结构不同的厚度。

107. 发明授权

US06657276B1 Shallow trench isolation (STI) region with high-K liner and method of formation 有权
标题翻译：浅沟隔离（STI）区域具有高K衬垫和形成方法
公开(公告)号：US06657276B1
公开(公告)日：2003-12-02
申请号：US10163925
申请日：2002-06-06
申请人： Olov B. Karlsson , HaiHong Wang , Bin Yu , Zoran Krivokapic , Qi Xiang
发明人： Olov B. Karlsson , HaiHong Wang , Bin Yu , Zoran Krivokapic , Qi Xiang
IPC分类号： H01L2900
CPC分类号： H01L29/7842 , H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/78654
摘要： A shallow trench isolation region formed in a layer of semiconductor material. The shallow trench isolation region includes a trench formed in the layer of semiconductor material, the trench being defined by sidewalls and a bottom; a liner within the trench formed from a high-K material, the liner conforming to the sidewalls and bottom of the trench; and a fill section made from isolating material, and disposed within and conforming to the high-K liner. A method of forming the shallow trench isolation region is also disclosed.
摘要翻译：形成在半导体材料层中的浅沟槽隔离区。浅沟槽隔离区域包括形成在半导体材料层中的沟槽，沟槽由侧壁和底部限定; 由高K材料形成的沟槽内的衬垫，衬垫符合沟槽的侧壁和底部; 以及由隔离材料制成并填充并符合高K衬里的填充部分。还公开了形成浅沟槽隔离区域的方法。

108. 发明授权

US06645797B1 Method for forming fins in a FinFET device using sacrificial carbon layer 有权
标题翻译：在使用牺牲碳层的FinFET器件中形成翅片的方法
公开(公告)号：US06645797B1
公开(公告)日：2003-11-11
申请号：US10310926
申请日：2002-12-06
申请人： Matthew S. Buynoski , Srikanteswara Dakshina-Murthy , Cyrus E. Tabery , Haihong Wang , Chih-Yuh Yang , Bin Yu
发明人： Matthew S. Buynoski , Srikanteswara Dakshina-Murthy , Cyrus E. Tabery , Haihong Wang , Chih-Yuh Yang , Bin Yu
IPC分类号： H01L2184
CPC分类号： H01L29/785 , H01L29/66795
摘要： A method for forming a fin in a semiconductor device that includes a substrate, an insulating layer formed on the substrate, and a conductive layer formed on the insulating layer, includes forming a carbon layer over the conductive layer and forming a mask over the carbon layer. The method further includes etching the mask and carbon layer to form at least one structure, where the structure has a first width, reducing the width of the carbon layer in the at least one structure to a second width, depositing an oxide layer to surround the at least one structure, removing a portion of the oxide layer and the mask, removing the carbon layer to form an opening in a remaining portion of the oxide layer for each of the at least one structure, filling the at least one opening with conductive material, and removing the remaining portion of the oxide layer and a portion of the conductive layer to form the fin.
摘要翻译：一种在半导体器件中形成翅片的方法，包括：衬底，形成在衬底上的绝缘层和形成在绝缘层上的导电层，包括在导电层上形成碳层，并在碳层上形成掩模。该方法还包括蚀刻掩模和碳层以形成至少一种结构，其中结构具有第一宽度，将至少一个结构中的碳层的宽度减小到第二宽度，沉积氧化物层以围绕至少一个结构，去除所述氧化物层和所述掩模的一部分，除去所述碳层以在所述至少一个结构中的每一个结构的氧化物层的剩余部分中形成开口，用导电材料填充所述至少一个开口并且去除氧化物层的剩余部分和导电层的一部分以形成翅片。

109. 发明授权

US06555879B1 SOI device with metal source/drain and method of fabrication 有权
标题翻译：具有金属源/漏极的SOI器件及其制造方法
公开(公告)号：US06555879B1
公开(公告)日：2003-04-29
申请号：US10044247
申请日：2002-01-11
申请人： Zoran Krivokapic , Qi Xiang , Bin Yu
发明人： Zoran Krivokapic , Qi Xiang , Bin Yu
IPC分类号： H01L2976
CPC分类号： H01L21/28194 , H01L21/84 , H01L27/1203 , H01L29/4908 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A MOSFET and method of fabrication. The MOSFET includes a metal containing source and a metal containing drain; a semiconductor body having a thickness of less than about 15 nm disposed between the source and the drain and on top of an insulating layer, the insulating layer formed on a substrate; a gate electrode disposed over the body and defining a channel interposed between the source and the drain; and a gate dielectric made from a high-K material and separating the gate electrode and the body.
摘要翻译：一种MOSFET及其制造方法。 MOSFET包括含金属源和含金属的漏极; 设置在源极和漏极之间并且在绝缘层的顶部上具有小于约15nm的厚度的半导体本体，所述绝缘层形成在基板上; 栅电极，其设置在所述主体上并且限定插入在所述源极和所述漏极之间的沟道; 以及由高K材料制成并分离栅电极和主体的栅极电介质。

110. 发明授权

US06555437B1 Multiple halo implant in a MOSFET with raised source/drain structure 有权
标题翻译：具有升高的源极/漏极结构的MOSFET中的多个晕轮注入
公开(公告)号：US06555437B1
公开(公告)日：2003-04-29
申请号：US09844888
申请日：2001-04-27
申请人： Bin Yu
发明人： Bin Yu
IPC分类号： H01L21336
CPC分类号： H01L29/66492 , H01L21/26586 , H01L29/1083 , H01L29/41783 , H01L29/665 , H01L29/6653 , H01L29/66628
摘要： A method and device for improving the channel doping profile of deep-submicron field effect transistors and MOSFETs. The method involves forming a multi-graded lateral channel doping profile by dual halo implants annealed at different temperatures to improve the threshold voltage roll-off characteristics of MOSFETs of 50 nm or less. The method includes forming a spacer on the sidewalls of a gate, followed by forming source/drain regions by epitaxial growth followed by a deep source/drain implant and anneal. After removal of the spacer, the first angled deep halo implant through the space formed by removal of the spacer and a second annealing at a temperature lower than the first anneal occurs. A second angled halo implant and a third anneal at a temperature less than the second anneal is performed. The microelectronic chip is then silicided and the MOSFET is further completed.
摘要翻译：一种用于改善深亚微米场效应晶体管和MOSFET的沟道掺杂分布的方法和装置。该方法包括通过在不同温度下退火的双光晕植入物形成多梯度横向沟道掺杂分布，以改善50nm或更小的MOSFET的阈值电压滚降特性。该方法包括在栅极的侧壁上形成间隔物，随后通过外延生长随后进行深源极/漏极注入和退火来形成源极/漏极区域。在去除间隔物之后，通过去除间隔物形成的空间的第一倾斜的深晕注入和在低于第一退火的温度下进行第二次退火。执行第二倾斜的晕轮植入物和在小于第二退火的温度下的第三退火。然后将微电子芯片硅化并且MOSFET进一步完成。

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