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1. 发明授权

US06764908B1 Narrow width CMOS devices fabricated on strained lattice semiconductor substrates with maximized NMOS and PMOS drive currents 有权
标题翻译：窄带CMOS器件制造在具有最大NMOS和PMOS驱动电流的应变晶格半导体衬底上
公开(公告)号：US06764908B1
公开(公告)日：2004-07-20
申请号：US10173770
申请日：2002-06-19
申请人： Daniel Kadosh , Derick J. Wristers , Qi Xiang , Bin Yu
发明人： Daniel Kadosh , Derick J. Wristers , Qi Xiang , Bin Yu
IPC分类号： H01L21336
CPC分类号： H01L29/1054 , H01L21/823807
摘要： A method of manufacturing a semiconductor device comprises steps of: (a) providing a semiconductor substrate comprising an upper, tensilely strained lattice semiconductor layer and a lower, unstressed semiconductor layer; and (b) forming at least one MOS transistor on or within the tensilely strained lattice semiconductor layer, wherein the forming comprises a step of regulating the drive current of the at least one MOS transistor by adjusting the thickness of the tensilely strained lattice semiconductor layer. Embodiments include CMOS devices formed in substrates including a strained Si layer lattice-matched to a graded composition Si—Ge layer, wherein the thickness of the strained Si layer of each of the PMOS and NMOS transistors is adjusted to provide each transistor type with maximum drive current.
摘要翻译：一种制造半导体器件的方法包括以下步骤：（a）提供包括上部，拉伸应变晶格半导体层和下部未应力半导体层的半导体衬底; 和（b）在拉伸应变晶格半导体层上或其内形成至少一个MOS晶体管，其中所述形成包括通过调整拉伸应变晶格半导体层的厚度来调节所述至少一个MOS晶体管的驱动电流的步骤。实施例包括形成在包括与渐变组合物Si-Ge层晶格匹配的应变Si层的衬底中的CMOS器件，其中调节每个PMOS晶体管和NMOS晶体管的应变Si层的厚度以提供每个晶体管类型的最大驱动当前。

2. 发明授权

US06936506B1 Strained-silicon devices with different silicon thicknesses 有权
标题翻译：具有不同硅厚度的应变硅器件
公开(公告)号：US06936506B1
公开(公告)日：2005-08-30
申请号：US10442975
申请日：2003-05-22
申请人： James F. Buller , Derick J. Wristers , Qi Xiang , Bin Yu
发明人： James F. Buller , Derick J. Wristers , Qi Xiang , Bin Yu
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/10
CPC分类号： H01L21/823807 , H01L29/1054
摘要： A method of manufacturing a semiconductor device includes providing a strained-silicon semiconductor layer over a silicon germanium layer, and partially removing a first portion of the strained-silicon layer. The strained-silicon layer includes the first portion and a second portion, and a thickness of the second portion is greater than a thickness of the first portion. Initially, the first and second portions of the strained-silicon layer initially can have the same thickness. A p-channel transistor is formed over the first portion, and a n-channel transistor is formed over the second portion. A semiconductor device is also disclosed.
摘要翻译：制造半导体器件的方法包括在硅锗层上提供应变硅半导体层，并部分去除应变硅层的第一部分。应变硅层包括第一部分和第二部分，第二部分的厚度大于第一部分的厚度。最初，应变硅层的第一和第二部分最初可以具有相同的厚度。在第一部分上形成p沟道晶体管，并且在第二部分上形成n沟道晶体管。还公开了一种半导体器件。

3. 发明授权

US06245649B1 Method for forming a retrograde impurity profile 有权
标题翻译：形成逆行杂质分布的方法
公开(公告)号：US06245649B1
公开(公告)日：2001-06-12
申请号：US09251923
申请日：1999-02-17
申请人： James F. Buller , Jon D. Cheek , Daniel Kadosh , Derick J. Wristers , H. Jim Fulford
发明人： James F. Buller , Jon D. Cheek , Daniel Kadosh , Derick J. Wristers , H. Jim Fulford
IPC分类号： H01L2104
CPC分类号： H01L29/105 , H01L21/2652
摘要： A method for forming a retrograde impurity profile in a semiconducting substrate is provided. The method comprises forming a sacrificial layer having a thickness in the range of about 10 Å to about 150 Å on the surface of a semiconducting substrate. Thereafter, an ion implantation process is performed wherein dopant impurity ions are directed through the sacrificial layer and into the semiconducting substrate under conditions effective to form a retrograde impurity profile in the semiconducting substrate.
摘要翻译：提供了一种在半导体衬底中形成逆向杂质分布的方法。该方法包括在半导体衬底的表面上形成具有在大约至大约的范围内的厚度的牺牲层。此后，进行离子注入工艺，其中掺杂杂质离子在有效地在半导体衬底中形成逆向杂质分布的条件下引导通过牺牲层并进入半导体衬底。

4. 发明授权

US6150695A Multilevel transistor formation employing a local substrate formed within a shallow trench 失效
标题翻译：使用在浅沟槽内形成的局部衬底的多晶体管形成
公开(公告)号：US6150695A
公开(公告)日：2000-11-21
申请号：US741812
申请日：1996-10-30
申请人： Mark Gardner , Daniel Kadosh , Derick J. Wristers
发明人： Mark Gardner , Daniel Kadosh , Derick J. Wristers
IPC分类号： H01L21/822 , H01L27/06 , H01L27/01
CPC分类号： H01L27/0688 , H01L21/8221
摘要： A dual level transistor and a fabrication technique. The dual level transistor is an integrated circuit in which a first transistor is formed on an upper surface of a global dielectric and a second transistor is formed on an upper surface of a first local substrate such that the second transistor is vertically displaced from the first transistor. The first local substrate is formed within a local trench etched into a first inter-substrate dielectric. By vertically displacing the first and second transistors, the lateral separation required to isolate first and second transistors in a typical single plane process is eliminated. The integrated circuit includes a semiconductor global substrate and a first transistor formed on the global substrate. The first transistor includes a first gate dielectric formed on an upper surface of the global substrate and a first conductive gate structure formed on an upper surface of the first dielectric. The integrated circuit further includes a first inter-substrate dielectric that is formed on the first conductive gate structure and the global substrate. The first inter-substrate dielectric includes a local trench. A first local substrate is formed within the local trench. A second transistor is located within the first local substrate. The second transistor includes a second gate dielectric formed on an upper surface of the first local substrate and a second conductive gate structure formed on an upper surface of the second gate dielectric.
摘要翻译：双级晶体管和制造技术。双电平晶体管是集成电路，其中第一晶体管形成在全局电介质的上表面上，并且第二晶体管形成在第一局部衬底的上表面上，使得第二晶体管垂直从第一晶体管。第一局部衬底形成在蚀刻到第一衬底间电介质中的局部沟槽内。通过垂直移位第一和第二晶体管，消除了在典型的单平面工艺中隔离第一和第二晶体管所需的横向分离。集成电路包括半导体全局基板和形成在全局基板上的第一晶体管。第一晶体管包括形成在全局衬底的上表面上的第一栅极电介质和形成在第一电介质的上表面上的第一导电栅极结构。集成电路还包括形成在第一导电栅极结构和全局基板上的第一基板间电介质。第一基板间电介质包括局部沟槽。第一局部衬底形成在局部沟槽内。第二晶体管位于第一局部衬底内。第二晶体管包括形成在第一局部衬底的上表面上的第二栅极电介质和形成在第二栅极电介质的上表面上的第二导电栅极结构。

5. 发明授权

US6051459A Method of making N-channel and P-channel IGFETs using selective doping and activation for the N-channel gate 失效
标题翻译：使用N沟道栅极的选择性掺杂和激活来制造N沟道和P沟道IGFET的方法
公开(公告)号：US6051459A
公开(公告)日：2000-04-18
申请号：US803730
申请日：1997-02-21
申请人： Mark I. Gardner , Daniel Kadosh , Frederick N. Hause , Derick J. Wristers
发明人： Mark I. Gardner , Daniel Kadosh , Frederick N. Hause , Derick J. Wristers
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： A method of making N-channel and P-channel IGFETs is disclosed. The method includes providing a semiconductor substrate with N-type and P-type active regions, forming a gate material over the N-type and P-type active regions, forming a first masking layer over the gate material, wherein the first masking layer includes an opening above a first portion of the gate material over the P-type active region, and the first masking layer covers a second portion of the gate material over the N-type active region, introducing an N-type dopant into the first portion of the gate material without introducing the N-type dopant into the second portion of the gate material, applying a thermal cycle to drive-in and activate the N-type dopant in the first portion of the gate material before introducing any doping into the second portion of the gate material, before introducing any source/drain doping into the N-type active region, and before introducing any source/drain doping into the P-type active region, forming a second masking layer over the gate material, wherein the second masking layer covers portions of the first and second portions of the gate material, applying an etch to form first and second gates from unetched portions of the first and second portions of the gate material, respectively, and forming an N-type source and drain in the P-type active region and forming a P-type source and drain in the N-type active region. Advantageously, a dopant in the gate for the N-channel IGFET can be driven-in and activated at a relatively high temperature without subjecting any source/drain doping to this temperature.
摘要翻译：公开了制造N沟道和P沟道IGFET的方法。该方法包括提供具有N型和P型有源区的半导体衬底，在N型和P型有源区上形成栅极材料，在栅极材料上形成第一掩模层，其中第一掩模层包括在P型有源区上方的栅极材料的第一部分上方的开口，并且第一掩模层覆盖N型有源区上的栅极材料的第二部分，将N型掺杂剂引入到第一部分栅极材料，而不将N型掺杂剂引入栅极材料的第二部分中，在引入任何掺杂到第二部分之前施加热循环以驱动和激活栅极材料的第一部分中的N型掺杂剂在向N型有源区域引入任何源极/漏极掺杂之前，在向P型有源区域引入任何源极/漏极掺杂之前，在栅极材料上形成第二掩模层，在第二掩模层中，分别覆盖栅极材料的第一和第二部分的部分，施加蚀刻以分别从栅极材料的第一和第二部分的未蚀刻部分形成第一和第二栅极，并形成N型源极并在P型有源区中漏极，并在N型有源区中形成P型源极和漏极。有利的是，用于N沟道IGFET的栅极中的掺杂剂可以被驱入并在相对较高的温度下被激活，而不会对该温度进行任何源极/漏极掺杂。

6. 发明授权

US6096591A Method of making an IGFET and a protected resistor with reduced processing steps 失效
标题翻译：制造IGFET和受保护电阻的方法，减少加工步骤
公开(公告)号：US6096591A
公开(公告)日：2000-08-01
申请号：US911746
申请日：1997-08-15
申请人： Mark I. Gardner , Daniel Kadosh , Derick J. Wristers
发明人： Mark I. Gardner , Daniel Kadosh , Derick J. Wristers
IPC分类号： H01L21/02 , H01L27/06 , H01L21/8234
CPC分类号： H01L28/20 , H01L27/0629
摘要： A method of making an IGFET and a protected resistor includes providing a semiconductor substrate with an active region and a resistor region, forming a gate over the active region, forming a diffused resistor in the resistor region, forming an insulating layer over the gate and the diffused resistor, forming a masking layer over the insulating layer that covers the resistor region and includes an opening above the active region, applying an etch using the masking layer as an etch mask so that unetched portions of the insulating layer over the active region form spacers in close proximity to opposing sidewalls of the gate and an unetched portion of the insulating layer over the resistor region forms a resistor-protect insulator, and forming a source and a drain in the active region. In this manner, a single insulating layer provides both sidewall spacers for the gate and a resistor-protect insulator for the diffused resistor.
摘要翻译：制造IGFET和受保护电阻器的方法包括向半导体衬底提供有源区和电阻区，在有源区上形成栅极，在电阻区中形成扩散电阻，在栅极上形成绝缘层，扩散电阻器，在覆盖电阻器区域的绝缘层上形成掩模层，并且在有源区域上方包括开口，使用掩模层施加蚀刻作为蚀刻掩模，使得在有源区域上的绝缘层的未蚀刻部分形成间隔物靠近栅极的相对侧壁并且在电阻器区域上的绝缘层的未蚀刻部分形成电阻器保护绝缘体，并且在有源区域中形成源极和漏极。以这种方式，单个绝缘层提供用于栅极的两个侧壁间隔件和用于扩散电阻器的电阻保护绝缘体。

7. 发明授权

US5935766A Method of forming a conductive plug in an interlevel dielectric 失效
标题翻译：在层间电介质中形成导电塞的方法
公开(公告)号：US5935766A
公开(公告)日：1999-08-10
申请号：US908487
申请日：1997-08-07
申请人： Jon Cheek , Daniel Kadosh , Derick J. Wristers
发明人： Jon Cheek , Daniel Kadosh , Derick J. Wristers
IPC分类号： H01L21/768 , H01L23/522 , G03F7/00 , H01L21/02
CPC分类号： H01L23/5226 , H01L21/76838 , H01L2924/0002
摘要： A method of forming a conductive plug in an interlevel dielectric includes forming a lower dielectric layer over a semiconductor substrate. A first etch mask is formed over the lower dielectric layer and is patterned using a reticle. A first etch is applied through an opening in the first etch mask to form an opening in the lower dielectric layer. A lower conductor is formed in the opening in the lower dielectric layer. A conducting layer is formed over the lower dielectric layer and the lower conductor. A second etch mask is formed over the conducting layer and is patterned using the reticle. A second etch is applied through an opening in the second etch mask to form a contact pad from an unetched portion of the conducting layer. An upper dielectric layer is formed over the lower dielectric layer and the contact pad. A third etch mask is formed over the upper dielectric layer and is patterned using the reticle. A third etch is applied through an opening in the third etch mask to form an opening in the upper dielectric layer. An upper conductor is formed in the opening in the upper dielectric layer. As a result, the conductive plug includes the upper and lower conductors and the contact pad, and the interlevel dielectric includes the upper and lower dielectric layers.
摘要翻译：在层间电介质中形成导电插塞的方法包括在半导体衬底上形成下介电层。在下介电层上形成第一蚀刻掩模，并使用掩模版进行图案化。通过第一蚀刻掩模中的开口施加第一蚀刻，以在下介电层中形成开口。下导体形成在下电介质层的开口中。在下介电层和下导体上形成导电层。在导电层上形成第二蚀刻掩模，并使用掩模版进行图案化。通过第二蚀刻掩模中的开口施加第二蚀刻，以从导电层的未蚀刻部分形成接触焊盘。在下电介质层和接触焊盘上形成上介电层。在上电介质层上形成第三蚀刻掩模，并使用掩模版进行图案化。通过第三蚀刻掩模中的开口施加第三蚀刻，以在上介电层中形成开口。上导体形成在上电介质层的开口中。结果，导电插塞包括上导体和下导体和接触垫，并且层间电介质包括上和下介电层。

8. 发明授权

US5885877A Composite gate electrode incorporating dopant diffusion-retarding barrier layer adjacent to underlying gate dielectric 失效
标题翻译：复合栅电极，其与掺杂剂扩散阻滞层结合，邻近底层栅极电介质
公开(公告)号：US5885877A
公开(公告)日：1999-03-23
申请号：US837581
申请日：1997-04-21
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Daniel Kadosh , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Daniel Kadosh , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/28 , H01L29/49 , H01L21/336 , H01L21/3205
CPC分类号： H01L21/28035 , H01L29/4916
摘要： A composite gate electrode layer incorporates a diffusion-retarding barrier layer disposed at the bottom of the gate electrode layer to reduce the amount of dopant which diffuses into the gate dielectric layer from the gate electrode layer. A lower nitrogen-containing gate electrode layer provides a diffusion-retarding barrier layer against dopant diffusion into the gate dielectric layer disposed therebelow, and an upper gate electrode layer is formed upon the lower layer and is doped to form a highly conductive layer. Together the first and second gate electrode layers form a composite gate electrode layer which incorporates a diffusion-retarding barrier layer adjacent to the underlying gate dielectric layer. The barrier layer may be formed by annealing a first polysilicon layer in a nitrogen-containing ambient, such as N.sub.2, NO, N.sub.2 O, and NH.sub.3, by implanting a nitrogen-containing material, such as elemental or molecular nitrogen, into a first polysilicon layer, and by in-situ depositing a nitrogen-doped first polysilicon layer. Diffusion of dopants into the gate dielectric layer may be retarded, as most dopant atoms are prevented from diffusing from the composite gate electrode layer at all. In addition, the nitrogen concentration within the gate dielectric layer, particularly at or near the substrate interface, may be maintained at lower concentrations than otherwise necessary to prevent dopant diffusion into the underlying substrate. The present invention is particularly well suited to thin gate dielectrics, such as a those having a thickness less than approximately 60 .ANG. when using a p-type dopant, such as boron.
摘要翻译：复合栅极电极层包括设置在栅极电极层底部的扩散阻挡层，以减少从栅极电极层扩散到栅极电介质层中的掺杂剂的量。下部含氮栅电极层提供阻止扩散阻挡层，以阻止掺杂剂扩散到设置在其下方的栅介质层中，并且在下层上形成上栅极电极层，并且被掺杂以形成高导电层。第一和第二栅极电极层一起形成复合栅极电极层，该复合栅极电极层包含与下面的栅极电介质层相邻的扩散阻滞阻挡层。通过将含氮材料（例如元素或分子氮）注入到第一多晶硅层中，可以通过在氮气环境如N 2，NO，N 2 O和NH 3中退火第一多晶硅层来形成阻挡层，并通过原位沉积氮掺杂的第一多晶硅层。完全可以防止掺杂剂扩散到栅极电介质层中，因为大多数掺杂剂原子被阻止从复合栅极电极层扩散。此外，栅极电介质层内，特别是在衬底界面处或附近的氮浓度可以保持在比防止掺杂剂扩散到下面的衬底中所必需的更低的浓度。本发明特别适用于薄栅电介质，例如当使用诸如硼的p型掺杂剂时厚度小于约60的薄电介质。

9. 发明授权

US5656518A Method for fabrication of a non-symmetrical transistor 失效
标题翻译：制造非对称晶体管的方法
公开(公告)号：US5656518A
公开(公告)日：1997-08-12
申请号：US713386
申请日：1996-09-13
申请人： Mark I. Gardner , Daniel Kadosh , Derick J. Wristers
发明人： Mark I. Gardner , Daniel Kadosh , Derick J. Wristers
IPC分类号： H01L21/336 , H01L29/78 , H01L21/8234
CPC分类号： H01L29/66659 , H01L29/7835
摘要： In the present invention, a method for fabrication of a non-symmetrical LDD-IGFET is described. The present invention includes a gate insulator and a gate electrode, such as a polysilicon, formed over a semiconductor substrate, the gate electrode having a top surface and opposing first and second sidewalls. A first dopant is implanted to provide a lightly doped drain region substantially aligned with the second sidewall. An oxide layer provides first and second sidewall oxide regions adjacent the first and second sidewalls, respectively. The first sidewall oxide region is isolated using a nitride layer having a window which exposes the second sidewall oxide region. Thermal oxidation is applied to the second sidewall oxide region wherein the size of the second sidewall oxide region increases while the size of the first sidewall oxide region remains substantially constant. The first sidewall oxide region is then exposed by removing the nitride layer and a second dopant is implanted to provide a heavily doped drain region substantially aligned with the outside edge of the second sidewall oxide region and a heavily doped source region.
摘要翻译：在本发明中，描述了用于制造非对称LDD-IGFET的方法。本发明包括形成在半导体衬底上的栅极绝缘体和诸如多晶硅的栅电极，栅电极具有顶表面和相对的第一和第二侧壁。植入第一掺杂剂以提供基本上与第二侧壁对准的轻掺杂漏极区。氧化物层分别提供与第一和第二侧壁相邻的第一和第二侧壁氧化物区域。使用具有暴露第二侧壁氧化物区域的窗口的氮化物层来隔离第一侧壁氧化物区域。热氧化被施加到第二侧壁氧化物区域，其中第二侧壁氧化物区域的尺寸增加，而第一侧壁氧化物区域的尺寸保持基本恒定。然后通过去除氮化物层来暴露第一侧壁氧化物区域，并且注入第二掺杂剂以提供与第二侧壁氧化物区域的外边缘基本对准的重掺杂漏极区域和重掺杂源极区域。

10. 发明授权

US06707106B1 Semiconductor device with tensile strain silicon introduced by compressive material in a buried oxide layer 有权
标题翻译：具有由埋置氧化物层中的压缩材料引入的拉伸应变硅的半导体器件
公开(公告)号：US06707106B1
公开(公告)日：2004-03-16
申请号：US10272979
申请日：2002-10-18
申请人： Derick J. Wristers , Qi Xiang , James F. Buller
发明人： Derick J. Wristers , Qi Xiang , James F. Buller
IPC分类号： H01L2701
CPC分类号： H01L29/78696 , H01L29/1054 , H01L29/66772 , H01L29/7846 , H01L29/78603
摘要： A semiconductor device is provided with the high-speed capabilities of silicon on insulator (SOI) and strained silicon technologies, without requiring the formation of a silicon germanium layer. A layer of compressive material is formed on a SOI semiconductor substrate to induce strain in the overlying silicon layer. The compressive materials include silicon oxynitride, phosphorous, silicon nitride, and boron/phosphorous doped silica glass.
摘要翻译：半导体器件具有绝缘体上硅（SOI）和应变硅技术的高速能力，而不需要形成硅锗层。在SOI半导体衬底上形成一层压缩材料，以在上层硅层中引起应变。压缩材料包括氮氧化硅，磷，氮化硅和掺杂硼/磷的二氧化硅玻璃。

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