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1. 发明授权

US06764908B1 Narrow width CMOS devices fabricated on strained lattice semiconductor substrates with maximized NMOS and PMOS drive currents 有权
标题翻译：窄带CMOS器件制造在具有最大NMOS和PMOS驱动电流的应变晶格半导体衬底上
公开(公告)号：US06764908B1
公开(公告)日：2004-07-20
申请号：US10173770
申请日：2002-06-19
申请人： Daniel Kadosh , Derick J. Wristers , Qi Xiang , Bin Yu
发明人： Daniel Kadosh , Derick J. Wristers , Qi Xiang , Bin Yu
IPC分类号： H01L21336
CPC分类号： H01L29/1054 , H01L21/823807
摘要： A method of manufacturing a semiconductor device comprises steps of: (a) providing a semiconductor substrate comprising an upper, tensilely strained lattice semiconductor layer and a lower, unstressed semiconductor layer; and (b) forming at least one MOS transistor on or within the tensilely strained lattice semiconductor layer, wherein the forming comprises a step of regulating the drive current of the at least one MOS transistor by adjusting the thickness of the tensilely strained lattice semiconductor layer. Embodiments include CMOS devices formed in substrates including a strained Si layer lattice-matched to a graded composition Si—Ge layer, wherein the thickness of the strained Si layer of each of the PMOS and NMOS transistors is adjusted to provide each transistor type with maximum drive current.
摘要翻译：一种制造半导体器件的方法包括以下步骤：（a）提供包括上部，拉伸应变晶格半导体层和下部未应力半导体层的半导体衬底; 和（b）在拉伸应变晶格半导体层上或其内形成至少一个MOS晶体管，其中所述形成包括通过调整拉伸应变晶格半导体层的厚度来调节所述至少一个MOS晶体管的驱动电流的步骤。实施例包括形成在包括与渐变组合物Si-Ge层晶格匹配的应变Si层的衬底中的CMOS器件，其中调节每个PMOS晶体管和NMOS晶体管的应变Si层的厚度以提供每个晶体管类型的最大驱动当前。

2. 发明授权

US07417250B1 Strained-silicon device with different silicon thicknesses 有权
标题翻译：具有不同硅厚度的应变硅器件
公开(公告)号：US07417250B1
公开(公告)日：2008-08-26
申请号：US11151550
申请日：2005-06-14
申请人： James F. Buller , Derick J Wristers , Qi Xiang , Bin Yu
发明人： James F. Buller , Derick J Wristers , Qi Xiang , Bin Yu
IPC分类号： H01L29/04
CPC分类号： H01L21/823807 , H01L29/1054
摘要： A method of manufacturing a semiconductor device includes providing a strained-silicon semiconductor layer over a silicon germanium layer, and partially removing a first portion of the strained-silicon layer. The strained-silicon layer includes the first portion and a second portion, and a thickness of the second portion is greater than a thickness of the first portion. Initially, the first and second portions of the strained-silicon layer initially can have the same thickness. A p-channel transistor is formed over the first portion, and a n-channel transistor is formed over the second portion. A semiconductor device is also disclosed.
摘要翻译：制造半导体器件的方法包括在硅锗层上提供应变硅半导体层，并部分去除应变硅层的第一部分。应变硅层包括第一部分和第二部分，第二部分的厚度大于第一部分的厚度。最初，应变硅层的第一和第二部分最初可以具有相同的厚度。在第一部分上形成p沟道晶体管，并且在第二部分上形成n沟道晶体管。还公开了一种半导体器件。

3. 发明授权

US06936506B1 Strained-silicon devices with different silicon thicknesses 有权
标题翻译：具有不同硅厚度的应变硅器件
公开(公告)号：US06936506B1
公开(公告)日：2005-08-30
申请号：US10442975
申请日：2003-05-22
申请人： James F. Buller , Derick J. Wristers , Qi Xiang , Bin Yu
发明人： James F. Buller , Derick J. Wristers , Qi Xiang , Bin Yu
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/10
CPC分类号： H01L21/823807 , H01L29/1054
摘要： A method of manufacturing a semiconductor device includes providing a strained-silicon semiconductor layer over a silicon germanium layer, and partially removing a first portion of the strained-silicon layer. The strained-silicon layer includes the first portion and a second portion, and a thickness of the second portion is greater than a thickness of the first portion. Initially, the first and second portions of the strained-silicon layer initially can have the same thickness. A p-channel transistor is formed over the first portion, and a n-channel transistor is formed over the second portion. A semiconductor device is also disclosed.
摘要翻译：制造半导体器件的方法包括在硅锗层上提供应变硅半导体层，并部分去除应变硅层的第一部分。应变硅层包括第一部分和第二部分，第二部分的厚度大于第一部分的厚度。最初，应变硅层的第一和第二部分最初可以具有相同的厚度。在第一部分上形成p沟道晶体管，并且在第二部分上形成n沟道晶体管。还公开了一种半导体器件。

4. 发明授权

US06707106B1 Semiconductor device with tensile strain silicon introduced by compressive material in a buried oxide layer 有权
标题翻译：具有由埋置氧化物层中的压缩材料引入的拉伸应变硅的半导体器件
公开(公告)号：US06707106B1
公开(公告)日：2004-03-16
申请号：US10272979
申请日：2002-10-18
申请人： Derick J. Wristers , Qi Xiang , James F. Buller
发明人： Derick J. Wristers , Qi Xiang , James F. Buller
IPC分类号： H01L2701
CPC分类号： H01L29/78696 , H01L29/1054 , H01L29/66772 , H01L29/7846 , H01L29/78603
摘要： A semiconductor device is provided with the high-speed capabilities of silicon on insulator (SOI) and strained silicon technologies, without requiring the formation of a silicon germanium layer. A layer of compressive material is formed on a SOI semiconductor substrate to induce strain in the overlying silicon layer. The compressive materials include silicon oxynitride, phosphorous, silicon nitride, and boron/phosphorous doped silica glass.
摘要翻译：半导体器件具有绝缘体上硅（SOI）和应变硅技术的高速能力，而不需要形成硅锗层。在SOI半导体衬底上形成一层压缩材料，以在上层硅层中引起应变。压缩材料包括氮氧化硅，磷，氮化硅和掺杂硼/磷的二氧化硅玻璃。

5. 发明授权

US06727534B1 Electrically programmed MOS transistor source/drain series resistance 有权
标题翻译：电子编程MOS晶体管源极/漏极串联电阻
公开(公告)号：US06727534B1
公开(公告)日：2004-04-27
申请号：US10022847
申请日：2001-12-20
申请人： James F. Buller , Qi Xiang , Derick J. Wristers
发明人： James F. Buller , Qi Xiang , Derick J. Wristers
IPC分类号： H01L2979
CPC分类号： H01L29/4983 , H01L29/42376 , H01L29/66484 , H01L29/6656
摘要： High-speed MOS transistors are provided by forming a conductive layer embedded in transistor gate sidewall spacers. The embedded conductive layer is electrically insulated from the gate electrode and the source/drain regions of the transistor. The embedded conductive layer is positioned over the source/drain extensions and causes charge to accumulate in the source/drain extensions lowering the series resistance of the source/drain regions.
摘要翻译：通过形成嵌入在晶体管栅极侧壁间隔物中的导电层来提供高速MOS晶体管。嵌入式导电层与晶体管的栅极电极和源极/漏极区域电绝缘。嵌入的导电层位于源极/漏极延伸部分上方，并使电荷累积在源极/漏极延伸部中，从而降低源极/漏极区域的串联电阻。

6. 发明授权

US07091097B1 End-of-range defect minimization in semiconductor device 有权
标题翻译：半导体器件的范围内缺陷最小化
公开(公告)号：US07091097B1
公开(公告)日：2006-08-15
申请号：US10933424
申请日：2004-09-03
申请人： Eric N. Paton , Qi Xiang , Cyrus E. Tabery , Bin Yu , Robert B. Ogle
发明人： Eric N. Paton , Qi Xiang , Cyrus E. Tabery , Bin Yu , Robert B. Ogle
IPC分类号： H01L21/336
CPC分类号： H01L21/268 , H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L29/6659 , H01L29/7833
摘要： A method of fabricating a semiconductor device comprises forming a gate electrode over a substrate and forming deep amorphous regions within the substrate. And implanting dopants to form deep source/drain regions at a depth less than that of the deep amorphous regions, partially re-crystallizing portions of the deep amorphous regions to reduce their depth, and re-crystallizing the reduced amorphous regions to form activated final source/drain regions.
摘要翻译：制造半导体器件的方法包括在衬底上形成栅电极并在衬底内形成深非晶区域。并且注入掺杂剂以在深非晶区域的深度处形成深的源极/漏极区域，部分地重新结晶深非晶区域的部分以减小它们的深度，并且将还原的非晶区域再结晶以形成激活的最终光源 /漏区。

7. 发明申请

US20050073022A1 Shallow trench isolation (STI) region with high-K liner and method of formation 失效
标题翻译：浅沟隔离（STI）区域具有高K衬垫和形成方法
公开(公告)号：US20050073022A1
公开(公告)日：2005-04-07
申请号：US10642916
申请日：2003-08-18
申请人： Olov Karlsson , HaiHong Wang , Bin Yu , Zoran Krivokapic , Qi Xiang
发明人： Olov Karlsson , HaiHong Wang , Bin Yu , Zoran Krivokapic , Qi Xiang
IPC分类号： H01L21/762 , H01L21/84 , H01L27/12 , H01L29/786 , H01L29/00
CPC分类号： H01L29/7842 , H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/78654
摘要： A shallow trench isolation region formed in a layer of semiconductor material. The shallow trench isolation region includes a trench formed in the layer of semiconductor material, the trench being defined by sidewalls and a bottom; a liner within the trench formed from a high-K material, the liner conforming to the sidewalls and bottom of the trench; and a fill section made from isolating material, and disposed within and conforming to the high-K liner. A method of forming the shallow trench isolation region is also disclosed.
摘要翻译：形成在半导体材料层中的浅沟槽隔离区。浅沟槽隔离区域包括形成在半导体材料层中的沟槽，沟槽由侧壁和底部限定; 由高K材料形成的沟槽内的衬垫，衬垫符合沟槽的侧壁和底部; 以及由隔离材料制成并填充并符合高K衬里的填充部分。还公开了形成浅沟槽隔离区域的方法。

8. 发明授权

US06743689B1 Method of fabrication SOI devices with accurately defined monocrystalline source/drain extensions 失效
标题翻译：制造具有精确定义的单晶源极/漏极延伸的SOI器件的方法
公开(公告)号：US06743689B1
公开(公告)日：2004-06-01
申请号：US10341427
申请日：2003-01-14
申请人： Eric N. Paton , Robert B. Ogle , Cyrus E. Tabery , Qi Xiang , Bin Yu
发明人： Eric N. Paton , Robert B. Ogle , Cyrus E. Tabery , Qi Xiang , Bin Yu
IPC分类号： H01L21336
CPC分类号： H01L21/26513 , H01L21/26506 , H01L21/2658 , H01L21/268 , H01L29/458 , H01L29/66492 , H01L29/665 , H01L29/6653 , H01L29/66553 , H01L29/66772 , H01L29/78612 , H01L29/78621
摘要： Semiconductor devices comprising fully and partially depleted SOI transistors with accurately defined monocrystalline or substantially completely monocrystalline silicon source/drain extensions are fabricated by selectively pre-amorphizing intended source/drain extensions, ion implanting dopants into the pre-amorphized regions and laser thermal annealing to effect crystallization and activation of the source/drain extensions. Embodiments include forming a gate electrode over an SOI substrate with a gate dielectric layer therebetween, forming silicon nitride sidewall spacers on the side surfaces of the gate electrode, forming source/drain regions, forming a thermal oxide layer on the gate electrode and on the source/drain regions, removing the silicon nitride sidewall spacers, pre-amorphizing the intended source/drain extension regions, ion implanting impurities into the pre-amorphized regions and laser thermal annealing to crystallize the pre-amorphized regions and to activate the source/drain extensions.
摘要翻译：包括具有精确定义的单晶或基本上完全单晶硅源极/漏极延伸的完全和部分耗尽的SOI晶体管的半导体器件通过将预期的源/漏延伸，离子注入掺杂剂预先非晶化以进行预非晶化区域和激光热退火来制造源/漏扩展的结晶和激活。实施例包括在SOI衬底之上形成栅极电介质层，在栅电极之间形成氮化硅侧壁间隔物，形成源/漏区，在栅电极和源极上形成热氧化层漏极区域，去除氮化硅侧壁间隔物，使预期的源极/漏极延伸区域预非晶化，离子注入杂质到预非晶化区域和激光热退火以使预非晶化区域结晶并激活源极/漏极延伸部分。

9. 发明授权

US06660578B1 High-K dielectric having barrier layer for P-doped devices and method of fabrication 有权
标题翻译：具有用于P掺杂器件的阻挡层的高K电介质和制造方法
公开(公告)号：US06660578B1
公开(公告)日：2003-12-09
申请号：US10118274
申请日：2002-04-08
申请人： Olov Karlsson , Qi Xiang , HaiHong Wang , Bin Yu , Zoran Krivokapic
发明人： Olov Karlsson , Qi Xiang , HaiHong Wang , Bin Yu , Zoran Krivokapic
IPC分类号： H01L218238
CPC分类号： H01L27/1203 , H01L21/84
摘要： A semiconductor device, a semiconductor wafer and a method of forming a semiconductor wafer where a barrier layer is used to inhibit P-type ion-penetration into a dielectric layer made from a high-K material.
摘要翻译：半导体器件，半导体晶片和形成半导体晶片的方法，其中阻挡层用于抑制由高K材料制成的电介质层中的P型离子渗透。

10. 发明授权

US06984569B2 Shallow trench isolation (STI) region with high-K liner and method of formation 失效
公开(公告)号：US06984569B2
公开(公告)日：2006-01-10
申请号：US10642916
申请日：2003-08-18
申请人： Olov B. Karlsson , HaiHong Wang , Bin Yu , Zoran Krivokapic , Qi Xiang
发明人： Olov B. Karlsson , HaiHong Wang , Bin Yu , Zoran Krivokapic , Qi Xiang
IPC分类号： H01L21/8224
CPC分类号： H01L29/7842 , H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/78654
摘要： A shallow trench isolation region formed in a layer of semiconductor material. The shallow trench isolation region includes a trench formed in the layer of semiconductor material, the trench being defined by sidewalls and a bottom; a liner within the trench formed from a high-K material, the liner conforming to the sidewalls and bottom of the trench; and a fill section made from isolating material, and disposed within and conforming to the high-K liner. A method of forming the shallow trench isolation region is also disclosed.

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